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change timer 0 to 2

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master
agsler 3 years ago
parent 3f30ee765f
commit be06b3f380
1 changed files with 7 additions and 7 deletions
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14
modbus-master.c
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@ -5,18 +5,18 @@
#define receiveOkay (modbusGetBusState() & (1<<ReceiveCompleted)) #define receiveOkay (modbusGetBusState() & (1<<ReceiveCompleted))
void timer0_init() void timer2_init()
{ {
TCCR0A = (1<<WGM01); //TIMER0 SET-UP: CTC MODE TCCR2A = (1<<WGM21); //TIMER0 SET-UP: CTC MODE
TCCR0B|=(1<<CS01); //prescaler 8 TCCR2B|=(1<<CS21); //prescaler 8
OCR0A = 200; OCR2A = 200;
TIMSK0|=(1<<OCIE0A); TIMSK2|=(1<<OCIE2A);
} }
void modbus_master_init(){ void modbus_master_init(){
modbusSetAddress(1); //better set this to sth. modbusSetAddress(1); //better set this to sth.
modbusInit(); modbusInit();
timer0_init(); // modbus tick timer timer2_init(); // modbus tick timer
} }
int8_t wait_receive(uint8_t len, uint16_t dest[], uint8_t timeout){ int8_t wait_receive(uint8_t len, uint16_t dest[], uint8_t timeout){
@ -121,6 +121,6 @@ void writeCoil(uint8_t slaveid, uint16_t address, uint16_t value) {
modbusSendMessage(5); modbusSendMessage(5);
} }
ISR(TIMER0_COMPA_vect) { //this ISR is called 9765.625 times per second ISR(TIMER2_COMPA_vect) { //this ISR is called 9765.625 times per second
modbusTickTimer(); modbusTickTimer();
} }