Add [10_m1284p_WIZNET_HTTPServer_RAM_pages] prj
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maxxir_w
132
10_m1284p_WIZNET_HTTPServer_RAM_pages/spi.h
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132
10_m1284p_WIZNET_HTTPServer_RAM_pages/spi.h
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/*
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* Copyright (c) 2010, Swedish Institute of Computer Science.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/**
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* \file
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* Basic SPI macros
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* \author
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* Joakim Eriksson <joakime@sics.se>
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* Niclas Finne <nfi@sics.se>
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*/
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#ifndef SPI_H_
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#define SPI_H_
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/* SPI input/output registers. */
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#define SPI_TXBUF SPDR
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#define SPI_RXBUF SPDR
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#define BV(bitno) _BV(bitno)
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#define SPI_WAITFOREOTx() do { while (!(SPSR & BV(SPIF))); } while (0)
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#define SPI_WAITFOREORx() do { while (!(SPSR & BV(SPIF))); } while (0)
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//M128
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//#define SCK 1 /* - Output: SPI Serial Clock (SCLK) - ATMEGA128 PORTB, PIN1 */
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//#define MOSI 2 /* - Output: SPI Master out - slave in (MOSI) - ATMEGA128 PORTB, PIN2 */
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//#define MISO 3 /* - Input: SPI Master in - slave out (MISO) - ATMEGA128 PORTB, PIN3 */
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//#define CSN 0 /*SPI - SS*/
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//#define FLASH_CS 6 /* PB.6 Output as CS*/
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//M644p/M1284p
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#define SCK 7 /* - Output: SPI Serial Clock (SCLK) - ATMEGA644/1284 PORTB, PIN7 */
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#define MOSI 5 /* - Output: SPI Master out - slave in (MOSI) - ATMEGA644/1284 PORTB, PIN5 */
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#define MISO 6 /* - Input: SPI Master in - slave out (MISO) - ATMEGA644/1284 PORTB, PIN6 */
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#define CSN 4 /*SPI - SS*/
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//#define FLASH_CS 3 /* PB.2 Output as CS*/
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//#define FLASH_CS 2 /* PB.2 Output as CS*/
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//#define CAN_CS 1 /* PB.1 Output as CS for CAN MCP2515*/
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//#define SPI_FLASH_ENABLE() ( PORTB &= ~BV(FLASH_CS) )
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//#define SPI_FLASH_DISABLE() ( PORTB |= BV(FLASH_CS) )
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#define WIZNET_CS 3 /* PB.3 Output as CS for Wiznet ETHERNET*/
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#define SPI_WIZNET_ENABLE() ( PORTB &= ~BV(WIZNET_CS) )
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#define SPI_WIZNET_DISABLE() ( PORTB |= BV(WIZNET_CS) )
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#define SD_CS 0 /* PB.0 Output as CS for SD-reader*/
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#define SPI_SD_ENABLE() ( PORTB &= ~BV(SD_CS) )
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#define SPI_SD_DISABLE() ( PORTB |= BV(SD_CS) )
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/* Define macros to use for checking SPI transmission status depending
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on if it is possible to wait for TX buffer ready. This is possible
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on for example MSP430 but not on AVR. */
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#ifdef SPI_WAITFORTxREADY
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#define SPI_WAITFORTx_BEFORE() SPI_WAITFORTxREADY()
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#define SPI_WAITFORTx_AFTER()
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#define SPI_WAITFORTx_ENDED() SPI_WAITFOREOTx()
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#else /* SPI_WAITFORTxREADY */
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#define SPI_WAITFORTx_BEFORE()
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#define SPI_WAITFORTx_AFTER() SPI_WAITFOREOTx()
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#define SPI_WAITFORTx_ENDED()
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#endif /* SPI_WAITFORTxREADY */
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extern unsigned char spi_busy;
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void spi_init(void);
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/* Write one character to SPI */
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#define SPI_WRITE(data) \
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do { \
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SPI_WAITFORTx_BEFORE(); \
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SPI_TXBUF = data; \
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SPI_WAITFOREOTx(); \
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} while(0)
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/* Write one character to SPI - will not wait for end
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useful for multiple writes with wait after final */
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#define SPI_WRITE_FAST(data) \
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do { \
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SPI_WAITFORTx_BEFORE(); \
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SPI_TXBUF = data; \
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SPI_WAITFORTx_AFTER(); \
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} while(0)
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/* Read one character from SPI */
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#define SPI_READ(data) \
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do { \
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SPI_TXBUF = 0; \
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SPI_WAITFOREORx(); \
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data = SPI_RXBUF; \
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} while(0)
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/* Flush the SPI read register */
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#ifndef SPI_FLUSH
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#define SPI_FLUSH() \
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do { \
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SPI_RXBUF; \
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} while(0);
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#endif
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#endif /* SPI_H_ */
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