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92 lines
3.1 KiB
C
92 lines
3.1 KiB
C
/*
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* Copyright (c) 2007, Swedish Institute of Computer Science
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <avr/io.h>
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#include "spi.h"
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#include "globals.h"
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//#include "contiki-conf.h"
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/*
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* On the Tmote sky access to I2C/SPI/UART0 must always be
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* exclusive. Set spi_busy so that interrupt handlers can check if
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* they are allowed to use the bus or not. Only the CC2420 radio needs
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* this in practice.
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*
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*/
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unsigned char spi_busy = 0;
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/*
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* Initialize SPI bus.
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*/
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//~ // From working SPI ENC28J60 driver
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//~ #define ENC28J60_CONTROL_PORT PORTB
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//~ #define ENC28J60_CONTROL_DDR DDRB
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//~
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//~ #define ENC28J60_CONTROL_CS PORTB6
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//~ #define ENC28J60_CONTROL_SO PORTB3
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//~ #define ENC28J60_CONTROL_SI PORTB2
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//~ #define ENC28J60_CONTROL_SCK PORTB1
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//~ #define ENC28J60_CONTROL_SS PORTB0
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//~
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//~ // set CS to 0 = active
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//~ #define CSACTIVE ENC28J60_CONTROL_PORT&=~(1<<ENC28J60_CONTROL_CS)
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//~ // set CS to 1 = passive
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//~ #define CSPASSIVE ENC28J60_CONTROL_PORT|=(1<<ENC28J60_CONTROL_CS)
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//
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//~ #define waitspi() while(!(SPSR&(1<<SPIF)))
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void
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spi_init(void)
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{
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// CS PIN for FLASH
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DDRB |= _BV(WIZNET_CS); // CS to OUT && Disable
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SPI_WIZNET_DISABLE();
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/* Initalize ports for communication with SPI units. */
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/* CSN=SS and must be output when master! */
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DDRB |= _BV(MOSI) | _BV(SCK) | _BV(CSN);
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PORTB |= _BV(MOSI) | _BV(SCK);
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/* Enables SPI, selects "master", clock rate FCK / 4 - 4Mhz, and SPI mode 0 */
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SPCR = _BV(SPE) | _BV(MSTR);
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#if defined(SPI_8_MHZ)
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SPSR = _BV(SPI2X); //FCK / 2 - 8Mhz
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#elif defined (SPI_4_MHZ)
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SPSR = 0x0; //FCK / 4 - 4Mhz
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#else
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SPSR = 0x0; //FCK / 4 - 4Mhz
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#endif
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}
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