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			93 lines
		
	
	
		
			3.2 KiB
		
	
	
	
		
			C
		
	
			
		
		
	
	
			93 lines
		
	
	
		
			3.2 KiB
		
	
	
	
		
			C
		
	
| #ifndef SPI_H_
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| #define SPI_H_
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| 
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| /* SPI input/output registers. */
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| #define SPI_TXBUF SPDR
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| #define SPI_RXBUF SPDR
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| 
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| #define BV(bitno) _BV(bitno)
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| 
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| #define SPI_WAITFOREOTx() do { while (!(SPSR & BV(SPIF))); } while (0)
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| #define SPI_WAITFOREORx() do { while (!(SPSR & BV(SPIF))); } while (0)
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| 
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| //M128
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| //#define SCK            1  /* - Output: SPI Serial Clock (SCLK) - ATMEGA128 PORTB, PIN1 */
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| //#define MOSI           2  /* - Output: SPI Master out - slave in (MOSI) - ATMEGA128 PORTB, PIN2 */
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| //#define MISO           3  /* - Input:  SPI Master in - slave out (MISO) - ATMEGA128 PORTB, PIN3 */
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| //#define CSN            0  /*SPI - SS*/
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| //#define FLASH_CS       6       /* PB.6 Output as CS*/
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| 
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| //M644p/M1284p
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| #define SCK            7  /* - Output: SPI Serial Clock (SCLK) - ATMEGA644/1284 PORTB, PIN7 */
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| #define MOSI           5  /* - Output: SPI Master out - slave in (MOSI) -  ATMEGA644/1284 PORTB, PIN5 */
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| #define MISO           6  /* - Input:  SPI Master in - slave out (MISO) -  ATMEGA644/1284 PORTB, PIN6 */
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| #define CSN            4  /*SPI - SS*/
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| 
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| //#define FLASH_CS       3       /* PB.2 Output as CS*/
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| //#define FLASH_CS       2       /* PB.2 Output as CS*/
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| //#define CAN_CS         1       /* PB.1 Output as CS for CAN MCP2515*/
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| 
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| //#define SPI_FLASH_ENABLE()  ( PORTB &= ~BV(FLASH_CS) )
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| //#define SPI_FLASH_DISABLE() ( PORTB |=  BV(FLASH_CS) )
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| 
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| #define WIZNET_CS       3       /* PB.3 Output as CS for Wiznet ETHERNET*/
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| #define SPI_WIZNET_ENABLE()  ( PORTB &= ~BV(WIZNET_CS) )
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| #define SPI_WIZNET_DISABLE() ( PORTB |=  BV(WIZNET_CS) )
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| 
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| #define SD_CS       0       /* PB.0 Output as CS for SD-reader*/
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| #define SPI_SD_ENABLE()  ( PORTB &= ~BV(SD_CS) )
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| #define SPI_SD_DISABLE() ( PORTB |=  BV(SD_CS) )
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| 
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| 
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| 
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| 
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| /* Define macros to use for checking SPI transmission status depending
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|    on if it is possible to wait for TX buffer ready. This is possible
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|    on for example MSP430 but not on AVR. */
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| #ifdef SPI_WAITFORTxREADY
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| #define SPI_WAITFORTx_BEFORE() SPI_WAITFORTxREADY()
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| #define SPI_WAITFORTx_AFTER()
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| #define SPI_WAITFORTx_ENDED() SPI_WAITFOREOTx()
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| #else /* SPI_WAITFORTxREADY */
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| #define SPI_WAITFORTx_BEFORE()
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| #define SPI_WAITFORTx_AFTER() SPI_WAITFOREOTx()
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| #define SPI_WAITFORTx_ENDED()
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| #endif /* SPI_WAITFORTxREADY */
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| 
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| void spi_init(void);
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| 
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| /* Write one character to SPI */
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| #define SPI_WRITE(data)                         \
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|   do {                                          \
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|     SPI_WAITFORTx_BEFORE();                     \
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|     SPI_TXBUF = data;                           \
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|     SPI_WAITFOREOTx();                          \
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|   } while(0)
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| 
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| /* Write one character to SPI - will not wait for end
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|    useful for multiple writes with wait after final */
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| #define SPI_WRITE_FAST(data)                    \
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|   do {                                          \
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|     SPI_WAITFORTx_BEFORE();                     \
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|     SPI_TXBUF = data;                           \
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|     SPI_WAITFORTx_AFTER();                      \
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|   } while(0)
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| 
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| /* Read one character from SPI */
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| #define SPI_READ(data)   \
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|   do {                   \
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|     SPI_TXBUF = 0;       \
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|     SPI_WAITFOREORx();   \
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|     data = SPI_RXBUF;    \
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|   } while(0)
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| 
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| /* Flush the SPI read register */
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| #ifndef SPI_FLUSH
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| #define SPI_FLUSH() \
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|   do {              \
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|     SPI_RXBUF;      \
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|   } while(0);
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| #endif
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| 
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| #endif /* SPI_H_ */
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