From f7a282051be06f9147883643e4e48ed7bccdbfa8 Mon Sep 17 00:00:00 2001
From: maxxir_w <maxx_ir@rambler.ru>
Date: Mon, 25 Mar 2019 08:36:17 +0400
Subject: [PATCH] Updated SPI code driver.

---
 12_m1284p_WIZNET_HTTPServer_SDCARD_pages/globals.h |  4 +++
 12_m1284p_WIZNET_HTTPServer_SDCARD_pages/mmc_avr.c | 19 ++++++++----
 12_m1284p_WIZNET_HTTPServer_SDCARD_pages/spi.c     | 35 +++++++++++++++++-----
 12_m644p_WIZNET_HTTPServer_SDCARD_pages/globals.h  |  4 +++
 12_m644p_WIZNET_HTTPServer_SDCARD_pages/mmc_avr.c  | 19 ++++++++----
 12_m644p_WIZNET_HTTPServer_SDCARD_pages/spi.c      | 35 +++++++++++++++++-----
 6 files changed, 88 insertions(+), 28 deletions(-)

diff --git a/12_m1284p_WIZNET_HTTPServer_SDCARD_pages/globals.h b/12_m1284p_WIZNET_HTTPServer_SDCARD_pages/globals.h
index bfb99a4..1806a53 100644
--- a/12_m1284p_WIZNET_HTTPServer_SDCARD_pages/globals.h
+++ b/12_m1284p_WIZNET_HTTPServer_SDCARD_pages/globals.h
@@ -34,6 +34,10 @@
 
 //#define IP_WORK
 
+//SPI CLOCK 4 or 8Mhz
+#define SPI_4_MHZ
+//#define SPI_8_MHZ
+
 extern unsigned long millis(void);
 extern int freeRam (void);
 
diff --git a/12_m1284p_WIZNET_HTTPServer_SDCARD_pages/mmc_avr.c b/12_m1284p_WIZNET_HTTPServer_SDCARD_pages/mmc_avr.c
index 0557785..2d59360 100644
--- a/12_m1284p_WIZNET_HTTPServer_SDCARD_pages/mmc_avr.c
+++ b/12_m1284p_WIZNET_HTTPServer_SDCARD_pages/mmc_avr.c
@@ -19,7 +19,7 @@
 
 #include <avr/io.h>
 #include "diskio.h"
-
+#include "globals.h"
 
 /* Port controls  (Platform dependent) */
 
@@ -113,17 +113,24 @@ void power_on (void)
 	DDRB  |= _BV(MOSI) | _BV(SCK) | _BV(CSN);
 	PORTB |= _BV(MOSI) | _BV(SCK);
 
+
+#if defined(SPI_8_MHZ)
 	/* Enables SPI, selects "master", clock rate FCK / 2, and SPI mode 0 */
 	// SPI 8Mhz
-	/*
 	SPCR = _BV(SPE) | _BV(MSTR);
-	SPSR = _BV(SPI2X);
-	*/
-
+	SPSR = _BV(SPI2X); //FCK / 2 - 8Mhz
+#elif defined (SPI_4_MHZ)
+	/* Enables SPI, selects "master", clock rate FCK / 4, and SPI mode 0 */
+	// SPI 4Mhz
+	SPCR = _BV(SPE) | _BV(MSTR);
+	SPSR = 0x0; //FCK / 4 - 4Mhz
+#else
 	/* Enables SPI, selects "master", clock rate FCK / 4, and SPI mode 0 */
 	// SPI 4Mhz
 	SPCR = _BV(SPE) | _BV(MSTR);
-	SPSR = 0x0;
+	SPSR = 0x0; //FCK / 4 - 4Mhz
+#endif
+
 }
 
 static
diff --git a/12_m1284p_WIZNET_HTTPServer_SDCARD_pages/spi.c b/12_m1284p_WIZNET_HTTPServer_SDCARD_pages/spi.c
index dfed60f..47d9c33 100644
--- a/12_m1284p_WIZNET_HTTPServer_SDCARD_pages/spi.c
+++ b/12_m1284p_WIZNET_HTTPServer_SDCARD_pages/spi.c
@@ -1,22 +1,36 @@
 #include <avr/io.h>
 #include "spi.h"
+#include "globals.h"
 
 /*
  * Initialize SPI bus.
  */
 
+//~ // From working SPI ENC28J60 driver
+//~ #define ENC28J60_CONTROL_PORT   PORTB
+//~ #define ENC28J60_CONTROL_DDR    DDRB
+//~ 
+//~ #define ENC28J60_CONTROL_CS PORTB6
+//~ #define ENC28J60_CONTROL_SO PORTB3
+//~ #define ENC28J60_CONTROL_SI PORTB2
+//~ #define ENC28J60_CONTROL_SCK PORTB1
+//~ #define ENC28J60_CONTROL_SS PORTB0
+//~ 
+//~ // set CS to 0 = active
+//~ #define CSACTIVE ENC28J60_CONTROL_PORT&=~(1<<ENC28J60_CONTROL_CS)
+//~ // set CS to 1 = passive
+//~ #define CSPASSIVE ENC28J60_CONTROL_PORT|=(1<<ENC28J60_CONTROL_CS)
+//
+//~ #define waitspi() while(!(SPSR&(1<<SPIF)))
+ 
+
 void
 spi_init(void)
 {
-  // CS PIN for WIZNET ETHERNET
+  // CS PIN for FLASH
   DDRB	|= _BV(WIZNET_CS); // CS to OUT && Disable
   SPI_WIZNET_DISABLE();
-
-  // CS PIN for SDCARD
-  DDRB	|= _BV(SD_CS); // CS to OUT && Disable
-  SPI_SD_DISABLE();
   
-
   /* Initalize ports for communication with SPI units. */
   /* CSN=SS and must be output when master! */
   DDRB  |= _BV(MOSI) | _BV(SCK) | _BV(CSN);
@@ -24,8 +38,13 @@ spi_init(void)
  
   /* Enables SPI, selects "master", clock rate FCK / 4 - 4Mhz, and SPI mode 0 */
   SPCR = _BV(SPE) | _BV(MSTR);
-  SPSR = 0x0;
-  //SPSR = _BV(SPI2X); //FCK / 2 - 8Mhz
+#if defined(SPI_8_MHZ)
+  SPSR = _BV(SPI2X); //FCK / 2 - 8Mhz
+#elif defined (SPI_4_MHZ)
+  SPSR = 0x0; //FCK / 4 - 4Mhz
+#else
+  SPSR = 0x0; //FCK / 4 - 4Mhz
+#endif
 
 
 }
diff --git a/12_m644p_WIZNET_HTTPServer_SDCARD_pages/globals.h b/12_m644p_WIZNET_HTTPServer_SDCARD_pages/globals.h
index 1dd978a..8bebfdf 100644
--- a/12_m644p_WIZNET_HTTPServer_SDCARD_pages/globals.h
+++ b/12_m644p_WIZNET_HTTPServer_SDCARD_pages/globals.h
@@ -34,6 +34,10 @@
 
 //#define IP_WORK
 
+//SPI CLOCK 4 or 8Mhz
+#define SPI_4_MHZ
+//#define SPI_8_MHZ
+
 extern unsigned long millis(void);
 extern int freeRam (void);
 
diff --git a/12_m644p_WIZNET_HTTPServer_SDCARD_pages/mmc_avr.c b/12_m644p_WIZNET_HTTPServer_SDCARD_pages/mmc_avr.c
index 0557785..2d59360 100644
--- a/12_m644p_WIZNET_HTTPServer_SDCARD_pages/mmc_avr.c
+++ b/12_m644p_WIZNET_HTTPServer_SDCARD_pages/mmc_avr.c
@@ -19,7 +19,7 @@
 
 #include <avr/io.h>
 #include "diskio.h"
-
+#include "globals.h"
 
 /* Port controls  (Platform dependent) */
 
@@ -113,17 +113,24 @@ void power_on (void)
 	DDRB  |= _BV(MOSI) | _BV(SCK) | _BV(CSN);
 	PORTB |= _BV(MOSI) | _BV(SCK);
 
+
+#if defined(SPI_8_MHZ)
 	/* Enables SPI, selects "master", clock rate FCK / 2, and SPI mode 0 */
 	// SPI 8Mhz
-	/*
 	SPCR = _BV(SPE) | _BV(MSTR);
-	SPSR = _BV(SPI2X);
-	*/
-
+	SPSR = _BV(SPI2X); //FCK / 2 - 8Mhz
+#elif defined (SPI_4_MHZ)
+	/* Enables SPI, selects "master", clock rate FCK / 4, and SPI mode 0 */
+	// SPI 4Mhz
+	SPCR = _BV(SPE) | _BV(MSTR);
+	SPSR = 0x0; //FCK / 4 - 4Mhz
+#else
 	/* Enables SPI, selects "master", clock rate FCK / 4, and SPI mode 0 */
 	// SPI 4Mhz
 	SPCR = _BV(SPE) | _BV(MSTR);
-	SPSR = 0x0;
+	SPSR = 0x0; //FCK / 4 - 4Mhz
+#endif
+
 }
 
 static
diff --git a/12_m644p_WIZNET_HTTPServer_SDCARD_pages/spi.c b/12_m644p_WIZNET_HTTPServer_SDCARD_pages/spi.c
index dfed60f..47d9c33 100644
--- a/12_m644p_WIZNET_HTTPServer_SDCARD_pages/spi.c
+++ b/12_m644p_WIZNET_HTTPServer_SDCARD_pages/spi.c
@@ -1,22 +1,36 @@
 #include <avr/io.h>
 #include "spi.h"
+#include "globals.h"
 
 /*
  * Initialize SPI bus.
  */
 
+//~ // From working SPI ENC28J60 driver
+//~ #define ENC28J60_CONTROL_PORT   PORTB
+//~ #define ENC28J60_CONTROL_DDR    DDRB
+//~ 
+//~ #define ENC28J60_CONTROL_CS PORTB6
+//~ #define ENC28J60_CONTROL_SO PORTB3
+//~ #define ENC28J60_CONTROL_SI PORTB2
+//~ #define ENC28J60_CONTROL_SCK PORTB1
+//~ #define ENC28J60_CONTROL_SS PORTB0
+//~ 
+//~ // set CS to 0 = active
+//~ #define CSACTIVE ENC28J60_CONTROL_PORT&=~(1<<ENC28J60_CONTROL_CS)
+//~ // set CS to 1 = passive
+//~ #define CSPASSIVE ENC28J60_CONTROL_PORT|=(1<<ENC28J60_CONTROL_CS)
+//
+//~ #define waitspi() while(!(SPSR&(1<<SPIF)))
+ 
+
 void
 spi_init(void)
 {
-  // CS PIN for WIZNET ETHERNET
+  // CS PIN for FLASH
   DDRB	|= _BV(WIZNET_CS); // CS to OUT && Disable
   SPI_WIZNET_DISABLE();
-
-  // CS PIN for SDCARD
-  DDRB	|= _BV(SD_CS); // CS to OUT && Disable
-  SPI_SD_DISABLE();
   
-
   /* Initalize ports for communication with SPI units. */
   /* CSN=SS and must be output when master! */
   DDRB  |= _BV(MOSI) | _BV(SCK) | _BV(CSN);
@@ -24,8 +38,13 @@ spi_init(void)
  
   /* Enables SPI, selects "master", clock rate FCK / 4 - 4Mhz, and SPI mode 0 */
   SPCR = _BV(SPE) | _BV(MSTR);
-  SPSR = 0x0;
-  //SPSR = _BV(SPI2X); //FCK / 2 - 8Mhz
+#if defined(SPI_8_MHZ)
+  SPSR = _BV(SPI2X); //FCK / 2 - 8Mhz
+#elif defined (SPI_4_MHZ)
+  SPSR = 0x0; //FCK / 4 - 4Mhz
+#else
+  SPSR = 0x0; //FCK / 4 - 4Mhz
+#endif
 
 
 }