Filamentstr/modbus_loadcell
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indentation

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This commit is contained in:
Eggert Jung
2022-05-24 20:07:55 +02:00
parent 0ba716fb3e
commit 029cb594cb
1 changed files with 6 additions and 6 deletions
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12
code/main.c
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@@ -40,7 +40,7 @@ uint32_t HX711_get_data(uint8_t clk_PIN, uint8_t data_PIN, uint8_t gain_for_next
extra_clk_pluses = 2; extra_clk_pluses = 2;
break; break;
default: default:
extra_clk_pluses = 1; extra_clk_pluses = 1;
} }
for(uint8_t i = 0; i < extra_clk_pluses; i++){ for(uint8_t i = 0; i < extra_clk_pluses; i++){
PORTB |= (1 << clk_PIN); //set clock-PIN high PORTB |= (1 << clk_PIN); //set clock-PIN high
@@ -52,7 +52,7 @@ uint32_t HX711_get_data(uint8_t clk_PIN, uint8_t data_PIN, uint8_t gain_for_next
/* Convert 24bit Two's complement to 32bit Two's complement /* Convert 24bit Two's complement to 32bit Two's complement
if MSB from 24Bit result is 1 aka negative*/ if MSB from 24Bit result is 1 aka negative*/
if(data & (1L<<23)){ if(data & (1L<<23)){
data |= 0xFFL << 24; data |= 0xFFL << 24;
} }
return data; return data;
} }
@@ -83,12 +83,12 @@ int main(void){
DDRB |= (1<<3); DDRB |= (1<<3);
modbusSetAddress(1); modbusSetAddress(1);
modbusInit(); modbusInit();
sei(); sei();
/* modbus tick timer */ /* modbus tick timer */
TCCR0B|=(1<<CS01); TCCR0B|=(1<<CS01);
TIMSK0|=(1<<TOIE0); TIMSK0|=(1<<TOIE0);
while(1){ while(1){
modbusGet(); modbusGet();
@@ -96,5 +96,5 @@ int main(void){
} }
ISR(TIMER0_OVF_vect) { //this ISR is called 9765.625 times per second ISR(TIMER0_OVF_vect) { //this ISR is called 9765.625 times per second
modbusTickTimer(); modbusTickTimer();
} }