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245 lines
8.3 KiB
C++
245 lines
8.3 KiB
C++
#include "lapic_registers.h"
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namespace LAPIC {
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namespace IPI {
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/*! \brief Delivery mode specifies the type of interrupt sent to the CPU. */
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enum DeliveryMode {
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FIXED = 0, ///< "ordinary" interrupt; send to ALL cores listed in the
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///< destination bit mask
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LOWEST_PRIORITY = 1, ///< "ordinary" interrupt; send to the lowest priority
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///< core from destination mask
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SMI = 2, ///< System Management Interrupt; vector number required to be 0
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// Reserved
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NMI = 4, ///< Non-Maskable Interrupt, vector number ignored, only edge
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///< triggered
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INIT = 5, ///< Initialization interrupt (always treated as edge triggered)
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INIT_LEVEL_DEASSERT = 5, ///< Synchronization interrupt
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STARTUP = 6, ///< Dedicated Startup-Interrupt (SIPI)
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// Reserved
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};
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/*! \brief Way of interpreting the value written to the destination field. */
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enum DestinationMode {
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PHYSICAL = 0, ///< Destination contains the physical destination APIC ID
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LOGICAL = 1 ///< Destination contains a mask of logical APIC IDs
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};
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/*! \brief Interrupt state */
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enum DeliveryStatus {
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IDLE = 0, ///< No activity for this interrupt
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SEND_PENDING =
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1 ///< Interrupt will be sent as soon as the bus / LAPIC is ready
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};
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/*! \brief Interrupt level */
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enum Level {
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DEASSERT = 0, ///< Must be zero when DeliveryMode::INIT_LEVEL_DEASSERT
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ASSERT = 1 ///< Must be one for all other delivery modes
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};
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/*! \brief Trigger mode for DeliveryMode::INIT_LEVEL_DEASSERT */
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enum TriggerMode {
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EDGE_TRIGGERED = 0, ///< edge triggered
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LEVEL_TRIGGERED = 1 ///< level triggered
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};
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/*! \brief Shorthand for commonly used destinations */
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enum DestinationShorthand {
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NO_SHORTHAND = 0, ///< Use destination field instead of shorthand
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SELF = 1, ///< Send IPI to self
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ALL_INCLUDING_SELF = 2, ///< Send IPI to all including self
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ALL_EXCLUDING_SELF = 3 ///< Send IPI to all except self
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};
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/*! \brief Interrupt mask */
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enum InterruptMask {
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UNMASKED = 0, ///< Interrupt entry is active (non-masked)
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MASKED = 1 ///< Interrupt entry is deactivated (masked)
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};
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/*! \brief Interrupt Command
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*
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* \see [ISDMv3 10.6.1 Interrupt Command Register
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* (ICR)](intel_manual_vol3.pdf#page=381)
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*/
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union InterruptCommand {
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struct {
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/*! \brief Interrupt vector in the \ref IDT "Interrupt Descriptor Table
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* (IDT)" will be activated when the corresponding external interrupt
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* triggers.
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*//*! \brief Interrupt vector in the \ref IDT "Interrupt Descriptor Table (IDT)" will be
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* activated when the corresponding external interrupt triggers.
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*/
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uint64_t vector : 8;
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/*! \brief The delivery mode denotes the way the interrupts will be
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* delivered to the local CPU cores, respectively to their local APICs.
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*
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* For StuBS, we use `DeliveryMode::LowestPriority`, as all CPU cores have
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* the same priority and we want to distribute interrupts evenly among them.
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* It, however, is not guaranteed that this method of load balancing will
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* work on every system.
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*/
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enum DeliveryMode delivery_mode : 3;
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/*! \brief The destination mode defines how the value stored in
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* `destination` will be interpreted.
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*
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* For StuBS, we use `DestinationMode::Logical`.
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*/
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enum DestinationMode destination_mode : 1;
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/*! \brief Delivery status holds the current status of interrupt delivery.
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*
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* \note This field is read only; write accesses to this field will be
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* ignored.
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*/
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enum DeliveryStatus delivery_status : 1;
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uint64_t : 1; ///< reserved
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/*! \brief The polarity denotes when an interrupt should be issued.
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*
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* For StuBS, we use `Polarity::High` (i.e., when the interrupt line is,
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* logically, 1).
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*/
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enum Level level : 1;
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/*! \brief The trigger mode states whether the interrupt signaling is level
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* or edge triggered.
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*
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* StuBS uses `TriggerMode::Edge` for Keyboard and Timer, the (optional)
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* serial interface, however, needs `TriggerMode::Level`.
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*/
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enum TriggerMode trigger_mode : 1;
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uint64_t : 2; ///< reserved
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enum DestinationShorthand destination_shorthand : 2;
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uint64_t : 36; ///< Reserved, do not modify
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/*! \brief Interrupt destination.
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*
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* The meaning of destination depends on the destination mode:
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* For the logical destination mode, destination holds a bit mask made up
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* of the cores that are candidates for receiving the interrupt. In the
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* single-core case, this value is `1`, in the multi-core case, the `n`
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* low-order bits needs to be set (with `n` being the number of CPU cores,
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* see \ref Core::count() ). Setting the `n` low-order bits marks all
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* available cores as candidates for receiving interrupts and thereby
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* balancing the number of interrupts between the cores.
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*
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* \note This form of load balancing depends on the hardware's behavior and
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* may not work on all systems in the same fashion. Most notably, in QEMU
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* all interrupts are sent to the BSP (core 0).
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*/
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uint64_t destination : 8;
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} __attribute__((packed));
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/*! \brief I/O redirection-table entry
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*
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* Every entry in the redirection table represents an external source of
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* interrupts and has a size of 64 bits. Due to the I/O APIC registers being
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* only 32 bits wide, the 64-bit value is split in two 32 bit values.
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*/
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struct {
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Register value_low; ///< First, low-order register
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Register value_high; ///< Second, high-order register
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} __attribute__((packed));
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/*! \brief Default constructor */
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InterruptCommand() = default;
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explicit InterruptCommand(
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uint8_t destination, uint8_t vector = 0,
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DestinationMode destination_mode = DestinationMode::PHYSICAL,
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DeliveryMode delivery_mode = DeliveryMode::FIXED,
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TriggerMode trigger_mode = TriggerMode::EDGE_TRIGGERED,
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Level level = Level::ASSERT) {
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readRegister();
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this->vector = vector;
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this->delivery_mode = delivery_mode;
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this->destination_mode = destination_mode;
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this->level = level;
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this->trigger_mode = trigger_mode;
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this->destination_shorthand = DestinationShorthand::NO_SHORTHAND;
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this->destination = destination;
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}
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InterruptCommand(DestinationShorthand destination_shorthand, uint8_t vector,
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DeliveryMode delivery_mode = DeliveryMode::FIXED,
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TriggerMode trigger_mode = TriggerMode::EDGE_TRIGGERED,
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Level level = Level::ASSERT) {
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readRegister();
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this->vector = vector;
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this->delivery_mode = delivery_mode;
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this->level = level;
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this->trigger_mode = trigger_mode;
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this->destination_shorthand = destination_shorthand;
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this->destination = destination;
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}
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void send() const {
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write(INTERRUPT_COMMAND_REGISTER_HIGH, value_high);
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write(INTERRUPT_COMMAND_REGISTER_LOW, value_low);
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}
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bool isSendPending() {
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value_low = read(INTERRUPT_COMMAND_REGISTER_LOW);
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return delivery_status == DeliveryStatus::SEND_PENDING;
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}
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private:
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void readRegister() {
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while (isSendPending()) {
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}
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value_high = read(INTERRUPT_COMMAND_REGISTER_HIGH);
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}
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};
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static_assert(sizeof(InterruptCommand) == 8,
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"LAPIC Interrupt Command has wrong size");
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bool isDelivered() {
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InterruptCommand ic;
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return !ic.isSendPending();
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}
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void send(uint8_t destination, uint8_t vector) {
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InterruptCommand ic(destination, vector);
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ic.send();
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}
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void sendGroup(uint8_t logical_destination, uint8_t vector) {
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InterruptCommand ic(logical_destination, vector, DestinationMode::LOGICAL);
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ic.send();
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}
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void sendAll(uint8_t vector) {
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InterruptCommand ic(DestinationShorthand::ALL_INCLUDING_SELF, vector);
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ic.send();
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}
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void sendOthers(uint8_t vector) {
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InterruptCommand ic(DestinationShorthand::ALL_EXCLUDING_SELF, vector);
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ic.send();
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}
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void sendInit(bool assert) {
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LAPIC::IPI::InterruptCommand ic(
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DestinationShorthand::ALL_EXCLUDING_SELF, 0, DeliveryMode::INIT,
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assert ? TriggerMode::EDGE_TRIGGERED : TriggerMode::LEVEL_TRIGGERED,
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assert ? Level::ASSERT : Level::DEASSERT);
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ic.send();
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}
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void sendStartup(uint8_t vector) {
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InterruptCommand ic(DestinationShorthand::ALL_EXCLUDING_SELF, vector,
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DeliveryMode::STARTUP);
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ic.send();
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}
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} // namespace IPI
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} // namespace LAPIC
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