Disabled uart.c ISRs if GDBSTUB (debug emulator) is set

tags/1.1.0^0 1.1.0
Ilya Elenskiy 5 years ago
parent d5c399120f
commit 5e33234261

@ -1,105 +1,109 @@
#include <avr/io.h> #include <avr/io.h>
#include <avr/interrupt.h> #include <avr/interrupt.h>
#include <stdint.h> #include <stdint.h>
#include <stdlib.h> #include <stdlib.h>
#include <util/delay.h> #include <util/delay.h>
#include "uart.h" #include "uart.h"
#include "fifo.h" #include "fifo.h"
#define UART_BUFSIZE_IN 16 #define UART_BUFSIZE_IN 16
#define UART_BUFSIZE_OUT 64 #define UART_BUFSIZE_OUT 64
uint8_t uart_inbuf[UART_BUFSIZE_IN]; uint8_t uart_inbuf[UART_BUFSIZE_IN];
uint8_t uart_outbuf[UART_BUFSIZE_OUT]; uint8_t uart_outbuf[UART_BUFSIZE_OUT];
fifo_t uart_infifo; fifo_t uart_infifo;
fifo_t uart_outfifo; fifo_t uart_outfifo;
void void
UART_Init (void) UART_Init (void)
{ {
// Save Status Register and disable Interrupts // Save Status Register and disable Interrupts
uint8_t sreg = SREG; uint8_t sreg = SREG;
cli(); cli();
// Set Baudrate according to datasheet (16MHz -> 9600 Baud -> 103) // Set Baudrate according to datasheet (16MHz -> 9600 Baud -> 103)
UBRR0 = 103; UBRR0 = 103;
// Enable RX, TX and RX Complete Interrupt // Enable RX, TX and RX Complete Interrupt
UCSR0B = (1 << RXEN0)|(1 << TXEN0)|(1 << RXCIE0); UCSR0B = (1 << RXEN0)|(1 << TXEN0)|(1 << RXCIE0);
// Reset Complete-Flags // Reset Complete-Flags
UCSR0A = (1 << RXC0)|(1 << TXC0); UCSR0A = (1 << RXC0)|(1 << TXC0);
// Reset Status Register // Reset Status Register
SREG = sreg; SREG = sreg;
// Initialize FIFO Buffers // Initialize FIFO Buffers
fifo_init(&uart_infifo, uart_inbuf, UART_BUFSIZE_IN); fifo_init(&uart_infifo, uart_inbuf, UART_BUFSIZE_IN);
fifo_init(&uart_outfifo, uart_outbuf, UART_BUFSIZE_OUT); fifo_init(&uart_outfifo, uart_outbuf, UART_BUFSIZE_OUT);
} }
int8_t int8_t
UART_PutChar (const uint8_t c) UART_PutChar (const uint8_t c)
{ {
// Put char into TX Buffer // Put char into TX Buffer
int8_t ret = fifo_put(&uart_outfifo, c); int8_t ret = fifo_put(&uart_outfifo, c);
// Enable DRE Interrupt // Enable DRE Interrupt
UCSR0B |= (1 << UDRIE0); UCSR0B |= (1 << UDRIE0);
return ret; return ret;
} }
// Receive Interrupt Routine #ifndef GDBSTUB
ISR(USART0_RX_vect)
{ // Receive Interrupt Routine
fifo_put(&uart_infifo, UDR0); ISR(USART0_RX_vect)
} {
fifo_put(&uart_infifo, UDR0);
// Data Register Empty Interrupt }
ISR(USART0_UDRE_vect)
{ // Data Register Empty Interrupt
if (uart_outfifo.count > 0) ISR(USART0_UDRE_vect)
UDR0 = fifo_get_nowait(&uart_outfifo); {
else if (uart_outfifo.count > 0)
UCSR0B &= ~(1 << UDRIE0); UDR0 = fifo_get_nowait(&uart_outfifo);
} else
UCSR0B &= ~(1 << UDRIE0);
int16_t }
UART_GetChar (void)
{ #endif
return fifo_get_nowait(&uart_infifo);
} int16_t
UART_GetChar (void)
uint8_t {
UART_GetChar_Wait (void) return fifo_get_nowait(&uart_infifo);
{ }
return fifo_get_wait(&uart_infifo);
} uint8_t
UART_GetChar_Wait (void)
void {
UART_PutString (const char *s) return fifo_get_wait(&uart_infifo);
{ }
do
{ void
UART_PutChar(*s); UART_PutString (const char *s)
} {
while (*(s++)); do
} {
UART_PutChar(*s);
void }
UART_PutInteger (const int i) while (*(s++));
{ }
// Buffer for Output
char buffer[10]; void
UART_PutInteger (const int i)
// Convert Integer to ASCII, Base 10 {
itoa(i, buffer, 10); // Buffer for Output
char buffer[10];
UART_PutString(buffer);
} // Convert Integer to ASCII, Base 10
itoa(i, buffer, 10);
UART_PutString(buffer);
}

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