1               		.file	"i2c.c"
   2               	__SP_H__ = 0x3e
   3               	__SP_L__ = 0x3d
   4               	__SREG__ = 0x3f
   5               	__RAMPZ__ = 0x3b
   6               	__tmp_reg__ = 0
   7               	__zero_reg__ = 1
   8               		.text
   9               	.Ltext0:
  10               		.cfi_sections	.debug_frame
  11               	.global	i2c_init
  13               	i2c_init:
  14               	.LFB0:
  15               		.file 1 "src/i2c.c"
   1:src/i2c.c     **** #include "i2c.h"
   2:src/i2c.c     **** #include "pinout.h"
   3:src/i2c.c     **** #include <util/twi.h> 			
   4:src/i2c.c     **** #include <avr/io.h>
   5:src/i2c.c     **** 
   6:src/i2c.c     **** 
   7:src/i2c.c     **** void i2c_init(void)
   8:src/i2c.c     **** {
  16               		.loc 1 8 0
  17               		.cfi_startproc
  18               	/* prologue: function */
  19               	/* frame size = 0 */
  20               	/* stack size = 0 */
  21               	.L__stack_usage = 0
   9:src/i2c.c     ****   /* initialize TWI clock: 100 kHz clock, TWPS = 0 => prescaler = 1 */
  10:src/i2c.c     ****   
  11:src/i2c.c     ****   TWSR = 1;                         /* no prescaler */
  22               		.loc 1 11 0
  23 0000 81E0      		ldi r24,lo8(1)
  24 0002 8093 B900 		sts 185,r24
  12:src/i2c.c     ****   TWBR = ((F_CPU/SCL_CLOCK)-16)/2;  /* must be > 10 for stable operation */
  25               		.loc 1 12 0
  26 0006 8BE4      		ldi r24,lo8(75)
  27 0008 8093 B800 		sts 184,r24
  28 000c 0895      		ret
  29               		.cfi_endproc
  30               	.LFE0:
  32               	.global	i2c_start
  34               	i2c_start:
  35               	.LFB1:
  13:src/i2c.c     **** 
  14:src/i2c.c     **** }
  15:src/i2c.c     **** 
  16:src/i2c.c     **** 
  17:src/i2c.c     **** unsigned char i2c_start(unsigned char address){
  36               		.loc 1 17 0
  37               		.cfi_startproc
  38               	.LVL0:
  39               	/* prologue: function */
  40               	/* frame size = 0 */
  41               	/* stack size = 0 */
  42               	.L__stack_usage = 0
  18:src/i2c.c     **** 	char DATA = 0b10011000;
  19:src/i2c.c     **** 	//Send START condition
  20:src/i2c.c     **** 	TWCR =  (1<<TWINT)| 
  43               		.loc 1 20 0
  44 000e 94EA      		ldi r25,lo8(-92)
  45 0010 9093 BC00 		sts 188,r25
  46               	.L4:
  21:src/i2c.c     **** 			(1<<TWSTA)|
  22:src/i2c.c     **** 			(1<<TWEN);
  23:src/i2c.c     **** 			
  24:src/i2c.c     **** 	//Wait for TWINT Flag set. This indicates that the START condition has been transmitted.
  25:src/i2c.c     **** 	while (!(TWCR &(1<<TWINT)));
  47               		.loc 1 25 0 discriminator 1
  48 0014 9091 BC00 		lds r25,188
  49 0018 97FF      		sbrs r25,7
  50 001a 00C0      		rjmp .L4
  26:src/i2c.c     **** 	
  27:src/i2c.c     **** 	//Check value of TWI Status Register. Mask prescaler bits. If status different from START go to ER
  28:src/i2c.c     **** 	if ((TWSR & 0xF8) != TW_START){
  51               		.loc 1 28 0
  52 001c 9091 B900 		lds r25,185
  29:src/i2c.c     **** 		//ERROR();
  30:src/i2c.c     **** 	}
  31:src/i2c.c     **** 	
  32:src/i2c.c     **** 	//Load SLA_W into TWDR Register. Clear TWINT bit in TWCR to start transmission of address.
  33:src/i2c.c     **** 	TWDR = address + I2C_WRITE;
  53               		.loc 1 33 0
  54 0020 8093 BB00 		sts 187,r24
  34:src/i2c.c     **** 	TWCR = (1<<TWINT) |
  55               		.loc 1 34 0
  56 0024 84E8      		ldi r24,lo8(-124)
  57               	.LVL1:
  58 0026 8093 BC00 		sts 188,r24
  59               	.LVL2:
  60               	.L6:
  35:src/i2c.c     **** 			(1<<TWEN);
  36:src/i2c.c     **** 		
  37:src/i2c.c     **** 	//Wait for TWINT Flag set. This indicates that the SLA+W has been transmitted, and ACK/NACK has be
  38:src/i2c.c     **** 	while (!(TWCR & (1<<TWINT)));
  61               		.loc 1 38 0 discriminator 1
  62 002a 8091 BC00 		lds r24,188
  63 002e 87FF      		sbrs r24,7
  64 0030 00C0      		rjmp .L6
  39:src/i2c.c     **** 	
  40:src/i2c.c     **** 	//Check value of TWI Status Register. Mask prescaler bits. If status different from MT_SLA_ACK go 
  41:src/i2c.c     **** 	if ((TWSR & 0xF8) != TW_MT_SLA_ACK){
  65               		.loc 1 41 0
  66 0032 8091 B900 		lds r24,185
  42:src/i2c.c     **** 	//	 ERROR();
  43:src/i2c.c     **** 	 }
  44:src/i2c.c     **** 	
  45:src/i2c.c     **** 	//Load DATA into TWDR Register. Clear TWINT bit in TWCR to start transmission of data.
  46:src/i2c.c     **** 	TWDR = DATA;
  67               		.loc 1 46 0
  68 0036 88E9      		ldi r24,lo8(-104)
  69 0038 8093 BB00 		sts 187,r24
  47:src/i2c.c     **** 	TWCR = (1<<TWINT) |
  70               		.loc 1 47 0
  71 003c 84E8      		ldi r24,lo8(-124)
  72 003e 8093 BC00 		sts 188,r24
  73               	.L8:
  48:src/i2c.c     **** 			(1<<TWEN);
  49:src/i2c.c     **** 			
  50:src/i2c.c     **** 	//Wait for TWINT Flag set. This indicates that the DATA has been transmitted, and ACK/NACK has bee
  51:src/i2c.c     **** 	while (!(TWCR &(1<<TWINT)));
  74               		.loc 1 51 0 discriminator 1
  75 0042 8091 BC00 		lds r24,188
  76 0046 87FF      		sbrs r24,7
  77 0048 00C0      		rjmp .L8
  52:src/i2c.c     **** 	
  53:src/i2c.c     **** 	//Check value of TWI Status Register. Mask prescaler bits. If status different from MT_DATA_ACK go
  54:src/i2c.c     **** 	if ((TWSR & 0xF8) != TW_MT_DATA_ACK){
  78               		.loc 1 54 0
  79 004a 8091 B900 		lds r24,185
  55:src/i2c.c     **** 	// ERROR();
  56:src/i2c.c     **** 	}
  57:src/i2c.c     **** 	
  58:src/i2c.c     **** 	//Transmit STOP condition
  59:src/i2c.c     **** 	TWCR = (1<<TWINT)|
  80               		.loc 1 59 0
  81 004e 84E9      		ldi r24,lo8(-108)
  82 0050 8093 BC00 		sts 188,r24
  60:src/i2c.c     **** 			(1<<TWEN) |
  61:src/i2c.c     **** 			(1<<TWSTO);
  62:src/i2c.c     **** 	
  63:src/i2c.c     **** 	
  64:src/i2c.c     **** 	/*
  65:src/i2c.c     **** 	TWCR = _BV(TWINT) | _BV(TWSTA) | _BV(TWEN);
  66:src/i2c.c     **** 	while  (!(TWCR & (1<<TWINT)));
  67:src/i2c.c     **** 	if ((TWSR & 0xF8) != TW_START)
  68:src/i2c.c     **** 	return 1;
  69:src/i2c.c     **** 	//ERROR();                                                                //Fehlerbehandlung
  70:src/i2c.c     **** 	TWDR = address + I2C_WRITE;
  71:src/i2c.c     **** 	TWCR = (1<<TWINT) | (1<<TWEN);
  72:src/i2c.c     **** 	while (!(TWCR & (1<<TWINT)));
  73:src/i2c.c     **** 	if ((TWSR & 0xF8) != TW_MT_SLA_ACK)
  74:src/i2c.c     ****   //ERROR();
  75:src/i2c.c     ****   return 2;
  76:src/i2c.c     ****  
  77:src/i2c.c     **** TWDR = address;
  78:src/i2c.c     **** TWCR = (1<<TWINT) | (1<<TWEN);
  79:src/i2c.c     **** while (!(TWCR & (1<<TWINT)));
  80:src/i2c.c     **** if ((TWSR & 0xF8) != TW_MT_DATA_ACK)
  81:src/i2c.c     **** return 3;
  82:src/i2c.c     ****   //ERROR();
  83:src/i2c.c     **** TWCR = (1<<TWINT)|(1<<TWEN)|
  84:src/i2c.c     **** (1<<TWSTO);
  85:src/i2c.c     **** */
  86:src/i2c.c     **** return 0;
  87:src/i2c.c     **** }
  83               		.loc 1 87 0
  84 0054 80E0      		ldi r24,0
  85 0056 0895      		ret
  86               		.cfi_endproc
  87               	.LFE1:
  89               	.Letext0:
  90               		.file 2 "/usr/local/CrossPack-AVR-20131216/avr/include/stdint.h"
DEFINED SYMBOLS
                            *ABS*:00000000 i2c.c
/var/folders/vp/mj8sv_kj3c1gtbdcbb9v8gb80000gn/T//ccKg5qqS.s:2      *ABS*:0000003e __SP_H__
/var/folders/vp/mj8sv_kj3c1gtbdcbb9v8gb80000gn/T//ccKg5qqS.s:3      *ABS*:0000003d __SP_L__
/var/folders/vp/mj8sv_kj3c1gtbdcbb9v8gb80000gn/T//ccKg5qqS.s:4      *ABS*:0000003f __SREG__
/var/folders/vp/mj8sv_kj3c1gtbdcbb9v8gb80000gn/T//ccKg5qqS.s:5      *ABS*:0000003b __RAMPZ__
/var/folders/vp/mj8sv_kj3c1gtbdcbb9v8gb80000gn/T//ccKg5qqS.s:6      *ABS*:00000000 __tmp_reg__
/var/folders/vp/mj8sv_kj3c1gtbdcbb9v8gb80000gn/T//ccKg5qqS.s:7      *ABS*:00000001 __zero_reg__
/var/folders/vp/mj8sv_kj3c1gtbdcbb9v8gb80000gn/T//ccKg5qqS.s:13     .text:00000000 i2c_init
/var/folders/vp/mj8sv_kj3c1gtbdcbb9v8gb80000gn/T//ccKg5qqS.s:34     .text:0000000e i2c_start

NO UNDEFINED SYMBOLS