From e7c793c88ede22acb7a8f09289bb90c300d06d69 Mon Sep 17 00:00:00 2001 From: Eggert Jung Date: Sat, 26 Apr 2025 16:39:50 +0200 Subject: [PATCH 1/6] wip on dma config --- Src/main.c | 76 +++++++++++++++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 63 insertions(+), 13 deletions(-) diff --git a/Src/main.c b/Src/main.c index 4100cb1..2bb25b7 100644 --- a/Src/main.c +++ b/Src/main.c @@ -62,27 +62,61 @@ static void MX_GPIO_Init(void); uint8_t rxBuffer[BUFFER_SIZE]; uint16_t rxBufferPos = 0; -void init_UART1(){ +void init_UART1_it(){ RCC->APBENR2 |= RCC_APBENR2_USART1EN; RCC->IOPENR |= RCC_IOPENR_GPIOCEN; GPIOC->MODER &= ~GPIO_MODER_MODE5; // Alternate function mode on RX pin GPIOC->MODER |= GPIO_MODER_MODE5_1; GPIOC->AFR[0] &= GPIO_AFRL_AFSEL5; - GPIOC->AFR[0] |= 1 << GPIO_AFRL_AFSEL5_Pos; + GPIOC->AFR[0] |= 1 << GPIO_AFRL_AFSEL5_Pos; // AF1 -> USART1 RX USART1->BRR = 128; // 32000000÷250000 USART1->CR1 = USART_CR1_RE; - USART1->CR3 |= USART_CR3_EIE; - USART1->CR1 |= USART_CR1_RXNEIE_RXFNEIE; + USART1->CR3 |= USART_CR3_EIE; // Interrupt on BREAK (and other errors) + USART1->CR1 |= USART_CR1_RXNEIE_RXFNEIE; // RX Interrupt USART1->CR1 |= USART_CR1_UE; HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); HAL_NVIC_EnableIRQ(USART1_IRQn); } -/* USER CODE END 0 */ + +void init_UART1_dma(){ + RCC->IOPENR |= RCC_IOPENR_GPIOCEN; + RCC->APBENR2 |= RCC_APBENR2_USART1EN; + RCC->AHBENR |= RCC_AHBENR_DMA1EN; + + GPIOC->MODER &= ~GPIO_MODER_MODE5; // Alternate function mode on RX pin + GPIOC->MODER |= GPIO_MODER_MODE5_1; + GPIOC->AFR[0] &= GPIO_AFRL_AFSEL5; + GPIOC->AFR[0] |= 1 << GPIO_AFRL_AFSEL5_Pos; // AF1 -> USART1 RX + + USART1->BRR = 128; // 32000000÷250000 + USART1->CR1 = USART_CR1_RE; + + USART1->CR3 |= USART_CR3_EIE; // Interrupt on BREAK (and other errors) + USART1->CR3 |= USART_CR3_DMAR; // DMA Receiver mode + + DMA1_Channel1->CCR = (0x02 << DMA_CCR_PL_Pos) | DMA_CCR_MINC | DMA_CCR_TCIE; + + DMA1_Channel1->CMAR = ( uint32_t )&rxBuffer[0]; + DMA1_Channel1->CPAR = ( uint32_t )&(USART1->RDR); + DMA1_Channel1->CNDTR = 5; + + DMAMUX1_Channel0->CCR &= ~( DMAMUX_CxCR_DMAREQ_ID ); + DMAMUX1_Channel0->CCR |= ( 50 << DMAMUX_CxCR_DMAREQ_ID_Pos ); // 50 -> USART1 RX + + + USART1->CR1 |= USART_CR1_UE; + + HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(USART1_IRQn); + + HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); +} void USART1_IRQHandler(){ if(USART1->ISR & USART_ISR_RXNE_RXFNE){ @@ -95,16 +129,18 @@ void USART1_IRQHandler(){ if(USART1->ISR & USART_ISR_FE){ USART1->ICR = USART_ICR_FECF; - printf("FE after %d\n",rxBufferPos); - rxBufferPos = 0; - printf("buf: "); - for(uint16_t i=0; i<10; i++) - printf("0x%02X ", rxBuffer[i]); - printf("\n"); + //if(rxBufferPos != 514) + // printf("FE after %d\n",rxBufferPos); + //rxBufferPos = 0; + printf("FE\n"); + //DMA1_Channel1->CNDTR = 1; + DMA1_Channel1->CNDTR = 5; + DMA1_Channel1->CCR |= ( DMA_CCR_EN ); + //DMA1_Channel1->CCR |= ( DMA_CCR_EN ); } if(USART1->ISR & USART_ISR_ORE){ USART1->ICR = USART_ICR_ORECF; - printf("ORE\n"); + //printf("ORE\n"); } if(USART1->ISR & USART_ISR_NE){ USART1->ICR = USART_ICR_NECF; @@ -116,6 +152,15 @@ void USART1_IRQHandler(){ } } +void DMA1_Channel1_IRQHandler(){ + if(DMA1->ISR & DMA_ISR_TCIF1){ + DMA1->IFCR = DMA_IFCR_CTCIF1; + DMA1_Channel1->CCR &= ~( DMA_CCR_EN ); + DMA1_Channel1->CMAR = ( uint32_t )&rxBuffer[0]; + } +} +/* USER CODE END 0 */ + /** * @brief The application entry point. * @retval int @@ -146,7 +191,7 @@ int main(void) /* Initialize all configured peripherals */ MX_GPIO_Init(); /* USER CODE BEGIN 2 */ - init_UART1(); + init_UART1_dma(); /* USER CODE END 2 */ /* Infinite loop */ @@ -154,6 +199,11 @@ int main(void) //HAL_UART_Receive_DMA(&huart1, rxBuffer, BUFFER_SIZE); while (1) { + printf("buf: "); + for(uint16_t i=0; i<10; i++) + printf("0x%02X ", rxBuffer[i]); + printf("\n"); + /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ From 8f576045ed7a30f99e93bc0b0855747e307ff28d Mon Sep 17 00:00:00 2001 From: Eggert Jung Date: Mon, 28 Apr 2025 20:40:04 +0200 Subject: [PATCH 2/6] add systemview for debugging purposes --- .gitmodules | 3 +++ Drivers/SystemView | 1 + Makefile | 7 ++++++- Src/main.c | 8 ++++++++ Src/stm32g0xx_it.c | 5 +++-- compile_flags.txt | 3 +++ 6 files changed, 24 insertions(+), 3 deletions(-) create mode 160000 Drivers/SystemView diff --git a/.gitmodules b/.gitmodules index c7477c3..bfbbd8f 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,6 @@ [submodule "Drivers/RTT"] path = Drivers/RTT url = https://github.com/SEGGERMicro/RTT.git +[submodule "Drivers/SystemView"] + path = Drivers/SystemView + url = https://github.com/SEGGERMicro/SystemView.git diff --git a/Drivers/SystemView b/Drivers/SystemView new file mode 160000 index 0000000..d8bbf3f --- /dev/null +++ b/Drivers/SystemView @@ -0,0 +1 @@ +Subproject commit d8bbf3f6e779af76a09cf7000c2003ab17ca11c6 diff --git a/Makefile b/Makefile index a9afc44..64ff4cf 100644 --- a/Makefile +++ b/Makefile @@ -58,6 +58,8 @@ Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c \ Drivers/RTT/RTT/SEGGER_RTT.c \ Drivers/RTT/RTT/SEGGER_RTT_printf.c \ Drivers/RTT/Syscalls/SEGGER_RTT_Syscalls_GCC.c \ +Drivers/SystemView/SYSVIEW/SEGGER_SYSVIEW.c \ +Drivers/SystemView/Sample/NoOS/Config/Cortex-M0/SEGGER_SYSVIEW_Config_NoOS_CM0.c\ Src/system_stm32g0xx.c # ASM sources @@ -124,7 +126,10 @@ C_INCLUDES = \ -IDrivers/CMSIS/Device/ST/STM32G0xx/Include \ -IDrivers/CMSIS/Include \ -IDrivers/RTT/Config \ --IDrivers/RTT/RTT +-IDrivers/RTT/RTT \ +-IDrivers/SystemView/Config \ +-IDrivers/SystemView/SEGGER \ +-IDrivers/SystemView/SYSVIEW # compile gcc flags diff --git a/Src/main.c b/Src/main.c index 2bb25b7..20fa865 100644 --- a/Src/main.c +++ b/Src/main.c @@ -21,6 +21,7 @@ /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ +#include "SEGGER_SYSVIEW.h" #include "SEGGER_RTT.h" #include "stm32g0b1xx.h" #include "stm32g0xx_hal_cortex.h" @@ -119,6 +120,7 @@ void init_UART1_dma(){ } void USART1_IRQHandler(){ + SEGGER_SYSVIEW_RecordEnterISR(); if(USART1->ISR & USART_ISR_RXNE_RXFNE){ //printf("%x ", USART1->RDR); rxBuffer[rxBufferPos++] = USART1->RDR; @@ -150,14 +152,17 @@ void USART1_IRQHandler(){ USART1->ICR = USART_ICR_UDRCF; printf("UDR\n"); } + SEGGER_SYSVIEW_RecordExitISR(); } void DMA1_Channel1_IRQHandler(){ + SEGGER_SYSVIEW_RecordEnterISR(); if(DMA1->ISR & DMA_ISR_TCIF1){ DMA1->IFCR = DMA_IFCR_CTCIF1; DMA1_Channel1->CCR &= ~( DMA_CCR_EN ); DMA1_Channel1->CMAR = ( uint32_t )&rxBuffer[0]; } + SEGGER_SYSVIEW_RecordExitISR(); } /* USER CODE END 0 */ @@ -167,9 +172,12 @@ void DMA1_Channel1_IRQHandler(){ */ int main(void) { + /* USER CODE BEGIN 1 */ SEGGER_RTT_ConfigUpBuffer(0, NULL, NULL, 0, SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL); printf("Moin!\n"); + + SEGGER_SYSVIEW_Conf(); /* Configure and initialize SystemView */ /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ diff --git a/Src/stm32g0xx_it.c b/Src/stm32g0xx_it.c index eee2e64..a519df9 100644 --- a/Src/stm32g0xx_it.c +++ b/Src/stm32g0xx_it.c @@ -23,6 +23,7 @@ /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ #include "stdio.h" +#include "SEGGER_SYSVIEW.h" /* USER CODE END Includes */ /* Private typedef -----------------------------------------------------------*/ @@ -126,11 +127,11 @@ void PendSV_Handler(void) void SysTick_Handler(void) { /* USER CODE BEGIN SysTick_IRQn 0 */ - + SEGGER_SYSVIEW_RecordEnterISR(); /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); /* USER CODE BEGIN SysTick_IRQn 1 */ - + SEGGER_SYSVIEW_RecordExitISR(); /* USER CODE END SysTick_IRQn 1 */ } diff --git a/compile_flags.txt b/compile_flags.txt index 5efdd1b..92d6f97 100644 --- a/compile_flags.txt +++ b/compile_flags.txt @@ -9,6 +9,9 @@ -IDrivers/CMSIS/Include -IDrivers/RTT/Config -IDrivers/RTT/RTT +-IDrivers/SystemView/Config +-IDrivers/SystemView/SEGGER +-IDrivers/SystemView/SYSVIEW -Og -Wall -fdata-sections From 19a85baf333415390850386d6380b13250056a3d Mon Sep 17 00:00:00 2001 From: Eggert Jung Date: Mon, 28 Apr 2025 21:45:42 +0200 Subject: [PATCH 3/6] fix timestamps --- Src/main.c | 12 ++++++------ Src/stm32g0xx_it.c | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/Src/main.c b/Src/main.c index 20fa865..9b70f83 100644 --- a/Src/main.c +++ b/Src/main.c @@ -174,11 +174,7 @@ int main(void) { /* USER CODE BEGIN 1 */ - SEGGER_RTT_ConfigUpBuffer(0, NULL, NULL, 0, SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL); - printf("Moin!\n"); - - SEGGER_SYSVIEW_Conf(); /* Configure and initialize SystemView */ - /* USER CODE END 1 */ + /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ @@ -193,6 +189,10 @@ int main(void) SystemClock_Config(); /* USER CODE BEGIN SysInit */ + SEGGER_RTT_ConfigUpBuffer(0, NULL, NULL, 0, SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL); + printf("Moin!\n"); + + SEGGER_SYSVIEW_Conf(); /* Configure and initialize SystemView */ /* USER CODE END SysInit */ @@ -211,7 +211,7 @@ int main(void) for(uint16_t i=0; i<10; i++) printf("0x%02X ", rxBuffer[i]); printf("\n"); - + SEGGER_SYSVIEW_OnIdle(); /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ diff --git a/Src/stm32g0xx_it.c b/Src/stm32g0xx_it.c index a519df9..93b02bf 100644 --- a/Src/stm32g0xx_it.c +++ b/Src/stm32g0xx_it.c @@ -43,7 +43,6 @@ /* Private variables ---------------------------------------------------------*/ /* USER CODE BEGIN PV */ - /* USER CODE END PV */ /* Private function prototypes -----------------------------------------------*/ @@ -127,6 +126,7 @@ void PendSV_Handler(void) void SysTick_Handler(void) { /* USER CODE BEGIN SysTick_IRQn 0 */ + SEGGER_SYSVIEW_TickCnt++; SEGGER_SYSVIEW_RecordEnterISR(); /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); From b85c8fc5f06d7cd45aacda17a4bb776bae3b8075 Mon Sep 17 00:00:00 2001 From: Eggert Jung Date: Mon, 28 Apr 2025 23:42:51 +0200 Subject: [PATCH 4/6] dma works --- Src/main.c | 32 +++++++++++++++++++++++++------- 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/Src/main.c b/Src/main.c index 9b70f83..7e1a71c 100644 --- a/Src/main.c +++ b/Src/main.c @@ -100,7 +100,7 @@ void init_UART1_dma(){ USART1->CR3 |= USART_CR3_EIE; // Interrupt on BREAK (and other errors) USART1->CR3 |= USART_CR3_DMAR; // DMA Receiver mode - DMA1_Channel1->CCR = (0x02 << DMA_CCR_PL_Pos) | DMA_CCR_MINC | DMA_CCR_TCIE; + DMA1_Channel1->CCR = (0x02 << DMA_CCR_PL_Pos) | DMA_CCR_MINC | DMA_CCR_TCIE; DMA1_Channel1->CMAR = ( uint32_t )&rxBuffer[0]; DMA1_Channel1->CPAR = ( uint32_t )&(USART1->RDR); @@ -109,7 +109,6 @@ void init_UART1_dma(){ DMAMUX1_Channel0->CCR &= ~( DMAMUX_CxCR_DMAREQ_ID ); DMAMUX1_Channel0->CCR |= ( 50 << DMAMUX_CxCR_DMAREQ_ID_Pos ); // 50 -> USART1 RX - USART1->CR1 |= USART_CR1_UE; HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); @@ -119,9 +118,25 @@ void init_UART1_dma(){ HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); } +void Reset_DMA(void) { + // Disable the DMA channel + DMA1_Channel1->CCR &= ~DMA_CCR_EN; // Disable DMA Channel 1 + + // Clear the transfer complete flag + DMA1->IFCR |= DMA_IFCR_CTCIF1; // Clear transfer complete flag for Channel 1 + + // Reconfigure the DMA + DMA1_Channel1->CMAR = (uint32_t)rxBuffer; // Set memory address to the start of the buffer + DMA1_Channel1->CNDTR = BUFFER_SIZE; // Set number of data items to transfer + + // Enable the DMA channel again + DMA1_Channel1->CCR |= DMA_CCR_EN; // Enable DMA Channel 1 +} + void USART1_IRQHandler(){ SEGGER_SYSVIEW_RecordEnterISR(); if(USART1->ISR & USART_ISR_RXNE_RXFNE){ + //SEGGER_SYSVIEW_PrintfHost("RXNE"); //printf("%x ", USART1->RDR); rxBuffer[rxBufferPos++] = USART1->RDR; if(rxBufferPos >= BUFFER_SIZE){ @@ -134,15 +149,19 @@ void USART1_IRQHandler(){ //if(rxBufferPos != 514) // printf("FE after %d\n",rxBufferPos); //rxBufferPos = 0; - printf("FE\n"); //DMA1_Channel1->CNDTR = 1; - DMA1_Channel1->CNDTR = 5; - DMA1_Channel1->CCR |= ( DMA_CCR_EN ); + SEGGER_SYSVIEW_PrintfHost("FE"); + Reset_DMA(); + //DMA1_Channel1->CCR &= ~( DMA_CCR_EN ); + //DMA1_Channel1->CNDTR = 512; + //DMA1_Channel1->CMAR = ( uint32_t )&rxBuffer[0]; //DMA1_Channel1->CCR |= ( DMA_CCR_EN ); + ////DMA1_Channel1->CCR |= ( DMA_CCR_EN ); } if(USART1->ISR & USART_ISR_ORE){ USART1->ICR = USART_ICR_ORECF; //printf("ORE\n"); + //SEGGER_SYSVIEW_PrintfHost("ORE"); } if(USART1->ISR & USART_ISR_NE){ USART1->ICR = USART_ICR_NECF; @@ -159,9 +178,8 @@ void DMA1_Channel1_IRQHandler(){ SEGGER_SYSVIEW_RecordEnterISR(); if(DMA1->ISR & DMA_ISR_TCIF1){ DMA1->IFCR = DMA_IFCR_CTCIF1; - DMA1_Channel1->CCR &= ~( DMA_CCR_EN ); - DMA1_Channel1->CMAR = ( uint32_t )&rxBuffer[0]; } + SEGGER_SYSVIEW_PrintfHost("DMA"); SEGGER_SYSVIEW_RecordExitISR(); } /* USER CODE END 0 */ From 096c40d216c208a86c5f0457efa5b15493ae5e31 Mon Sep 17 00:00:00 2001 From: Eggert Jung Date: Fri, 2 May 2025 01:56:18 +0200 Subject: [PATCH 5/6] bump freqency to 64MHz (max) had problems in cubeMX with that, but now it seems to work --- Makefile | 2 +- Parafraktor.ioc | 61 +++++++++++++++++++++++++++++---------------------------- Src/main.c | 6 +++--- 3 files changed, 35 insertions(+), 34 deletions(-) diff --git a/Makefile b/Makefile index 64ff4cf..a2f03af 100644 --- a/Makefile +++ b/Makefile @@ -1,5 +1,5 @@ ########################################################################################################################## -# File automatically-generated by tool: [projectgenerator] version: [4.2.0-B44] date: [Fri Apr 25 22:56:53 CEST 2025] +# File automatically-generated by tool: [projectgenerator] version: [4.2.0-B44] date: [Thu May 01 21:37:30 CEST 2025] ########################################################################################################################## # ------------------------------------------------ diff --git a/Parafraktor.ioc b/Parafraktor.ioc index 2a9cfea..a424b6f 100644 --- a/Parafraktor.ioc +++ b/Parafraktor.ioc @@ -65,49 +65,50 @@ ProjectManager.UAScriptAfterPath= ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=false ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_USART1_UART_Init-USART1-false-HAL-true -RCC.ADCFreq_Value=32000000 -RCC.AHBFreq_Value=32000000 -RCC.APBFreq_Value=32000000 -RCC.APBTimFreq_Value=32000000 +RCC.ADCFreq_Value=64000000 +RCC.AHBFreq_Value=64000000 +RCC.APBFreq_Value=64000000 +RCC.APBTimFreq_Value=64000000 RCC.CECFreq_Value=32786.88524590164 -RCC.CortexFreq_Value=32000000 +RCC.CortexFreq_Value=64000000 RCC.EXTERNAL_CLOCK_VALUE=48000 -RCC.FCLKCortexFreq_Value=32000000 -RCC.FDCANFreq_Value=32000000 +RCC.FCLKCortexFreq_Value=64000000 +RCC.FDCANFreq_Value=64000000 RCC.FamilyName=M -RCC.HCLKFreq_Value=32000000 +RCC.HCLKFreq_Value=64000000 RCC.HSE_VALUE=8000000 RCC.HSI48_VALUE=48000000 RCC.HSI_VALUE=16000000 -RCC.I2C1Freq_Value=32000000 -RCC.I2C2Freq_Value=32000000 -RCC.I2S1Freq_Value=32000000 -RCC.I2S2Freq_Value=32000000 -RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APBFreq_Value,APBTimFreq_Value,CECFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2S1Freq_Value,I2S2Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LPUART2Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,MCO2PinFreq_Value,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSourceVirtual,PWRFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TIM15Freq_Value,TIM1Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value -RCC.LPTIM1Freq_Value=32000000 -RCC.LPTIM2Freq_Value=32000000 -RCC.LPUART1Freq_Value=32000000 -RCC.LPUART2Freq_Value=32000000 +RCC.I2C1Freq_Value=64000000 +RCC.I2C2Freq_Value=64000000 +RCC.I2S1Freq_Value=64000000 +RCC.I2S2Freq_Value=64000000 +RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APBFreq_Value,APBTimFreq_Value,CECFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2S1Freq_Value,I2S2Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LPUART2Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,MCO2PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSourceVirtual,PWRFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TIM15Freq_Value,TIM1Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value +RCC.LPTIM1Freq_Value=64000000 +RCC.LPTIM2Freq_Value=64000000 +RCC.LPUART1Freq_Value=64000000 +RCC.LPUART2Freq_Value=64000000 RCC.LSCOPinFreq_Value=32000 RCC.LSE_VALUE=32768 RCC.LSI_VALUE=32000 -RCC.MCO1PinFreq_Value=32000000 -RCC.MCO2PinFreq_Value=32000000 -RCC.PLLPoutputFreq_Value=32000000 -RCC.PLLQoutputFreq_Value=32000000 -RCC.PLLRCLKFreq_Value=32000000 +RCC.MCO1PinFreq_Value=64000000 +RCC.MCO2PinFreq_Value=64000000 +RCC.PLLN=16 +RCC.PLLPoutputFreq_Value=64000000 +RCC.PLLQoutputFreq_Value=64000000 +RCC.PLLRCLKFreq_Value=64000000 RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE -RCC.PWRFreq_Value=32000000 -RCC.SYSCLKFreq_VALUE=32000000 +RCC.PWRFreq_Value=64000000 +RCC.SYSCLKFreq_VALUE=64000000 RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK -RCC.TIM15Freq_Value=32000000 -RCC.TIM1Freq_Value=32000000 -RCC.USART1Freq_Value=32000000 -RCC.USART2Freq_Value=32000000 -RCC.USART3Freq_Value=32000000 +RCC.TIM15Freq_Value=64000000 +RCC.TIM1Freq_Value=64000000 +RCC.USART1Freq_Value=64000000 +RCC.USART2Freq_Value=64000000 +RCC.USART3Freq_Value=64000000 RCC.USBFreq_Value=48000000 RCC.VCOInputFreq_Value=8000000 -RCC.VCOOutputFreq_Value=64000000 +RCC.VCOOutputFreq_Value=128000000 VP_SYS_VS_DBSignals.Mode=DisableDeadBatterySignals VP_SYS_VS_DBSignals.Signal=SYS_VS_DBSignals VP_SYS_VS_Systick.Mode=SysTick diff --git a/Src/main.c b/Src/main.c index 7e1a71c..05407ca 100644 --- a/Src/main.c +++ b/Src/main.c @@ -94,7 +94,7 @@ void init_UART1_dma(){ GPIOC->AFR[0] &= GPIO_AFRL_AFSEL5; GPIOC->AFR[0] |= 1 << GPIO_AFRL_AFSEL5_Pos; // AF1 -> USART1 RX - USART1->BRR = 128; // 32000000÷250000 + USART1->BRR = 256; // 64000000÷250000 USART1->CR1 = USART_CR1_RE; USART1->CR3 |= USART_CR3_EIE; // Interrupt on BREAK (and other errors) @@ -258,7 +258,7 @@ void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; - RCC_OscInitStruct.PLL.PLLN = 8; + RCC_OscInitStruct.PLL.PLLN = 16; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; @@ -275,7 +275,7 @@ void SystemClock_Config(void) RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { Error_Handler(); } From 97c86af4b71a6b912fcb9b66d45e5a203fc61161 Mon Sep 17 00:00:00 2001 From: Eggert Jung Date: Fri, 2 May 2025 02:00:51 +0200 Subject: [PATCH 6/6] step motor turns, minimal example --- Src/main.c | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/Src/main.c b/Src/main.c index 05407ca..7ab808f 100644 --- a/Src/main.c +++ b/Src/main.c @@ -145,6 +145,7 @@ void USART1_IRQHandler(){ } if(USART1->ISR & USART_ISR_FE){ + //TODO read rx==0 USART1->ICR = USART_ICR_FECF; //if(rxBufferPos != 514) // printf("FE after %d\n",rxBufferPos); @@ -182,6 +183,27 @@ void DMA1_Channel1_IRQHandler(){ SEGGER_SYSVIEW_PrintfHost("DMA"); SEGGER_SYSVIEW_RecordExitISR(); } + +void init_stepper(){ + RCC->IOPENR |= RCC_IOPENR_GPIOBEN; + RCC->IOPENR |= RCC_IOPENR_GPIOCEN; + RCC->IOPENR |= RCC_IOPENR_GPIOEEN; + + // Set to output (00: Input, 01: Output, 10: Alternate function, 11: Analog) + // PB4 Direction + GPIOB->MODER &= ~(0x3 << (4 * 2)); // Clear mode bits for PB4 + GPIOB->MODER |= (0x1 << (4 * 2)); // Set mode to output for PB4 + + // PC11 Enable + GPIOC->MODER &= ~(0x3 << (11 * 2)); // Clear mode bits for PC11 + GPIOC->MODER |= (0x1 << (11 * 2)); // Set mode to output for PC11 + + // PE2 Step + GPIOE->MODER &= ~(0x3 << (2 * 2)); // Clear mode bits for PE2 + GPIOE->MODER |= (0x1 << (2 * 2)); // Set mode to output for PE2 + + GPIOC->BSRR |= GPIO_BSRR_BS11; +} /* USER CODE END 0 */ /** @@ -190,9 +212,8 @@ void DMA1_Channel1_IRQHandler(){ */ int main(void) { - /* USER CODE BEGIN 1 */ - /* USER CODE END 1 */ + /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ @@ -218,11 +239,13 @@ int main(void) MX_GPIO_Init(); /* USER CODE BEGIN 2 */ init_UART1_dma(); + init_stepper(); /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ //HAL_UART_Receive_DMA(&huart1, rxBuffer, BUFFER_SIZE); + uint16_t cnt = 0; while (1) { printf("buf: "); @@ -230,6 +253,10 @@ int main(void) printf("0x%02X ", rxBuffer[i]); printf("\n"); SEGGER_SYSVIEW_OnIdle(); + if(cnt++ >= 260-rxBuffer[1]){ + cnt = 0; + GPIOE->ODR ^= GPIO_ODR_OD2; + } /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */