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130 lines
4.0 KiB
C
130 lines
4.0 KiB
C
#include "uart_dmx.h"
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#include "SEGGER_SYSVIEW.h"
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#include "stdio.h"
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#include "stm32g0xx_hal.h"
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#include "system_stm32g0xx.h"
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uint8_t rxBuffer[BUFFER_SIZE];
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uint16_t rxBufferPos = 0;
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void init_UART1_it(){
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RCC->APBENR2 |= RCC_APBENR2_USART1EN;
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RCC->IOPENR |= RCC_IOPENR_GPIOCEN;
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GPIOC->MODER &= ~GPIO_MODER_MODE5; // Alternate function mode on RX pin
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GPIOC->MODER |= GPIO_MODER_MODE5_1;
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GPIOC->AFR[0] &= GPIO_AFRL_AFSEL5;
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GPIOC->AFR[0] |= 1 << GPIO_AFRL_AFSEL5_Pos; // AF1 -> USART1 RX
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USART1->BRR = 128; // 32000000÷250000
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USART1->CR1 = USART_CR1_RE;
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USART1->CR3 |= USART_CR3_EIE; // Interrupt on BREAK (and other errors)
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USART1->CR1 |= USART_CR1_RXNEIE_RXFNEIE; // RX Interrupt
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USART1->CR1 |= USART_CR1_UE;
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HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
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HAL_NVIC_EnableIRQ(USART1_IRQn);
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}
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void init_UART1_dma(){
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RCC->IOPENR |= RCC_IOPENR_GPIOCEN;
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RCC->APBENR2 |= RCC_APBENR2_USART1EN;
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RCC->AHBENR |= RCC_AHBENR_DMA1EN;
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GPIOC->MODER &= ~GPIO_MODER_MODE5; // Alternate function mode on RX pin
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GPIOC->MODER |= GPIO_MODER_MODE5_1;
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GPIOC->AFR[0] &= GPIO_AFRL_AFSEL5;
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GPIOC->AFR[0] |= 1 << GPIO_AFRL_AFSEL5_Pos; // AF1 -> USART1 RX
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USART1->BRR = SystemCoreClock / 250000; // 64000000÷250000
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USART1->CR1 = USART_CR1_RE;
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USART1->CR3 |= USART_CR3_EIE; // Interrupt on BREAK (and other errors)
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USART1->CR3 |= USART_CR3_DMAR; // DMA Receiver mode
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DMA1_Channel1->CCR = (0x02 << DMA_CCR_PL_Pos) | DMA_CCR_MINC | DMA_CCR_TCIE;
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DMA1_Channel1->CMAR = ( uint32_t )&rxBuffer[0];
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DMA1_Channel1->CPAR = ( uint32_t )&(USART1->RDR);
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DMA1_Channel1->CNDTR = 5;
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DMAMUX1_Channel0->CCR &= ~( DMAMUX_CxCR_DMAREQ_ID );
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DMAMUX1_Channel0->CCR |= ( 50 << DMAMUX_CxCR_DMAREQ_ID_Pos ); // 50 -> USART1 RX
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USART1->CR1 |= USART_CR1_UE;
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HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
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HAL_NVIC_EnableIRQ(USART1_IRQn);
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HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
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HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
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}
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void Reset_DMA(void) {
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// Disable the DMA channel
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DMA1_Channel1->CCR &= ~DMA_CCR_EN; // Disable DMA Channel 1
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// Clear the transfer complete flag
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DMA1->IFCR |= DMA_IFCR_CTCIF1; // Clear transfer complete flag for Channel 1
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// Reconfigure the DMA
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DMA1_Channel1->CMAR = (uint32_t)rxBuffer; // Set memory address to the start of the buffer
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DMA1_Channel1->CNDTR = BUFFER_SIZE; // Set number of data items to transfer
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// Enable the DMA channel again
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DMA1_Channel1->CCR |= DMA_CCR_EN; // Enable DMA Channel 1
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}
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void USART1_IRQHandler(){
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SEGGER_SYSVIEW_RecordEnterISR();
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if(USART1->ISR & USART_ISR_RXNE_RXFNE){
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//SEGGER_SYSVIEW_PrintfHost("RXNE");
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//printf("%x ", USART1->RDR);
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rxBuffer[rxBufferPos++] = USART1->RDR;
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if(rxBufferPos >= BUFFER_SIZE){
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rxBufferPos = 0;
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}
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}
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if(USART1->ISR & USART_ISR_FE){
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//TODO read rx==0
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USART1->ICR = USART_ICR_FECF;
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//if(rxBufferPos != 514)
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// printf("FE after %d\n",rxBufferPos);
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//rxBufferPos = 0;
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//DMA1_Channel1->CNDTR = 1;
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SEGGER_SYSVIEW_PrintfHost("FE");
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Reset_DMA();
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//DMA1_Channel1->CCR &= ~( DMA_CCR_EN );
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//DMA1_Channel1->CNDTR = 512;
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//DMA1_Channel1->CMAR = ( uint32_t )&rxBuffer[0];
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//DMA1_Channel1->CCR |= ( DMA_CCR_EN );
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////DMA1_Channel1->CCR |= ( DMA_CCR_EN );
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}
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if(USART1->ISR & USART_ISR_ORE){
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USART1->ICR = USART_ICR_ORECF;
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//printf("ORE\n");
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//SEGGER_SYSVIEW_PrintfHost("ORE");
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}
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if(USART1->ISR & USART_ISR_NE){
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USART1->ICR = USART_ICR_NECF;
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printf("NE\n");
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}
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if(USART1->ISR & USART_ISR_UDR){
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USART1->ICR = USART_ICR_UDRCF;
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printf("UDR\n");
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}
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SEGGER_SYSVIEW_RecordExitISR();
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}
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void DMA1_Channel1_IRQHandler(){
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SEGGER_SYSVIEW_RecordEnterISR();
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if(DMA1->ISR & DMA_ISR_TCIF1){
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DMA1->IFCR = DMA_IFCR_CTCIF1;
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}
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SEGGER_SYSVIEW_PrintfHost("DMA");
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SEGGER_SYSVIEW_RecordExitISR();
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}
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