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344 lines
13 KiB
C
344 lines
13 KiB
C
/**
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******************************************************************************
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* @file stm32g0xx_ll_utils.h
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* @author MCD Application Team
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* @brief Header file of UTILS LL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2018 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@verbatim
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==============================================================================
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##### How to use this driver #####
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==============================================================================
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[..]
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The LL UTILS driver contains a set of generic APIs that can be
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used by user:
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(+) Device electronic signature
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(+) Timing functions
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(+) PLL configuration functions
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@endverbatim
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32G0xx_LL_UTILS_H
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#define STM32G0xx_LL_UTILS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32g0xx.h"
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/** @addtogroup STM32G0xx_LL_Driver
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* @{
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*/
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/** @defgroup UTILS_LL UTILS
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
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* @{
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*/
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/* Max delay can be used in LL_mDelay */
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#define LL_MAX_DELAY 0xFFFFFFFFU
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/**
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* @brief Unique device ID register base address
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*/
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#define UID_BASE_ADDRESS UID_BASE
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/**
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* @brief Flash size data register base address
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*/
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#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
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/**
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* @brief Package data register base address
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*/
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#define PACKAGE_BASE_ADDRESS PACKAGE_BASE
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/**
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* @}
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*/
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/* Private macros ------------------------------------------------------------*/
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/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
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* @{
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*/
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/**
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* @}
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
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* @{
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*/
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/**
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* @brief UTILS PLL structure definition
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*/
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typedef struct
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{
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uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
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This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_PLL_ConfigDomain_SYS(). */
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uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
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This parameter must be a number between Min_Data = 8 and Max_Data = 86
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_PLL_ConfigDomain_SYS(). */
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uint32_t PLLR; /*!< Division for the main system clock.
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This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_PLL_ConfigDomain_SYS(). */
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} LL_UTILS_PLLInitTypeDef;
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/**
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* @brief UTILS System, AHB and APB buses clock configuration structure definition
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*/
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typedef struct
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{
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uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
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This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_SetAHBPrescaler(). */
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uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
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This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_SetAPB1Prescaler(). */
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} LL_UTILS_ClkInitTypeDef;
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
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* @{
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*/
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/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
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* @{
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*/
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#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
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#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
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/**
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* @}
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*/
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/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
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* @{
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*/
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#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
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#define LL_UTILS_PACKAGETYPE_QFP100 0x00000000U /*!< LQFP100 package type */
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#define LL_UTILS_PACKAGETYPE_QFN32_GP 0x00000001U /*!< LQFP32/UFQFPN32 General purpose (GP) */
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#define LL_UTILS_PACKAGETYPE_QFN32_N 0x00000002U /*!< LQFP32/UFQFPN32 N-version */
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#define LL_UTILS_PACKAGETYPE_QFN48_GP 0x00000004U /*!< LQFP48/UFQPN48 General purpose (GP) */
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#define LL_UTILS_PACKAGETYPE_QFN48_N 0x00000005U /*!< LQFP48/UFQPN48 N-version */
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#define LL_UTILS_PACKAGETYPE_WLCSP52 0x00000006U /*!< WLCSP52 */
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#define LL_UTILS_PACKAGETYPE_QFN64_GP 0x00000007U /*!< LQFP64 General purpose (GP) */
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#define LL_UTILS_PACKAGETYPE_QFN64_N 0x00000008U /*!< LQFP64 N-version */
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#define LL_UTILS_PACKAGETYPE_BGA64_N 0x0000000AU /*!< UFBGA64 N-version */
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#define LL_UTILS_PACKAGETYPE_QFP80 0x0000000BU /*!< LQFP80 package type */
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#define LL_UTILS_PACKAGETYPE_BGA100 0x0000000CU /*!< UBGA100 package type */
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#elif defined(STM32G061xx) || defined(STM32G051xx) || defined(STM32G050xx) || defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx)
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#define LL_UTILS_PACKAGETYPE_SO8 0x00000001U /*!< SO8 package type */
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#define LL_UTILS_PACKAGETYPE_WLCSP18 0x00000002U /*!< WLCSP18 package type */
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#define LL_UTILS_PACKAGETYPE_TSSOP20 0x00000003U /*!< TSSOP20 package type */
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#define LL_UTILS_PACKAGETYPE_QFP28 0x00000004U /*!< UFQFPN28 package type */
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#define LL_UTILS_PACKAGETYPE_QFN32 0x00000005U /*!< UFQFPN32 / LQFP32 package type */
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#define LL_UTILS_PACKAGETYPE_QFN48 0x00000007U /*!< UFQFPN48 / LQFP48 package type */
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#elif defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G070xx)
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#define LL_UTILS_PACKAGETYPE_QFN28_GP 0x00000000U /*!< UFQFPN28 general purpose (GP) package type */
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#define LL_UTILS_PACKAGETYPE_QFN28_PD 0x00000001U /*!< UFQFPN28 Power Delivery (PD) */
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#define LL_UTILS_PACKAGETYPE_QFN32_GP 0x00000004U /*!< UFQFPN32 / LQFP32 general purpose (GP) package type */
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#define LL_UTILS_PACKAGETYPE_QFN32_PD 0x00000005U /*!< UFQFPN32 / LQFP32 Power Delivery (PD) package type */
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#define LL_UTILS_PACKAGETYPE_QFN48 0x00000008U /*!< UFQFPN48 / LQFP488 package type */
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#define LL_UTILS_PACKAGETYPE_QFP64 0x0000000CU /*!< LQPF64 package type */
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#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
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* @{
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*/
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/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
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* @{
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*/
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/**
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* @brief Get Word0 of the unique device identifier (UID based on 96 bits)
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* @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
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*/
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__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
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{
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return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
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}
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/**
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* @brief Get Word1 of the unique device identifier (UID based on 96 bits)
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* @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
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*/
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__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
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{
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return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
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}
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/**
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* @brief Get Word2 of the unique device identifier (UID based on 96 bits)
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* @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
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*/
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__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
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{
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return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
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}
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/**
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* @brief Get Flash memory size
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* @note This bitfield indicates the size of the device Flash memory expressed in
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* Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
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* @retval FLASH_SIZE[15:0]: Flash memory size
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*/
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__STATIC_INLINE uint32_t LL_GetFlashSize(void)
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{
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return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0x0000FFFFUL);
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}
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/**
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* @brief Get Package type
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* @retval PKG[3:0]: Package type - This parameter can be a value of @ref UTILS_EC_PACKAGETYPE
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* @if defined(STM32G0C1xx)
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* @arg @ref LL_UTILS_PACKAGETYPE_QFP100
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* @arg @ref LL_UTILS_PACKAGETYPE_QFN32_GP
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* @arg @ref LL_UTILS_PACKAGETYPE_QFN32_N
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* @arg @ref LL_UTILS_PACKAGETYPE_QFN48_GP
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* @arg @ref LL_UTILS_PACKAGETYPE_QFN48_N
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* @arg @ref LL_UTILS_PACKAGETYPE_WLCSP52
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* @arg @ref LL_UTILS_PACKAGETYPE_QFN64_GP
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* @arg @ref LL_UTILS_PACKAGETYPE_QFN64_N
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* @arg @ref LL_UTILS_PACKAGETYPE_BGA64_N
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* @arg @ref LL_UTILS_PACKAGETYPE_QFP80
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* @arg @ref LL_UTILS_PACKAGETYPE_BGA100
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* @elif defined(STM32G061xx) || defined(STM32G041xx)
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* @arg @ref LL_UTILS_PACKAGETYPE_SO8
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* @arg @ref LL_UTILS_PACKAGETYPE_WLCSP18
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* @arg @ref LL_UTILS_PACKAGETYPE_TSSOP20
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* @arg @ref LL_UTILS_PACKAGETYPE_QFP28
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* @arg @ref LL_UTILS_PACKAGETYPE_QFN32
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* @arg @ref LL_UTILS_PACKAGETYPE_QFN48
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* @elif defined(STM32G081xx)
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* @arg @ref LL_UTILS_PACKAGETYPE_QFN28_GP
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* @arg @ref LL_UTILS_PACKAGETYPE_QFN28_PD
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* @arg @ref LL_UTILS_PACKAGETYPE_QFN32_GP
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* @arg @ref LL_UTILS_PACKAGETYPE_QFN32_PD
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* @arg @ref LL_UTILS_PACKAGETYPE_QFN48
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* @arg @ref LL_UTILS_PACKAGETYPE_QFP64
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* @endif
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*
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*/
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__STATIC_INLINE uint32_t LL_GetPackageType(void)
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{
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#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
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return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
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#else
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return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0xFU);
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#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
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}
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/**
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* @}
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*/
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/** @defgroup UTILS_LL_EF_DELAY DELAY
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* @{
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*/
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/**
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* @brief This function configures the Cortex-M SysTick source of the time base.
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* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
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* @note When a RTOS is used, it is recommended to avoid changing the SysTick
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* configuration by calling this function, for a delay use rather osDelay RTOS service.
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* @param Ticks Frequency of Ticks (Hz)
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* @retval None
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*/
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__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
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{
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/* Configure the SysTick to have interrupt in 1ms time base */
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SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
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SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
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SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
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}
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void LL_Init1msTick(uint32_t HCLKFrequency);
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void LL_mDelay(uint32_t Delay);
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/**
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* @}
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*/
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/** @defgroup UTILS_EF_SYSTEM SYSTEM
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* @{
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*/
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void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
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ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
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LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
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ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
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LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
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ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* STM32G0xx_LL_UTILS_H */
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