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1558 lines
64 KiB
C
1558 lines
64 KiB
C
/**
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******************************************************************************
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* @file stm32g0xx_ll_exti.h
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* @author MCD Application Team
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* @brief Header file of EXTI LL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2018 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32G0xx_LL_EXTI_H
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#define STM32G0xx_LL_EXTI_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32g0xx.h"
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/** @addtogroup STM32G0xx_LL_Driver
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* @{
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*/
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#if defined (EXTI)
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/** @defgroup EXTI_LL EXTI
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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#define LL_EXTI_REGISTER_PINPOS_SHFT 16u /*!< Define used to shift pin position in EXTICR register */
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/* Private Macros ------------------------------------------------------------*/
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#if defined(USE_FULL_LL_DRIVER)
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/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
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* @{
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*/
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/**
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* @}
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*/
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#endif /*USE_FULL_LL_DRIVER*/
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/* Exported types ------------------------------------------------------------*/
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#if defined(USE_FULL_LL_DRIVER)
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/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
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* @{
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*/
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typedef struct
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{
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uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
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This parameter can be any combination of @ref EXTI_LL_EC_LINE */
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#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
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uint32_t Line_32_63; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63
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This parameter can be any combination of @ref EXTI_LL_EC_LINE */
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#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
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FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines.
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This parameter can be set either to ENABLE or DISABLE */
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uint8_t Mode; /*!< Specifies the mode for the EXTI lines.
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This parameter can be a value of @ref EXTI_LL_EC_MODE. */
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uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
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This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
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} LL_EXTI_InitTypeDef;
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/**
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* @}
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*/
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#endif /*USE_FULL_LL_DRIVER*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
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* @{
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*/
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/** @defgroup EXTI_LL_EC_LINE LINE
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* @{
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*/
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#define LL_EXTI_LINE_0 EXTI_IMR1_IM0 /*!< Extended line 0 */
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#define LL_EXTI_LINE_1 EXTI_IMR1_IM1 /*!< Extended line 1 */
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#define LL_EXTI_LINE_2 EXTI_IMR1_IM2 /*!< Extended line 2 */
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#define LL_EXTI_LINE_3 EXTI_IMR1_IM3 /*!< Extended line 3 */
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#define LL_EXTI_LINE_4 EXTI_IMR1_IM4 /*!< Extended line 4 */
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#define LL_EXTI_LINE_5 EXTI_IMR1_IM5 /*!< Extended line 5 */
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#define LL_EXTI_LINE_6 EXTI_IMR1_IM6 /*!< Extended line 6 */
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#define LL_EXTI_LINE_7 EXTI_IMR1_IM7 /*!< Extended line 7 */
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#define LL_EXTI_LINE_8 EXTI_IMR1_IM8 /*!< Extended line 8 */
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#define LL_EXTI_LINE_9 EXTI_IMR1_IM9 /*!< Extended line 9 */
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#define LL_EXTI_LINE_10 EXTI_IMR1_IM10 /*!< Extended line 10 */
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#define LL_EXTI_LINE_11 EXTI_IMR1_IM11 /*!< Extended line 11 */
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#define LL_EXTI_LINE_12 EXTI_IMR1_IM12 /*!< Extended line 12 */
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#define LL_EXTI_LINE_13 EXTI_IMR1_IM13 /*!< Extended line 13 */
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#define LL_EXTI_LINE_14 EXTI_IMR1_IM14 /*!< Extended line 14 */
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#define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */
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#if defined(EXTI_IMR1_IM16)
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#define LL_EXTI_LINE_16 EXTI_IMR1_IM16 /*!< Extended line 16 */
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#endif /* EXTI_IMR1_IM16 */
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#if defined(EXTI_IMR1_IM17)
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#define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */
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#endif /* EXTI_IMR1_IM17 */
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#if defined(EXTI_IMR1_IM18)
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#define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */
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#endif /* EXTI_IMR1_IM18 */
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#define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */
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#if defined(EXTI_IMR1_IM20)
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#define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */
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#endif /* EXTI_IMR1_IM20 */
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#if defined(EXTI_IMR1_IM21)
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#define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */
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#endif /* EXTI_IMR1_IM21 */
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#if defined(EXTI_IMR1_IM22)
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#define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */
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#endif /* EXTI_IMR1_IM22 */
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#define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */
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#if defined(EXTI_IMR1_IM24)
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#define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */
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#endif /* EXTI_IMR1_IM24 */
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#if defined(EXTI_IMR1_IM25)
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#define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */
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#endif /* EXTI_IMR1_IM25 */
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#if defined(EXTI_IMR1_IM26)
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#define LL_EXTI_LINE_26 EXTI_IMR1_IM26 /*!< Extended line 26 */
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#endif /* EXTI_IMR1_IM26 */
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#if defined(EXTI_IMR1_IM27)
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#define LL_EXTI_LINE_27 EXTI_IMR1_IM27 /*!< Extended line 27 */
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#endif /* EXTI_IMR1_IM27 */
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#if defined(EXTI_IMR1_IM28)
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#define LL_EXTI_LINE_28 EXTI_IMR1_IM28 /*!< Extended line 28 */
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#endif /* EXTI_IMR1_IM28 */
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#if defined(EXTI_IMR1_IM29)
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#define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */
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#endif /* EXTI_IMR1_IM29 */
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#if defined(EXTI_IMR1_IM30)
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#define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */
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#endif /* EXTI_IMR1_IM30 */
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#if defined(EXTI_IMR1_IM31)
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#define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */
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#endif /* EXTI_IMR1_IM31 */
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#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM /*!< All Extended line not reserved*/
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#if defined(EXTI_IMR2_IM32)
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#define LL_EXTI_LINE_32 EXTI_IMR2_IM32 /*!< Extended line 32 */
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#endif /* EXTI_IMR2_IM32 */
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#if defined(EXTI_IMR2_IM33)
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#define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */
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#endif /* EXTI_IMR2_IM33 */
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#if defined(EXTI_IMR2_IM34)
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#define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */
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#endif /* EXTI_IMR2_IM34 */
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#if defined(EXTI_IMR2_IM35)
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#define LL_EXTI_LINE_35 EXTI_IMR2_IM35 /*!< Extended line 35 */
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#endif /* EXTI_IMR2_IM35 */
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#if defined(EXTI_IMR2_IM36)
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#define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */
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#endif /* EXTI_IMR2_IM36 */
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#if defined(EXTI_IMR2_IM32) || defined(EXTI_IMR2_IM33) || defined(EXTI_IMR2_IM34) || defined(EXTI_IMR2_IM35) || defined(EXTI_IMR2_IM36)
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#define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< All Extended line not reserved*/
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#endif /* EXTI_IMR2_IM32 || EXTI_IMR2_IM33 || EXTI_IMR2_IM34 || EXTI_IMR2_IM35 || EXTI_IMR2_IM36 */
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#define LL_EXTI_LINE_ALL 0xFFFFFFFFU /*!< All Extended line */
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#if defined(USE_FULL_LL_DRIVER)
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#define LL_EXTI_LINE_NONE 0x00000000U /*!< None Extended line */
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#endif /*USE_FULL_LL_DRIVER*/
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/** @defgroup EXTI_LL_EC_CONFIG_PORT EXTI CONFIG PORT
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* @{
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*/
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#define LL_EXTI_CONFIG_PORTA 0U /*!< EXTI PORT A */
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#define LL_EXTI_CONFIG_PORTB EXTI_EXTICR1_EXTI0_0 /*!< EXTI PORT B */
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#define LL_EXTI_CONFIG_PORTC EXTI_EXTICR1_EXTI0_1 /*!< EXTI PORT C */
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#if defined(GPIOD_BASE)
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#define LL_EXTI_CONFIG_PORTD (EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT D */
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#endif /*GPIOD_BASE*/
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#if defined(GPIOE_BASE)
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#define LL_EXTI_CONFIG_PORTE EXTI_EXTICR1_EXTI0_2 /*!< EXTI PORT E */
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#endif /*GPIOE_BASE*/
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#define LL_EXTI_CONFIG_PORTF (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT F */
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/**
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* @}
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*/
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/** @defgroup EXTI_LL_EC_CONFIG_LINE EXTI CONFIG LINE
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* @{
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*/
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#define LL_EXTI_CONFIG_LINE0 ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */
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#define LL_EXTI_CONFIG_LINE1 ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */
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#define LL_EXTI_CONFIG_LINE2 ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_16 | EXTICR[0] */
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#define LL_EXTI_CONFIG_LINE3 ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_24 | EXTICR[0] */
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#define LL_EXTI_CONFIG_LINE4 ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */
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#define LL_EXTI_CONFIG_LINE5 ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */
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#define LL_EXTI_CONFIG_LINE6 ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_16 | EXTICR[1] */
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#define LL_EXTI_CONFIG_LINE7 ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_24 | EXTICR[1] */
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#define LL_EXTI_CONFIG_LINE8 ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */
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#define LL_EXTI_CONFIG_LINE9 ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */
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#define LL_EXTI_CONFIG_LINE10 ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_16 | EXTICR[2] */
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#define LL_EXTI_CONFIG_LINE11 ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_24 | EXTICR[2] */
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#define LL_EXTI_CONFIG_LINE12 ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */
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#define LL_EXTI_CONFIG_LINE13 ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */
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#define LL_EXTI_CONFIG_LINE14 ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_16 | EXTICR[3] */
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#define LL_EXTI_CONFIG_LINE15 ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_24 | EXTICR[3] */
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/**
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* @}
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*/
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/**
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* @}
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*/
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#if defined(USE_FULL_LL_DRIVER)
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/** @defgroup EXTI_LL_EC_MODE Mode
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* @{
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*/
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#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */
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#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */
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#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
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/**
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* @}
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*/
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/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
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* @{
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*/
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#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */
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#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */
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#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */
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#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
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/**
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* @}
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*/
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#endif /*USE_FULL_LL_DRIVER*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
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* @{
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*/
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/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
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* @{
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*/
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/**
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* @brief Write a value in EXTI register
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* @param __REG__ Register to be written
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* @param __VALUE__ Value to be written in the register
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* @retval None
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*/
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#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
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/**
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* @brief Read a value in EXTI register
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* @param __REG__ Register to be read
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* @retval Register value
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*/
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#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
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* @{
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*/
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/** @defgroup EXTI_LL_EF_IT_Management IT_Management
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* @{
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*/
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/**
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* @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31
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* @note The reset value for the direct or internal lines (see RM)
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* is set to 1 in order to enable the interrupt by default.
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* Bits are set automatically at Power on.
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* @rmtoll IMR1 IMx LL_EXTI_EnableIT_0_31
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* @param ExtiLine This parameter can be one of the following values:
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* @arg @ref LL_EXTI_LINE_0
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* @arg @ref LL_EXTI_LINE_1
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* @arg @ref LL_EXTI_LINE_2
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* @arg @ref LL_EXTI_LINE_3
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* @arg @ref LL_EXTI_LINE_4
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* @arg @ref LL_EXTI_LINE_5
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* @arg @ref LL_EXTI_LINE_6
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* @arg @ref LL_EXTI_LINE_7
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* @arg @ref LL_EXTI_LINE_8
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* @arg @ref LL_EXTI_LINE_9
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* @arg @ref LL_EXTI_LINE_10
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* @arg @ref LL_EXTI_LINE_11
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* @arg @ref LL_EXTI_LINE_12
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* @arg @ref LL_EXTI_LINE_13
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* @arg @ref LL_EXTI_LINE_14
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* @arg @ref LL_EXTI_LINE_15
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* @arg @ref LL_EXTI_LINE_16
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* @arg @ref LL_EXTI_LINE_17
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* @arg @ref LL_EXTI_LINE_18
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* @arg @ref LL_EXTI_LINE_19
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* @arg @ref LL_EXTI_LINE_21
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* @arg @ref LL_EXTI_LINE_23
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* @arg @ref LL_EXTI_LINE_25
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* @arg @ref LL_EXTI_LINE_26
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* @arg @ref LL_EXTI_LINE_27
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* @arg @ref LL_EXTI_LINE_28
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* @arg @ref LL_EXTI_LINE_29
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* @arg @ref LL_EXTI_LINE_30
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* @arg @ref LL_EXTI_LINE_31
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* @arg @ref LL_EXTI_LINE_ALL_0_31
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* @note Please check each device line mapping for EXTI Line availability
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* @retval None
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*/
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__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
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{
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SET_BIT(EXTI->IMR1, ExtiLine);
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}
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#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
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/**
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* @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63
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* @note The reset value for the direct lines (lines 32 & 33)
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* is set to 1 in order to enable the interrupt by default.
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* Bits are set automatically at Power on.
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* @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63
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* @param ExtiLine This parameter can be one of the following values:
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* @arg @ref LL_EXTI_LINE_32
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* @arg @ref LL_EXTI_LINE_33
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* @arg @ref LL_EXTI_LINE_34
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* @arg @ref LL_EXTI_LINE_35
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* @arg @ref LL_EXTI_LINE_36
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* @arg @ref LL_EXTI_LINE_ALL_32_63
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* @note Please check each device line mapping for EXTI Line availability
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* @retval None
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*/
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__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
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{
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SET_BIT(EXTI->IMR2, ExtiLine);
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}
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#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
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/**
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* @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
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* @note The reset value for the direct or internal lines (see RM)
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* is set to 1 in order to enable the interrupt by default.
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* Bits are set automatically at Power on.
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* @rmtoll IMR1 IMx LL_EXTI_DisableIT_0_31
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* @param ExtiLine This parameter can be one of the following values:
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* @arg @ref LL_EXTI_LINE_0
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* @arg @ref LL_EXTI_LINE_1
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* @arg @ref LL_EXTI_LINE_2
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* @arg @ref LL_EXTI_LINE_3
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* @arg @ref LL_EXTI_LINE_4
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* @arg @ref LL_EXTI_LINE_5
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* @arg @ref LL_EXTI_LINE_6
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* @arg @ref LL_EXTI_LINE_7
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* @arg @ref LL_EXTI_LINE_8
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* @arg @ref LL_EXTI_LINE_9
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* @arg @ref LL_EXTI_LINE_10
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* @arg @ref LL_EXTI_LINE_11
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* @arg @ref LL_EXTI_LINE_12
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* @arg @ref LL_EXTI_LINE_13
|
|
* @arg @ref LL_EXTI_LINE_14
|
|
* @arg @ref LL_EXTI_LINE_15
|
|
* @arg @ref LL_EXTI_LINE_16
|
|
* @arg @ref LL_EXTI_LINE_17
|
|
* @arg @ref LL_EXTI_LINE_18
|
|
* @arg @ref LL_EXTI_LINE_19
|
|
* @arg @ref LL_EXTI_LINE_21
|
|
* @arg @ref LL_EXTI_LINE_23
|
|
* @arg @ref LL_EXTI_LINE_25
|
|
* @arg @ref LL_EXTI_LINE_26
|
|
* @arg @ref LL_EXTI_LINE_27
|
|
* @arg @ref LL_EXTI_LINE_28
|
|
* @arg @ref LL_EXTI_LINE_29
|
|
* @arg @ref LL_EXTI_LINE_30
|
|
* @arg @ref LL_EXTI_LINE_31
|
|
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
|
|
{
|
|
CLEAR_BIT(EXTI->IMR1, ExtiLine);
|
|
}
|
|
|
|
#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
|
|
/**
|
|
* @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63
|
|
* @note The reset value for the direct lines (lines 32 & 33)
|
|
* is set to 1 in order to enable the interrupt by default.
|
|
* Bits are set automatically at Power on.
|
|
* @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63
|
|
* @param ExtiLine This parameter can be one of the following values:
|
|
* @arg @ref LL_EXTI_LINE_32
|
|
* @arg @ref LL_EXTI_LINE_33
|
|
* @arg @ref LL_EXTI_LINE_34
|
|
* @arg @ref LL_EXTI_LINE_35
|
|
* @arg @ref LL_EXTI_LINE_36
|
|
* @arg @ref LL_EXTI_LINE_ALL_32_63
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)
|
|
{
|
|
CLEAR_BIT(EXTI->IMR2, ExtiLine);
|
|
}
|
|
#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
|
|
|
|
/**
|
|
* @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
|
|
* @note The reset value for the direct or internal lines (see RM)
|
|
* is set to 1 in order to enable the interrupt by default.
|
|
* Bits are set automatically at Power on.
|
|
* @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31
|
|
* @param ExtiLine This parameter can be one of the following values:
|
|
* @arg @ref LL_EXTI_LINE_0
|
|
* @arg @ref LL_EXTI_LINE_1
|
|
* @arg @ref LL_EXTI_LINE_2
|
|
* @arg @ref LL_EXTI_LINE_3
|
|
* @arg @ref LL_EXTI_LINE_4
|
|
* @arg @ref LL_EXTI_LINE_5
|
|
* @arg @ref LL_EXTI_LINE_6
|
|
* @arg @ref LL_EXTI_LINE_7
|
|
* @arg @ref LL_EXTI_LINE_8
|
|
* @arg @ref LL_EXTI_LINE_9
|
|
* @arg @ref LL_EXTI_LINE_10
|
|
* @arg @ref LL_EXTI_LINE_11
|
|
* @arg @ref LL_EXTI_LINE_12
|
|
* @arg @ref LL_EXTI_LINE_13
|
|
* @arg @ref LL_EXTI_LINE_14
|
|
* @arg @ref LL_EXTI_LINE_15
|
|
* @arg @ref LL_EXTI_LINE_16
|
|
* @arg @ref LL_EXTI_LINE_17
|
|
* @arg @ref LL_EXTI_LINE_18
|
|
* @arg @ref LL_EXTI_LINE_19
|
|
* @arg @ref LL_EXTI_LINE_21
|
|
* @arg @ref LL_EXTI_LINE_23
|
|
* @arg @ref LL_EXTI_LINE_25
|
|
* @arg @ref LL_EXTI_LINE_26
|
|
* @arg @ref LL_EXTI_LINE_27
|
|
* @arg @ref LL_EXTI_LINE_28
|
|
* @arg @ref LL_EXTI_LINE_29
|
|
* @arg @ref LL_EXTI_LINE_30
|
|
* @arg @ref LL_EXTI_LINE_31
|
|
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
|
|
{
|
|
return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
|
|
}
|
|
|
|
#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
|
|
/**
|
|
* @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63
|
|
* @note The reset value for the direct lines (lines 32 & 33)
|
|
* is set to 1 in order to enable the interrupt by default.
|
|
* @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63
|
|
* @param ExtiLine This parameter can be one of the following values:
|
|
* @arg @ref LL_EXTI_LINE_32
|
|
* @arg @ref LL_EXTI_LINE_33
|
|
* @arg @ref LL_EXTI_LINE_34
|
|
* @arg @ref LL_EXTI_LINE_35
|
|
* @arg @ref LL_EXTI_LINE_36
|
|
* @arg @ref LL_EXTI_LINE_ALL_32_63
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
|
|
{
|
|
return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
|
|
}
|
|
#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup EXTI_LL_EF_Event_Management Event_Management
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enable ExtiLine Event request for Lines in range 0 to 31
|
|
* @rmtoll EMR1 EMx LL_EXTI_EnableEvent_0_31
|
|
* @param ExtiLine This parameter can be one of the following values:
|
|
* @arg @ref LL_EXTI_LINE_0
|
|
* @arg @ref LL_EXTI_LINE_1
|
|
* @arg @ref LL_EXTI_LINE_2
|
|
* @arg @ref LL_EXTI_LINE_3
|
|
* @arg @ref LL_EXTI_LINE_4
|
|
* @arg @ref LL_EXTI_LINE_5
|
|
* @arg @ref LL_EXTI_LINE_6
|
|
* @arg @ref LL_EXTI_LINE_7
|
|
* @arg @ref LL_EXTI_LINE_8
|
|
* @arg @ref LL_EXTI_LINE_9
|
|
* @arg @ref LL_EXTI_LINE_10
|
|
* @arg @ref LL_EXTI_LINE_11
|
|
* @arg @ref LL_EXTI_LINE_12
|
|
* @arg @ref LL_EXTI_LINE_13
|
|
* @arg @ref LL_EXTI_LINE_14
|
|
* @arg @ref LL_EXTI_LINE_15
|
|
* @arg @ref LL_EXTI_LINE_16
|
|
* @arg @ref LL_EXTI_LINE_17
|
|
* @arg @ref LL_EXTI_LINE_18
|
|
* @arg @ref LL_EXTI_LINE_19
|
|
* @arg @ref LL_EXTI_LINE_21
|
|
* @arg @ref LL_EXTI_LINE_23
|
|
* @arg @ref LL_EXTI_LINE_25
|
|
* @arg @ref LL_EXTI_LINE_26
|
|
* @arg @ref LL_EXTI_LINE_27
|
|
* @arg @ref LL_EXTI_LINE_28
|
|
* @arg @ref LL_EXTI_LINE_29
|
|
* @arg @ref LL_EXTI_LINE_30
|
|
* @arg @ref LL_EXTI_LINE_31
|
|
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
|
|
{
|
|
SET_BIT(EXTI->EMR1, ExtiLine);
|
|
|
|
}
|
|
|
|
#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
|
|
/**
|
|
* @brief Enable ExtiLine Event request for Lines in range 32 to 63
|
|
* @rmtoll EMR2 EMx LL_EXTI_EnableEvent_32_63
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_32
|
|
* @arg @ref LL_EXTI_LINE_33
|
|
* @arg @ref LL_EXTI_LINE_34
|
|
* @arg @ref LL_EXTI_LINE_35
|
|
* @arg @ref LL_EXTI_LINE_36
|
|
* @arg @ref LL_EXTI_LINE_ALL_32_63
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
|
|
{
|
|
SET_BIT(EXTI->EMR2, ExtiLine);
|
|
}
|
|
#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
|
|
/**
|
|
* @brief Disable ExtiLine Event request for Lines in range 0 to 31
|
|
* @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31
|
|
* @param ExtiLine This parameter can be one of the following values:
|
|
* @arg @ref LL_EXTI_LINE_0
|
|
* @arg @ref LL_EXTI_LINE_1
|
|
* @arg @ref LL_EXTI_LINE_2
|
|
* @arg @ref LL_EXTI_LINE_3
|
|
* @arg @ref LL_EXTI_LINE_4
|
|
* @arg @ref LL_EXTI_LINE_5
|
|
* @arg @ref LL_EXTI_LINE_6
|
|
* @arg @ref LL_EXTI_LINE_7
|
|
* @arg @ref LL_EXTI_LINE_8
|
|
* @arg @ref LL_EXTI_LINE_9
|
|
* @arg @ref LL_EXTI_LINE_10
|
|
* @arg @ref LL_EXTI_LINE_11
|
|
* @arg @ref LL_EXTI_LINE_12
|
|
* @arg @ref LL_EXTI_LINE_13
|
|
* @arg @ref LL_EXTI_LINE_14
|
|
* @arg @ref LL_EXTI_LINE_15
|
|
* @arg @ref LL_EXTI_LINE_16
|
|
* @arg @ref LL_EXTI_LINE_17
|
|
* @arg @ref LL_EXTI_LINE_18
|
|
* @arg @ref LL_EXTI_LINE_19
|
|
* @arg @ref LL_EXTI_LINE_21
|
|
* @arg @ref LL_EXTI_LINE_23
|
|
* @arg @ref LL_EXTI_LINE_25
|
|
* @arg @ref LL_EXTI_LINE_26
|
|
* @arg @ref LL_EXTI_LINE_27
|
|
* @arg @ref LL_EXTI_LINE_28
|
|
* @arg @ref LL_EXTI_LINE_29
|
|
* @arg @ref LL_EXTI_LINE_30
|
|
* @arg @ref LL_EXTI_LINE_31
|
|
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
|
|
{
|
|
CLEAR_BIT(EXTI->EMR1, ExtiLine);
|
|
}
|
|
|
|
#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
|
|
/**
|
|
* @brief Disable ExtiLine Event request for Lines in range 32 to 63
|
|
* @rmtoll EMR2 EMx LL_EXTI_DisableEvent_32_63
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_32
|
|
* @arg @ref LL_EXTI_LINE_33
|
|
* @arg @ref LL_EXTI_LINE_34
|
|
* @arg @ref LL_EXTI_LINE_35
|
|
* @arg @ref LL_EXTI_LINE_36
|
|
* @arg @ref LL_EXTI_LINE_ALL_32_63
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
|
|
{
|
|
CLEAR_BIT(EXTI->EMR2, ExtiLine);
|
|
}
|
|
#endif
|
|
/**
|
|
* @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
|
|
* @rmtoll EMR1 EMx LL_EXTI_IsEnabledEvent_0_31
|
|
* @param ExtiLine This parameter can be one of the following values:
|
|
* @arg @ref LL_EXTI_LINE_0
|
|
* @arg @ref LL_EXTI_LINE_1
|
|
* @arg @ref LL_EXTI_LINE_2
|
|
* @arg @ref LL_EXTI_LINE_3
|
|
* @arg @ref LL_EXTI_LINE_4
|
|
* @arg @ref LL_EXTI_LINE_5
|
|
* @arg @ref LL_EXTI_LINE_6
|
|
* @arg @ref LL_EXTI_LINE_7
|
|
* @arg @ref LL_EXTI_LINE_8
|
|
* @arg @ref LL_EXTI_LINE_9
|
|
* @arg @ref LL_EXTI_LINE_10
|
|
* @arg @ref LL_EXTI_LINE_11
|
|
* @arg @ref LL_EXTI_LINE_12
|
|
* @arg @ref LL_EXTI_LINE_13
|
|
* @arg @ref LL_EXTI_LINE_14
|
|
* @arg @ref LL_EXTI_LINE_15
|
|
* @arg @ref LL_EXTI_LINE_16
|
|
* @arg @ref LL_EXTI_LINE_17
|
|
* @arg @ref LL_EXTI_LINE_18
|
|
* @arg @ref LL_EXTI_LINE_19
|
|
* @arg @ref LL_EXTI_LINE_21
|
|
* @arg @ref LL_EXTI_LINE_23
|
|
* @arg @ref LL_EXTI_LINE_25
|
|
* @arg @ref LL_EXTI_LINE_26
|
|
* @arg @ref LL_EXTI_LINE_27
|
|
* @arg @ref LL_EXTI_LINE_28
|
|
* @arg @ref LL_EXTI_LINE_29
|
|
* @arg @ref LL_EXTI_LINE_30
|
|
* @arg @ref LL_EXTI_LINE_31
|
|
* @arg @ref LL_EXTI_LINE_ALL_0_31
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
|
|
{
|
|
return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
|
|
}
|
|
|
|
#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
|
|
/**
|
|
* @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63
|
|
* @rmtoll EMR2 EMx LL_EXTI_IsEnabledEvent_32_63
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_32
|
|
* @arg @ref LL_EXTI_LINE_33
|
|
* @arg @ref LL_EXTI_LINE_34
|
|
* @arg @ref LL_EXTI_LINE_35
|
|
* @arg @ref LL_EXTI_LINE_36
|
|
* @arg @ref LL_EXTI_LINE_ALL_32_63
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
|
|
{
|
|
return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
|
|
}
|
|
#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
|
|
* @note The configurable wakeup lines are edge-triggered. No glitch must be
|
|
* generated on these lines. If a rising edge on a configurable interrupt
|
|
* line occurs during a write operation in the EXTI_RTSR register, the
|
|
* pending bit is not set.
|
|
* Rising and falling edge triggers can be set for
|
|
* the same interrupt line. In this case, both generate a trigger
|
|
* condition.
|
|
* @rmtoll RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_0
|
|
* @arg @ref LL_EXTI_LINE_1
|
|
* @arg @ref LL_EXTI_LINE_2
|
|
* @arg @ref LL_EXTI_LINE_3
|
|
* @arg @ref LL_EXTI_LINE_4
|
|
* @arg @ref LL_EXTI_LINE_5
|
|
* @arg @ref LL_EXTI_LINE_6
|
|
* @arg @ref LL_EXTI_LINE_7
|
|
* @arg @ref LL_EXTI_LINE_8
|
|
* @arg @ref LL_EXTI_LINE_9
|
|
* @arg @ref LL_EXTI_LINE_10
|
|
* @arg @ref LL_EXTI_LINE_11
|
|
* @arg @ref LL_EXTI_LINE_12
|
|
* @arg @ref LL_EXTI_LINE_13
|
|
* @arg @ref LL_EXTI_LINE_14
|
|
* @arg @ref LL_EXTI_LINE_15
|
|
* @arg @ref LL_EXTI_LINE_16
|
|
* @arg @ref LL_EXTI_LINE_17
|
|
* @arg @ref LL_EXTI_LINE_18
|
|
* @arg @ref LL_EXTI_LINE_20
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
|
|
{
|
|
SET_BIT(EXTI->RTSR1, ExtiLine);
|
|
|
|
}
|
|
#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
|
|
/**
|
|
* @brief Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
|
|
* @note The configurable wakeup lines are edge-triggered. No glitch must be
|
|
* generated on these lines. If a rising edge on a configurable interrupt
|
|
* line occurs during a write operation in the EXTI_RTSR register, the
|
|
* pending bit is not set.
|
|
* Rising and falling edge triggers can be set for
|
|
* the same interrupt line. In this case, both generate a trigger
|
|
* condition.
|
|
* @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_34
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
|
|
{
|
|
SET_BIT(EXTI->RTSR2, ExtiLine);
|
|
|
|
}
|
|
#endif /* STM32G0C1xx || STM32G0B1xx */
|
|
|
|
/**
|
|
* @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
|
|
* @note The configurable wakeup lines are edge-triggered. No glitch must be
|
|
* generated on these lines. If a rising edge on a configurable interrupt
|
|
* line occurs during a write operation in the EXTI_RTSR register, the
|
|
* pending bit is not set.
|
|
* Rising and falling edge triggers can be set for
|
|
* the same interrupt line. In this case, both generate a trigger
|
|
* condition.
|
|
* @rmtoll RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_0
|
|
* @arg @ref LL_EXTI_LINE_1
|
|
* @arg @ref LL_EXTI_LINE_2
|
|
* @arg @ref LL_EXTI_LINE_3
|
|
* @arg @ref LL_EXTI_LINE_4
|
|
* @arg @ref LL_EXTI_LINE_5
|
|
* @arg @ref LL_EXTI_LINE_6
|
|
* @arg @ref LL_EXTI_LINE_7
|
|
* @arg @ref LL_EXTI_LINE_8
|
|
* @arg @ref LL_EXTI_LINE_9
|
|
* @arg @ref LL_EXTI_LINE_10
|
|
* @arg @ref LL_EXTI_LINE_11
|
|
* @arg @ref LL_EXTI_LINE_12
|
|
* @arg @ref LL_EXTI_LINE_13
|
|
* @arg @ref LL_EXTI_LINE_14
|
|
* @arg @ref LL_EXTI_LINE_15
|
|
* @arg @ref LL_EXTI_LINE_16
|
|
* @arg @ref LL_EXTI_LINE_17
|
|
* @arg @ref LL_EXTI_LINE_18
|
|
* @arg @ref LL_EXTI_LINE_20
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
|
|
{
|
|
CLEAR_BIT(EXTI->RTSR1, ExtiLine);
|
|
|
|
}
|
|
|
|
#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
|
|
/**
|
|
* @brief Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
|
|
* @note The configurable wakeup lines are edge-triggered. No glitch must be
|
|
* generated on these lines. If a rising edge on a configurable interrupt
|
|
* line occurs during a write operation in the EXTI_RTSR register, the
|
|
* pending bit is not set.
|
|
* Rising and falling edge triggers can be set for
|
|
* the same interrupt line. In this case, both generate a trigger
|
|
* condition.
|
|
* @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_34
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)
|
|
{
|
|
CLEAR_BIT(EXTI->RTSR2, ExtiLine);
|
|
|
|
}
|
|
#endif /* STM32G0C1xx || STM32G0B1xx */
|
|
|
|
/**
|
|
* @brief Check if rising edge trigger is enabled for Lines in range 0 to 31
|
|
* @rmtoll RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_0
|
|
* @arg @ref LL_EXTI_LINE_1
|
|
* @arg @ref LL_EXTI_LINE_2
|
|
* @arg @ref LL_EXTI_LINE_3
|
|
* @arg @ref LL_EXTI_LINE_4
|
|
* @arg @ref LL_EXTI_LINE_5
|
|
* @arg @ref LL_EXTI_LINE_6
|
|
* @arg @ref LL_EXTI_LINE_7
|
|
* @arg @ref LL_EXTI_LINE_8
|
|
* @arg @ref LL_EXTI_LINE_9
|
|
* @arg @ref LL_EXTI_LINE_10
|
|
* @arg @ref LL_EXTI_LINE_11
|
|
* @arg @ref LL_EXTI_LINE_12
|
|
* @arg @ref LL_EXTI_LINE_13
|
|
* @arg @ref LL_EXTI_LINE_14
|
|
* @arg @ref LL_EXTI_LINE_15
|
|
* @arg @ref LL_EXTI_LINE_16
|
|
* @arg @ref LL_EXTI_LINE_17
|
|
* @arg @ref LL_EXTI_LINE_20
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
|
|
{
|
|
return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
|
|
}
|
|
|
|
#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
|
|
/**
|
|
* @brief Check if rising edge trigger is enabled for Lines in range 32 to 63
|
|
* @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_34
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine)
|
|
{
|
|
return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
|
|
}
|
|
#endif /* STM32G0C1xx || STM32G0B1xx */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
|
|
* @note The configurable wakeup lines are edge-triggered. No glitch must be
|
|
* generated on these lines. If a falling edge on a configurable interrupt
|
|
* line occurs during a write operation in the EXTI_FTSR register, the
|
|
* pending bit is not set.
|
|
* Rising and falling edge triggers can be set for
|
|
* the same interrupt line. In this case, both generate a trigger
|
|
* condition.
|
|
* @rmtoll FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_0
|
|
* @arg @ref LL_EXTI_LINE_1
|
|
* @arg @ref LL_EXTI_LINE_2
|
|
* @arg @ref LL_EXTI_LINE_3
|
|
* @arg @ref LL_EXTI_LINE_4
|
|
* @arg @ref LL_EXTI_LINE_5
|
|
* @arg @ref LL_EXTI_LINE_6
|
|
* @arg @ref LL_EXTI_LINE_7
|
|
* @arg @ref LL_EXTI_LINE_8
|
|
* @arg @ref LL_EXTI_LINE_9
|
|
* @arg @ref LL_EXTI_LINE_10
|
|
* @arg @ref LL_EXTI_LINE_11
|
|
* @arg @ref LL_EXTI_LINE_12
|
|
* @arg @ref LL_EXTI_LINE_13
|
|
* @arg @ref LL_EXTI_LINE_14
|
|
* @arg @ref LL_EXTI_LINE_15
|
|
* @arg @ref LL_EXTI_LINE_16
|
|
* @arg @ref LL_EXTI_LINE_17
|
|
* @arg @ref LL_EXTI_LINE_18
|
|
* @arg @ref LL_EXTI_LINE_20
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
|
|
{
|
|
SET_BIT(EXTI->FTSR1, ExtiLine);
|
|
}
|
|
|
|
#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
|
|
/**
|
|
* @brief Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
|
|
* @note The configurable wakeup lines are edge-triggered. No glitch must be
|
|
* generated on these lines. If a falling edge on a configurable interrupt
|
|
* line occurs during a write operation in the EXTI_FTSR register, the
|
|
* pending bit is not set.
|
|
* Rising and falling edge triggers can be set for
|
|
* the same interrupt line. In this case, both generate a trigger
|
|
* condition.
|
|
* @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_34
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)
|
|
{
|
|
SET_BIT(EXTI->FTSR2, ExtiLine);
|
|
}
|
|
#endif /* STM32G0C1xx || STM32G0B1xx */
|
|
|
|
/**
|
|
* @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
|
|
* @note The configurable wakeup lines are edge-triggered. No glitch must be
|
|
* generated on these lines. If a Falling edge on a configurable interrupt
|
|
* line occurs during a write operation in the EXTI_FTSR register, the
|
|
* pending bit is not set.
|
|
* Rising and falling edge triggers can be set for the same interrupt line.
|
|
* In this case, both generate a trigger condition.
|
|
* @rmtoll FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_0
|
|
* @arg @ref LL_EXTI_LINE_1
|
|
* @arg @ref LL_EXTI_LINE_2
|
|
* @arg @ref LL_EXTI_LINE_3
|
|
* @arg @ref LL_EXTI_LINE_4
|
|
* @arg @ref LL_EXTI_LINE_5
|
|
* @arg @ref LL_EXTI_LINE_6
|
|
* @arg @ref LL_EXTI_LINE_7
|
|
* @arg @ref LL_EXTI_LINE_8
|
|
* @arg @ref LL_EXTI_LINE_9
|
|
* @arg @ref LL_EXTI_LINE_10
|
|
* @arg @ref LL_EXTI_LINE_11
|
|
* @arg @ref LL_EXTI_LINE_12
|
|
* @arg @ref LL_EXTI_LINE_13
|
|
* @arg @ref LL_EXTI_LINE_14
|
|
* @arg @ref LL_EXTI_LINE_15
|
|
* @arg @ref LL_EXTI_LINE_16
|
|
* @arg @ref LL_EXTI_LINE_17
|
|
* @arg @ref LL_EXTI_LINE_18
|
|
* @arg @ref LL_EXTI_LINE_20
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
|
|
{
|
|
CLEAR_BIT(EXTI->FTSR1, ExtiLine);
|
|
}
|
|
|
|
#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
|
|
/**
|
|
* @brief Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
|
|
* @note The configurable wakeup lines are edge-triggered. No glitch must be
|
|
* generated on these lines. If a Falling edge on a configurable interrupt
|
|
* line occurs during a write operation in the EXTI_FTSR register, the
|
|
* pending bit is not set.
|
|
* Rising and falling edge triggers can be set for the same interrupt line.
|
|
* In this case, both generate a trigger condition.
|
|
* @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_34
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)
|
|
{
|
|
CLEAR_BIT(EXTI->FTSR2, ExtiLine);
|
|
}
|
|
#endif /* STM32G0C1xx || STM32G0B1xx */
|
|
|
|
/**
|
|
* @brief Check if falling edge trigger is enabled for Lines in range 0 to 31
|
|
* @rmtoll FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_0
|
|
* @arg @ref LL_EXTI_LINE_1
|
|
* @arg @ref LL_EXTI_LINE_2
|
|
* @arg @ref LL_EXTI_LINE_3
|
|
* @arg @ref LL_EXTI_LINE_4
|
|
* @arg @ref LL_EXTI_LINE_5
|
|
* @arg @ref LL_EXTI_LINE_6
|
|
* @arg @ref LL_EXTI_LINE_7
|
|
* @arg @ref LL_EXTI_LINE_8
|
|
* @arg @ref LL_EXTI_LINE_9
|
|
* @arg @ref LL_EXTI_LINE_10
|
|
* @arg @ref LL_EXTI_LINE_11
|
|
* @arg @ref LL_EXTI_LINE_12
|
|
* @arg @ref LL_EXTI_LINE_13
|
|
* @arg @ref LL_EXTI_LINE_14
|
|
* @arg @ref LL_EXTI_LINE_15
|
|
* @arg @ref LL_EXTI_LINE_16
|
|
* @arg @ref LL_EXTI_LINE_17
|
|
* @arg @ref LL_EXTI_LINE_18
|
|
* @arg @ref LL_EXTI_LINE_20
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
|
|
{
|
|
return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
|
|
}
|
|
|
|
#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
|
|
/**
|
|
* @brief Check if falling edge trigger is enabled for Lines in range 32 to 63
|
|
* @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_34
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine)
|
|
{
|
|
return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
|
|
}
|
|
#endif /* STM32G0C1xx || STM32G0B1xx */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Generate a software Interrupt Event for Lines in range 0 to 31
|
|
* @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
|
|
* this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
|
|
* resulting in an interrupt request generation.
|
|
* This bit is cleared by clearing the corresponding bit in the EXTI_PR
|
|
* register (by writing a 1 into the bit)
|
|
* @rmtoll SWIER1 SWIx LL_EXTI_GenerateSWI_0_31
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_0
|
|
* @arg @ref LL_EXTI_LINE_1
|
|
* @arg @ref LL_EXTI_LINE_2
|
|
* @arg @ref LL_EXTI_LINE_3
|
|
* @arg @ref LL_EXTI_LINE_4
|
|
* @arg @ref LL_EXTI_LINE_5
|
|
* @arg @ref LL_EXTI_LINE_6
|
|
* @arg @ref LL_EXTI_LINE_7
|
|
* @arg @ref LL_EXTI_LINE_8
|
|
* @arg @ref LL_EXTI_LINE_9
|
|
* @arg @ref LL_EXTI_LINE_10
|
|
* @arg @ref LL_EXTI_LINE_11
|
|
* @arg @ref LL_EXTI_LINE_12
|
|
* @arg @ref LL_EXTI_LINE_13
|
|
* @arg @ref LL_EXTI_LINE_14
|
|
* @arg @ref LL_EXTI_LINE_15
|
|
* @arg @ref LL_EXTI_LINE_16
|
|
* @arg @ref LL_EXTI_LINE_17
|
|
* @arg @ref LL_EXTI_LINE_18
|
|
* @arg @ref LL_EXTI_LINE_20
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
|
|
{
|
|
SET_BIT(EXTI->SWIER1, ExtiLine);
|
|
}
|
|
|
|
#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
|
|
/**
|
|
* @brief Generate a software Interrupt Event for Lines in range 32 to 63
|
|
* @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
|
|
* this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
|
|
* resulting in an interrupt request generation.
|
|
* This bit is cleared by clearing the corresponding bit in the EXTI_PR
|
|
* register (by writing a 1 into the bit)
|
|
* @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_34
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine)
|
|
{
|
|
SET_BIT(EXTI->SWIER2, ExtiLine);
|
|
}
|
|
#endif /* STM32G0C1xx || STM32G0B1xx */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Check if the ExtLine Falling Flag is set or not for Lines in range 0 to 31
|
|
* @note This bit is set when the falling edge event arrives on the interrupt
|
|
* line. This bit is cleared by writing a 1 to the bit.
|
|
* @rmtoll FPR1 FPIFx LL_EXTI_IsActiveFallingFlag_0_31
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_0
|
|
* @arg @ref LL_EXTI_LINE_1
|
|
* @arg @ref LL_EXTI_LINE_2
|
|
* @arg @ref LL_EXTI_LINE_3
|
|
* @arg @ref LL_EXTI_LINE_4
|
|
* @arg @ref LL_EXTI_LINE_5
|
|
* @arg @ref LL_EXTI_LINE_6
|
|
* @arg @ref LL_EXTI_LINE_7
|
|
* @arg @ref LL_EXTI_LINE_8
|
|
* @arg @ref LL_EXTI_LINE_9
|
|
* @arg @ref LL_EXTI_LINE_10
|
|
* @arg @ref LL_EXTI_LINE_11
|
|
* @arg @ref LL_EXTI_LINE_12
|
|
* @arg @ref LL_EXTI_LINE_13
|
|
* @arg @ref LL_EXTI_LINE_14
|
|
* @arg @ref LL_EXTI_LINE_15
|
|
* @arg @ref LL_EXTI_LINE_16
|
|
* @arg @ref LL_EXTI_LINE_17
|
|
* @arg @ref LL_EXTI_LINE_18
|
|
* @arg @ref LL_EXTI_LINE_20
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_0_31(uint32_t ExtiLine)
|
|
{
|
|
return ((READ_BIT(EXTI->FPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
|
|
}
|
|
|
|
#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
|
|
/**
|
|
* @brief Check if the ExtLine Falling Flag is set or not for Lines in range 32 to 63
|
|
* @note This bit is set when the falling edge event arrives on the interrupt
|
|
* line. This bit is cleared by writing a 1 to the bit.
|
|
* @rmtoll FPR2 FPIFx LL_EXTI_IsActiveFallingFlag_32_63
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_34
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_32_63(uint32_t ExtiLine)
|
|
{
|
|
return ((READ_BIT(EXTI->FPR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
|
|
}
|
|
#endif /* STM32G0C1xx || STM32G0B1xx */
|
|
|
|
/**
|
|
* @brief Read ExtLine Combination Falling Flag for Lines in range 0 to 31
|
|
* @note This bit is set when the falling edge event arrives on the interrupt
|
|
* line. This bit is cleared by writing a 1 to the bit.
|
|
* @rmtoll FPR1 FPIFx LL_EXTI_ReadFallingFlag_0_31
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_0
|
|
* @arg @ref LL_EXTI_LINE_1
|
|
* @arg @ref LL_EXTI_LINE_2
|
|
* @arg @ref LL_EXTI_LINE_3
|
|
* @arg @ref LL_EXTI_LINE_4
|
|
* @arg @ref LL_EXTI_LINE_5
|
|
* @arg @ref LL_EXTI_LINE_6
|
|
* @arg @ref LL_EXTI_LINE_7
|
|
* @arg @ref LL_EXTI_LINE_8
|
|
* @arg @ref LL_EXTI_LINE_9
|
|
* @arg @ref LL_EXTI_LINE_10
|
|
* @arg @ref LL_EXTI_LINE_11
|
|
* @arg @ref LL_EXTI_LINE_12
|
|
* @arg @ref LL_EXTI_LINE_13
|
|
* @arg @ref LL_EXTI_LINE_14
|
|
* @arg @ref LL_EXTI_LINE_15
|
|
* @arg @ref LL_EXTI_LINE_16
|
|
* @arg @ref LL_EXTI_LINE_17
|
|
* @arg @ref LL_EXTI_LINE_18
|
|
* @arg @ref LL_EXTI_LINE_20
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval @note This bit is set when the selected edge event arrives on the interrupt
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_0_31(uint32_t ExtiLine)
|
|
{
|
|
return (READ_BIT(EXTI->FPR1, ExtiLine));
|
|
}
|
|
|
|
#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
|
|
/**
|
|
* @brief Read ExtLine Combination Falling Flag for Lines in range 32 to 63
|
|
* @note This bit is set when the falling edge event arrives on the interrupt
|
|
* line. This bit is cleared by writing a 1 to the bit.
|
|
* @rmtoll FPR2 FPIFx LL_EXTI_ReadFallingFlag_32_63
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_34
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval @note This bit is set when the selected edge event arrives on the interrupt
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_32_63(uint32_t ExtiLine)
|
|
{
|
|
return (READ_BIT(EXTI->FPR2, ExtiLine));
|
|
}
|
|
#endif /* STM32G0C1xx || STM32G0B1xx */
|
|
|
|
/**
|
|
* @brief Clear ExtLine Falling Flags for Lines in range 0 to 31
|
|
* @note This bit is set when the falling edge event arrives on the interrupt
|
|
* line. This bit is cleared by writing a 1 to the bit.
|
|
* @rmtoll FPR1 FPIFx LL_EXTI_ClearFallingFlag_0_31
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_0
|
|
* @arg @ref LL_EXTI_LINE_1
|
|
* @arg @ref LL_EXTI_LINE_2
|
|
* @arg @ref LL_EXTI_LINE_3
|
|
* @arg @ref LL_EXTI_LINE_4
|
|
* @arg @ref LL_EXTI_LINE_5
|
|
* @arg @ref LL_EXTI_LINE_6
|
|
* @arg @ref LL_EXTI_LINE_7
|
|
* @arg @ref LL_EXTI_LINE_8
|
|
* @arg @ref LL_EXTI_LINE_9
|
|
* @arg @ref LL_EXTI_LINE_10
|
|
* @arg @ref LL_EXTI_LINE_11
|
|
* @arg @ref LL_EXTI_LINE_12
|
|
* @arg @ref LL_EXTI_LINE_13
|
|
* @arg @ref LL_EXTI_LINE_14
|
|
* @arg @ref LL_EXTI_LINE_15
|
|
* @arg @ref LL_EXTI_LINE_16
|
|
* @arg @ref LL_EXTI_LINE_17
|
|
* @arg @ref LL_EXTI_LINE_18
|
|
* @arg @ref LL_EXTI_LINE_20
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_EXTI_ClearFallingFlag_0_31(uint32_t ExtiLine)
|
|
{
|
|
WRITE_REG(EXTI->FPR1, ExtiLine);
|
|
}
|
|
|
|
#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
|
|
/**
|
|
* @brief Clear ExtLine Falling Flags for Lines in range 32 to 63
|
|
* @note This bit is set when the falling edge event arrives on the interrupt
|
|
* line. This bit is cleared by writing a 1 to the bit.
|
|
* @rmtoll FPR2 FPIFx LL_EXTI_ClearFallingFlag_32_63
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_34
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_EXTI_ClearFallingFlag_32_63(uint32_t ExtiLine)
|
|
{
|
|
WRITE_REG(EXTI->FPR2, ExtiLine);
|
|
}
|
|
#endif /* STM32G0C1xx || STM32G0B1xx */
|
|
|
|
/**
|
|
* @brief Check if the ExtLine Rising Flag is set or not for Lines in range 0 to 31
|
|
* @note This bit is set when the Rising edge event arrives on the interrupt
|
|
* line. This bit is cleared by writing a 1 to the bit.
|
|
* @rmtoll RPR1 RPIFx LL_EXTI_IsActiveRisingFlag_0_31
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_0
|
|
* @arg @ref LL_EXTI_LINE_1
|
|
* @arg @ref LL_EXTI_LINE_2
|
|
* @arg @ref LL_EXTI_LINE_3
|
|
* @arg @ref LL_EXTI_LINE_4
|
|
* @arg @ref LL_EXTI_LINE_5
|
|
* @arg @ref LL_EXTI_LINE_6
|
|
* @arg @ref LL_EXTI_LINE_7
|
|
* @arg @ref LL_EXTI_LINE_8
|
|
* @arg @ref LL_EXTI_LINE_9
|
|
* @arg @ref LL_EXTI_LINE_10
|
|
* @arg @ref LL_EXTI_LINE_11
|
|
* @arg @ref LL_EXTI_LINE_12
|
|
* @arg @ref LL_EXTI_LINE_13
|
|
* @arg @ref LL_EXTI_LINE_14
|
|
* @arg @ref LL_EXTI_LINE_15
|
|
* @arg @ref LL_EXTI_LINE_16
|
|
* @arg @ref LL_EXTI_LINE_17
|
|
* @arg @ref LL_EXTI_LINE_18
|
|
* @arg @ref LL_EXTI_LINE_20
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_0_31(uint32_t ExtiLine)
|
|
{
|
|
return ((READ_BIT(EXTI->RPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
|
|
}
|
|
|
|
#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
|
|
/**
|
|
* @brief Check if the ExtLine Rising Flag is set or not for Lines in range 32 to 63
|
|
* @note This bit is set when the Rising edge event arrives on the interrupt
|
|
* line. This bit is cleared by writing a 1 to the bit.
|
|
* @rmtoll RPR2 RPIFx LL_EXTI_IsActiveRisingFlag_32_63
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_34
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_32_63(uint32_t ExtiLine)
|
|
{
|
|
return ((READ_BIT(EXTI->RPR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
|
|
}
|
|
#endif /* STM32G0C1xx || STM32G0B1xx */
|
|
|
|
/**
|
|
* @brief Read ExtLine Combination Rising Flag for Lines in range 0 to 31
|
|
* @note This bit is set when the Rising edge event arrives on the interrupt
|
|
* line. This bit is cleared by writing a 1 to the bit.
|
|
* @rmtoll RPR1 RPIFx LL_EXTI_ReadRisingFlag_0_31
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_0
|
|
* @arg @ref LL_EXTI_LINE_1
|
|
* @arg @ref LL_EXTI_LINE_2
|
|
* @arg @ref LL_EXTI_LINE_3
|
|
* @arg @ref LL_EXTI_LINE_4
|
|
* @arg @ref LL_EXTI_LINE_5
|
|
* @arg @ref LL_EXTI_LINE_6
|
|
* @arg @ref LL_EXTI_LINE_7
|
|
* @arg @ref LL_EXTI_LINE_8
|
|
* @arg @ref LL_EXTI_LINE_9
|
|
* @arg @ref LL_EXTI_LINE_10
|
|
* @arg @ref LL_EXTI_LINE_11
|
|
* @arg @ref LL_EXTI_LINE_12
|
|
* @arg @ref LL_EXTI_LINE_13
|
|
* @arg @ref LL_EXTI_LINE_14
|
|
* @arg @ref LL_EXTI_LINE_15
|
|
* @arg @ref LL_EXTI_LINE_16
|
|
* @arg @ref LL_EXTI_LINE_17
|
|
* @arg @ref LL_EXTI_LINE_18
|
|
* @arg @ref LL_EXTI_LINE_20
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval @note This bit is set when the selected edge event arrives on the interrupt
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_0_31(uint32_t ExtiLine)
|
|
{
|
|
return (READ_BIT(EXTI->RPR1, ExtiLine));
|
|
}
|
|
|
|
#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
|
|
/**
|
|
* @brief Read ExtLine Combination Rising Flag for Lines in range 32 to 63
|
|
* @note This bit is set when the Rising edge event arrives on the interrupt
|
|
* line. This bit is cleared by writing a 1 to the bit.
|
|
* @rmtoll RPR2 RPIFx LL_EXTI_ReadRisingFlag_32_63
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_34
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval @note This bit is set when the selected edge event arrives on the interrupt
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_32_63(uint32_t ExtiLine)
|
|
{
|
|
return (READ_BIT(EXTI->RPR2, ExtiLine));
|
|
}
|
|
#endif /* STM32G0C1xx || STM32G0B1xx */
|
|
|
|
/**
|
|
* @brief Clear ExtLine Rising Flags for Lines in range 0 to 31
|
|
* @note This bit is set when the Rising edge event arrives on the interrupt
|
|
* line. This bit is cleared by writing a 1 to the bit.
|
|
* @rmtoll RPR1 RPIFx LL_EXTI_ClearRisingFlag_0_31
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_0
|
|
* @arg @ref LL_EXTI_LINE_1
|
|
* @arg @ref LL_EXTI_LINE_2
|
|
* @arg @ref LL_EXTI_LINE_3
|
|
* @arg @ref LL_EXTI_LINE_4
|
|
* @arg @ref LL_EXTI_LINE_5
|
|
* @arg @ref LL_EXTI_LINE_6
|
|
* @arg @ref LL_EXTI_LINE_7
|
|
* @arg @ref LL_EXTI_LINE_8
|
|
* @arg @ref LL_EXTI_LINE_9
|
|
* @arg @ref LL_EXTI_LINE_10
|
|
* @arg @ref LL_EXTI_LINE_11
|
|
* @arg @ref LL_EXTI_LINE_12
|
|
* @arg @ref LL_EXTI_LINE_13
|
|
* @arg @ref LL_EXTI_LINE_14
|
|
* @arg @ref LL_EXTI_LINE_15
|
|
* @arg @ref LL_EXTI_LINE_16
|
|
* @arg @ref LL_EXTI_LINE_17
|
|
* @arg @ref LL_EXTI_LINE_18
|
|
* @arg @ref LL_EXTI_LINE_20
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_EXTI_ClearRisingFlag_0_31(uint32_t ExtiLine)
|
|
{
|
|
WRITE_REG(EXTI->RPR1, ExtiLine);
|
|
}
|
|
|
|
#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
|
|
/**
|
|
* @brief Clear ExtLine Rising Flags for Lines in range 32 to 63
|
|
* @note This bit is set when the Rising edge event arrives on the interrupt
|
|
* line. This bit is cleared by writing a 1 to the bit.
|
|
* @rmtoll RPR2 RPIFx LL_EXTI_ClearRisingFlag_32_63
|
|
* @param ExtiLine This parameter can be a combination of the following values:
|
|
* @arg @ref LL_EXTI_LINE_34
|
|
* @note Please check each device line mapping for EXTI Line availability
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_EXTI_ClearRisingFlag_32_63(uint32_t ExtiLine)
|
|
{
|
|
WRITE_REG(EXTI->RPR2, ExtiLine);
|
|
}
|
|
#endif /* STM32G0C1xx || STM32G0B1xx */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
/** @defgroup EXTI_LL_EF_Config EF configuration functions
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Configure source input for the EXTI external interrupt.
|
|
* @rmtoll EXTI_EXTICR1 EXTI0 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR1 EXTI1 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR1 EXTI2 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR1 EXTI3 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR2 EXTI4 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR2 EXTI5 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR2 EXTI6 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR2 EXTI7 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR3 EXTI8 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR3 EXTI9 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR3 EXTI10 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR3 EXTI11 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR4 EXTI12 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR4 EXTI13 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR4 EXTI14 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR4 EXTI15 LL_EXTI_SetEXTISource
|
|
* @param Port This parameter can be one of the following values:
|
|
* @arg @ref EXTI_LL_EC_CONFIG_PORT
|
|
*
|
|
* (*) value not defined in all devices
|
|
* @param Line This parameter can be one of the following values:
|
|
* @arg @ref LL_EXTI_CONFIG_LINE0
|
|
* @arg @ref LL_EXTI_CONFIG_LINE1
|
|
* @arg @ref LL_EXTI_CONFIG_LINE2
|
|
* @arg @ref LL_EXTI_CONFIG_LINE3
|
|
* @arg @ref LL_EXTI_CONFIG_LINE4
|
|
* @arg @ref LL_EXTI_CONFIG_LINE5
|
|
* @arg @ref LL_EXTI_CONFIG_LINE6
|
|
* @arg @ref LL_EXTI_CONFIG_LINE7
|
|
* @arg @ref LL_EXTI_CONFIG_LINE8
|
|
* @arg @ref LL_EXTI_CONFIG_LINE9
|
|
* @arg @ref LL_EXTI_CONFIG_LINE10
|
|
* @arg @ref LL_EXTI_CONFIG_LINE11
|
|
* @arg @ref LL_EXTI_CONFIG_LINE12
|
|
* @arg @ref LL_EXTI_CONFIG_LINE13
|
|
* @arg @ref LL_EXTI_CONFIG_LINE14
|
|
* @arg @ref LL_EXTI_CONFIG_LINE15
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_EXTI_SetEXTISource(uint32_t Port, uint32_t Line)
|
|
{
|
|
MODIFY_REG(EXTI->EXTICR[Line & 0x03u], EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT), Port << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT));
|
|
}
|
|
|
|
/**
|
|
* @brief Get the configured defined for specific EXTI Line
|
|
* @rmtoll EXTI_EXTICR1 EXTI0 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR1 EXTI1 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR1 EXTI2 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR1 EXTI3 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR2 EXTI4 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR2 EXTI5 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR2 EXTI6 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR2 EXTI7 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR3 EXTI8 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR3 EXTI9 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR3 EXTI10 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR3 EXTI11 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR4 EXTI12 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR4 EXTI13 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR4 EXTI14 LL_EXTI_SetEXTISource\n
|
|
* EXTI_EXTICR4 EXTI15 LL_EXTI_SetEXTISource
|
|
* @param Line This parameter can be one of the following values:
|
|
* @arg @ref LL_EXTI_CONFIG_LINE0
|
|
* @arg @ref LL_EXTI_CONFIG_LINE1
|
|
* @arg @ref LL_EXTI_CONFIG_LINE2
|
|
* @arg @ref LL_EXTI_CONFIG_LINE3
|
|
* @arg @ref LL_EXTI_CONFIG_LINE4
|
|
* @arg @ref LL_EXTI_CONFIG_LINE5
|
|
* @arg @ref LL_EXTI_CONFIG_LINE6
|
|
* @arg @ref LL_EXTI_CONFIG_LINE7
|
|
* @arg @ref LL_EXTI_CONFIG_LINE8
|
|
* @arg @ref LL_EXTI_CONFIG_LINE9
|
|
* @arg @ref LL_EXTI_CONFIG_LINE10
|
|
* @arg @ref LL_EXTI_CONFIG_LINE11
|
|
* @arg @ref LL_EXTI_CONFIG_LINE12
|
|
* @arg @ref LL_EXTI_CONFIG_LINE13
|
|
* @arg @ref LL_EXTI_CONFIG_LINE14
|
|
* @arg @ref LL_EXTI_CONFIG_LINE15
|
|
* @retval Returned value can be one of the following values:
|
|
* @arg @ref EXTI_LL_EC_CONFIG_PORT
|
|
*
|
|
* (*) value not defined in all devices
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_EXTI_GetEXTISource(uint32_t Line)
|
|
{
|
|
return (READ_BIT(EXTI->EXTICR[Line & 0x03u], (EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT))) >> (Line >> LL_EXTI_REGISTER_PINPOS_SHFT));
|
|
}
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#if defined(USE_FULL_LL_DRIVER)
|
|
/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
|
|
* @{
|
|
*/
|
|
|
|
uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
|
|
uint32_t LL_EXTI_DeInit(void);
|
|
void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
|
|
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
#endif /* USE_FULL_LL_DRIVER */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* EXTI */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* STM32G0xx_LL_EXTI_H */
|
|
|