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1307 lines
59 KiB
C
1307 lines
59 KiB
C
/**
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******************************************************************************
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* @file stm32g0xx_ll_bus.h
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* @author MCD Application Team
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* @brief Header file of BUS LL module.
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@verbatim
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##### RCC Limitations #####
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==============================================================================
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[..]
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A delay between an RCC peripheral clock enable and the effective peripheral
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enabling should be taken into account in order to manage the peripheral read/write
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from/to registers.
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(+) This delay depends on the peripheral mapping.
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(++) AHB & APB peripherals, 1 dummy read is necessary
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[..]
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Workarounds:
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(#) For AHB & APB peripherals, a dummy read to the peripheral register has been
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inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
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@endverbatim
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2018 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file in
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* the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32G0xx_LL_BUS_H
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#define STM32G0xx_LL_BUS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32g0xx.h"
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/** @addtogroup STM32G0xx_LL_Driver
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* @{
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*/
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#if defined(RCC)
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/** @defgroup BUS_LL BUS
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
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* @{
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*/
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/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
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* @{
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*/
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#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
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#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
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#if defined(DMA2)
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#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
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#endif /* DMA2 */
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#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLASHEN
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#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN
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#if defined(CRC)
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#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
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#endif /* CRC */
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#if defined(AES)
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#define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_AESEN
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#endif /* AES */
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#if defined(RNG)
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#define LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN
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#endif /* RNG */
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/**
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* @}
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*/
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/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
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* @{
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*/
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#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
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#if defined(TIM2)
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#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APBENR1_TIM2EN
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#endif /* TIM2 */
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#if defined(TIM3)
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#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APBENR1_TIM3EN
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#endif /* TIM3 */
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#if defined(TIM4)
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#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APBENR1_TIM4EN
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#endif /* TIM4 */
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#if defined(TIM6)
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#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APBENR1_TIM6EN
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#endif /* TIM6 */
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#if defined(TIM7)
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#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APBENR1_TIM7EN
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#endif /* TIM7 */
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#if defined(LPUART2)
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#define LL_APB1_GRP1_PERIPH_LPUART2 RCC_APBENR1_LPUART2EN
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#endif /* LPUART2 */
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#if defined(USART5)
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#define LL_APB1_GRP1_PERIPH_USART5 RCC_APBENR1_USART5EN
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#endif /* USART5 */
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#if defined(USART6)
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#define LL_APB1_GRP1_PERIPH_USART6 RCC_APBENR1_USART6EN
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#endif /* USART6 */
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#define LL_APB1_GRP1_PERIPH_RTC RCC_APBENR1_RTCAPBEN
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#define LL_APB1_GRP1_PERIPH_WWDG RCC_APBENR1_WWDGEN
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#if defined(FDCAN1) || defined(FDCAN2)
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#define LL_APB1_GRP1_PERIPH_FDCAN RCC_APBENR1_FDCANEN
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#endif /* FDCAN1 */
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#if defined(USB_DRD_FS)
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#define LL_APB1_GRP1_PERIPH_USB RCC_APBENR1_USBEN
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#endif /* USB_DRD_FS */
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#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APBENR1_SPI2EN
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#if defined(SPI3)
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#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APBENR1_SPI3EN
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#endif /* SPI3 */
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#if defined(CRS)
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#define LL_APB1_GRP1_PERIPH_CRS RCC_APBENR1_CRSEN
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#endif /* CRS */
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#define LL_APB1_GRP1_PERIPH_USART2 RCC_APBENR1_USART2EN
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#if defined(USART3)
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#define LL_APB1_GRP1_PERIPH_USART3 RCC_APBENR1_USART3EN
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#endif /* USART3 */
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#if defined(USART4)
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#define LL_APB1_GRP1_PERIPH_USART4 RCC_APBENR1_USART4EN
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#endif /* USART4 */
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#if defined(LPUART1)
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#define LL_APB1_GRP1_PERIPH_LPUART1 RCC_APBENR1_LPUART1EN
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#endif /* LPUART1 */
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#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APBENR1_I2C1EN
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#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APBENR1_I2C2EN
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#if defined(I2C3)
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#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APBENR1_I2C3EN
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#endif /* I2C3 */
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#if defined(CEC)
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#define LL_APB1_GRP1_PERIPH_CEC RCC_APBENR1_CECEN
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#endif /* CEC */
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#if defined(UCPD1)
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#define LL_APB1_GRP1_PERIPH_UCPD1 RCC_APBENR1_UCPD1EN
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#endif /* UCPD1 */
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#if defined(UCPD2)
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#define LL_APB1_GRP1_PERIPH_UCPD2 RCC_APBENR1_UCPD2EN
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#endif /* UCPD2 */
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#define LL_APB1_GRP1_PERIPH_DBGMCU RCC_APBENR1_DBGEN
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#define LL_APB1_GRP1_PERIPH_PWR RCC_APBENR1_PWREN
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#if defined(DAC1)
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#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APBENR1_DAC1EN
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#endif /* DAC1 */
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#if defined(LPTIM2)
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#define LL_APB1_GRP1_PERIPH_LPTIM2 RCC_APBENR1_LPTIM2EN
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#endif /* LPTIM2 */
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#if defined(LPTIM1)
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#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APBENR1_LPTIM1EN
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#endif /* LPTIM1 */
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/**
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* @}
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*/
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/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
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* @{
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*/
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#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
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#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APBENR2_SYSCFGEN
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#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APBENR2_TIM1EN
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#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APBENR2_SPI1EN
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#define LL_APB2_GRP1_PERIPH_USART1 RCC_APBENR2_USART1EN
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#if defined(TIM14)
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#define LL_APB2_GRP1_PERIPH_TIM14 RCC_APBENR2_TIM14EN
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#endif /* TIM14 */
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#if defined(TIM15)
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#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APBENR2_TIM15EN
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#endif /* TIM15 */
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#if defined(TIM16)
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#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APBENR2_TIM16EN
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#endif /* TIM16 */
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#if defined(TIM17)
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#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APBENR2_TIM17EN
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#endif /* TIM17 */
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#if defined(ADC)
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#define LL_APB2_GRP1_PERIPH_ADC RCC_APBENR2_ADCEN
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#endif /* ADC */
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/**
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* @}
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*/
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/** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH
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* @{
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*/
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#define LL_IOP_GRP1_PERIPH_ALL 0xFFFFFFFFU
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#define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN
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#define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN
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#define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN
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#define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN
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#if defined(GPIOE)
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#define LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN
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#endif /* GPIOE */
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#if defined(GPIOF)
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#define LL_IOP_GRP1_PERIPH_GPIOF RCC_IOPENR_GPIOFEN
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#endif /* GPIOF */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
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* @{
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*/
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/** @defgroup BUS_LL_EF_AHB1 AHB1
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* @{
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*/
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/**
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* @brief Enable AHB1 peripherals clock.
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* @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
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* AHBENR FLASHEN LL_AHB1_GRP1_EnableClock\n
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* AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
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* AHBENR AESEN LL_AHB1_GRP1_EnableClock\n
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* AHBENR RNGEN LL_AHB1_GRP1_EnableClock
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
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* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
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* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
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* @note (*) RNG & CRYP Peripherals available only on STM32G081xx
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* @retval None
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*/
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__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
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{
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__IO uint32_t tmpreg;
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SET_BIT(RCC->AHBENR, Periphs);
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/* Delay after an RCC peripheral clock enabling */
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tmpreg = READ_BIT(RCC->AHBENR, Periphs);
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(void)tmpreg;
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}
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/**
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* @brief Check if AHB1 peripheral clock is enabled or not
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* @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
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* AHBENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
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* AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
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* AHBENR AESEN LL_AHB1_GRP1_IsEnabledClock\n
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* AHBENR RNGEN LL_AHB1_GRP1_IsEnabledClock
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
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* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
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* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
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* @note (*) RNG & CRYP Peripherals available only on STM32G081xx
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* @retval State of Periphs (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
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{
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return ((READ_BIT(RCC->AHBENR, Periphs) == Periphs) ? 1UL : 0UL);
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}
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/**
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* @brief Disable AHB1 peripherals clock.
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* @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
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* AHBENR FLASHEN LL_AHB1_GRP1_DisableClock\n
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* AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
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* AHBENR AESEN LL_AHB1_GRP1_DisableClock\n
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* AHBENR RNGEN LL_AHB1_GRP1_DisableClock
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
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* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
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* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
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* @note (*) RNG & CRYP Peripherals available only on STM32G081xx
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* @retval None
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*/
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__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
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{
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CLEAR_BIT(RCC->AHBENR, Periphs);
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}
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/**
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* @brief Force AHB1 peripherals reset.
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* @rmtoll AHBRSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
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* AHBRSTR FLASHRST LL_AHB1_GRP1_ForceReset\n
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* AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n
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* AHBRSTR AESRST LL_AHB1_GRP1_ForceReset\n
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* AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
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* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
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* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
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* @note (*) RNG & CRYP Peripherals available only on STM32G081xx
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* @retval None
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*/
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__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
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{
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SET_BIT(RCC->AHBRSTR, Periphs);
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}
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/**
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* @brief Release AHB1 peripherals reset.
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* @rmtoll AHBRSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
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* AHBRSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n
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* AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
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* AHBRSTR AESRST LL_AHB1_GRP1_ReleaseReset\n
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* AHBRSTR RNGRST LL_AHB1_GRP1_ReleaseReset
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
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* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
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* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
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* @note (*) RNG & CRYP Peripherals available only on STM32G081xx
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* @retval None
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*/
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__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
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{
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CLEAR_BIT(RCC->AHBRSTR, Periphs);
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}
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/**
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* @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
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* @rmtoll AHBSMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
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* AHBSMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
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* AHBSMENR SRAMSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
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* AHBSMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
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* AHBSMENR AESSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
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* AHBSMENR RNGSMEN LL_AHB1_GRP1_EnableClockStopSleep
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
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* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
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* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
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* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
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* @note (*) RNG & CRYP Peripherals available only on STM32G081xx
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* @retval None
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*/
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__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
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{
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__IO uint32_t tmpreg;
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SET_BIT(RCC->AHBSMENR, Periphs);
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/* Delay after an RCC peripheral clock enabling */
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tmpreg = READ_BIT(RCC->AHBSMENR, Periphs);
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(void)tmpreg;
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}
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/**
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* @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
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* @rmtoll AHBSMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
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* AHBSMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
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* AHBSMENR SRAMSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
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* AHBSMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
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* AHBSMENR AESSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
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* AHBSMENR RNGSMEN LL_AHB1_GRP1_DisableClockStopSleep
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
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* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
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* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
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* @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
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* @note (*) RNG & CRYP Peripherals available only on STM32G081xx
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* @retval None
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*/
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__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
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{
|
|
CLEAR_BIT(RCC->AHBSMENR, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup BUS_LL_EF_APB1 APB1
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enable APB1 peripherals clock.
|
|
* @rmtoll APBENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 TIM4EN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 TIM6EN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 TIM7EN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 SPI3EN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 USART2EN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 USART3EN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 USART4EN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 USART5EN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 USART6EN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 LPUART1EN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 LPUART2EN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 I2C2EN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 I2C3EN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 CECEN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 UCPD1EN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 UCPD2EN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 USBEN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 FDCANEN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 DBGEN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 PWREN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 DAC1EN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 LPTIM2EN LL_APB1_GRP1_EnableClock\n
|
|
* APBENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_RTC
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART6 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_CEC (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_UCPD1 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_UCPD2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USB (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (1)
|
|
* @note Peripheral marked with (1) are not available all devices
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
|
|
{
|
|
__IO uint32_t tmpreg;
|
|
SET_BIT(RCC->APBENR1, Periphs);
|
|
/* Delay after an RCC peripheral clock enabling */
|
|
tmpreg = READ_BIT(RCC->APBENR1, Periphs);
|
|
(void)tmpreg;
|
|
}
|
|
|
|
/**
|
|
* @brief Check if APB1 peripheral clock is enabled or not
|
|
* @rmtoll APBENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 USART4EN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 USART5EN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 USART6EN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 LPUART1EN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 LPUART2EN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 CECEN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 UCPD1EN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 UCPD2EN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 USBEN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 FDCANEN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 DBGEN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 LPTIM2EN LL_APB1_GRP1_IsEnabledClock\n
|
|
* APBENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_RTC
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART6 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_CEC (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_UCPD1 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_UCPD2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USB (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (1)
|
|
* @note Peripheral marked with (1) are not available all devices
|
|
* @retval State of Periphs (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
|
|
{
|
|
return ((READ_BIT(RCC->APBENR1, Periphs) == (Periphs)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable APB1 peripherals clock.
|
|
* @rmtoll APBENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 TIM4EN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 TIM6EN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 TIM7EN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 SPI3EN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 USART2EN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 USART3EN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 USART4EN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 USART5EN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 USART6EN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 LPUART1EN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 LPUART2EN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 I2C2EN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 I2C3EN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 CECEN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 UCPD1EN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 UCPD2EN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 USBEN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 FDCANEN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 DBGEN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 PWREN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 DAC1EN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 LPTIM2EN LL_APB1_GRP1_DisableClock\n
|
|
* APBENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_RTC
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART6 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_CEC (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_UCPD1 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_UCPD2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USB (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (1)
|
|
* @note Peripheral marked with (1) are not available all devices
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
|
|
{
|
|
CLEAR_BIT(RCC->APBENR1, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @brief Force APB1 peripherals reset.
|
|
* @rmtoll APBRSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 RTCRST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 USART3RST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 USART4RST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 USART5RST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 USART6RST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 LPUART1RST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 LPUART2RST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 CECRST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 UCPD1RST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 UCPD2RST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 USBRST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 FDCANRST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 DBGRST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 PWRRST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 DAC1RST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 LPTIM2RST LL_APB1_GRP1_ForceReset\n
|
|
* APBRSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_RTC
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART6 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_CEC (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_UCPD1 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_UCPD2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USB (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (1)
|
|
* @note Peripheral marked with (1) are not available all devices
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
|
|
{
|
|
SET_BIT(RCC->APBRSTR1, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @brief Release APB1 peripherals reset.
|
|
* @rmtoll APBRSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 RTCRST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 USART4RST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 USART5RST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 USART6RST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 LPUART1RST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 LPUART2RST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 CECRST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 UCPD1RST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 UCPD2RST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 USBRST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 FDCANRST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 DBGRST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 DAC1RST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 LPTIM2RST LL_APB1_GRP1_ReleaseReset\n
|
|
* APBRSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_RTC
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART6 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_CEC (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_UCPD1 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_UCPD2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USB (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (1)
|
|
* @note Peripheral marked with (1) are not available all devices
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
|
|
{
|
|
CLEAR_BIT(RCC->APBRSTR1, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @brief Enable APB1 peripheral clocks in Sleep and Stop modes
|
|
* @rmtoll APBSMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 USART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 USART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 USART6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 LPUART1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 LPUART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 CECSMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 UCPD1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 UCPD2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 USBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 FDCANSMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 DBGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 LPTIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_RTC
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART6 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_CEC (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_UCPD1 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_UCPD2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USB (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (1)
|
|
* @note Peripheral marked with (1) are not available all devices
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
|
|
{
|
|
__IO uint32_t tmpreg;
|
|
SET_BIT(RCC->APBSMENR1, Periphs);
|
|
/* Delay after an RCC peripheral clock enabling */
|
|
tmpreg = READ_BIT(RCC->APBSMENR1, Periphs);
|
|
(void)tmpreg;
|
|
}
|
|
|
|
/**
|
|
* @brief Disable APB1 peripheral clocks in Sleep and Stop modes
|
|
* @rmtoll APBSMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 TIM'SMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 USART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 USART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 USART6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 LPUART1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 LPUART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 CECSMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 UCPD1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 UCPD2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 USBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 FSCANSMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 DBGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 LPTIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_RTC
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART4 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART5 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USART6 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPUART2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_CEC (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_UCPD1 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_UCPD2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_USB (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM2 (1)
|
|
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (1)
|
|
* @note Peripheral marked with (1) are not available all devices
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
|
|
{
|
|
CLEAR_BIT(RCC->APBSMENR1, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup BUS_LL_EF_APB2 APB2
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enable APB2 peripherals clock.
|
|
* @rmtoll APBENR2 SYSCFGEN LL_APB2_GRP1_EnableClock\n
|
|
* APBENR2 TIM1EN LL_APB2_GRP1_EnableClock\n
|
|
* APBENR2 SPI1EN LL_APB2_GRP1_EnableClock\n
|
|
* APBENR2 USART1EN LL_APB2_GRP1_EnableClock\n
|
|
* APBENR2 TIM14EN LL_APB2_GRP1_EnableClock\n
|
|
* APBENR2 TIM15EN LL_APB2_GRP1_EnableClock\n
|
|
* APBENR2 TIM16EN LL_APB2_GRP1_EnableClock\n
|
|
* APBENR2 TIM17EN LL_APB2_GRP1_EnableClock\n
|
|
* APBENR2 ADCEN LL_APB2_GRP1_EnableClock
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM14
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ADC
|
|
* @note (*) peripheral not available on all devices
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
|
|
{
|
|
__IO uint32_t tmpreg;
|
|
SET_BIT(RCC->APBENR2, Periphs);
|
|
/* Delay after an RCC peripheral clock enabling */
|
|
tmpreg = READ_BIT(RCC->APBENR2, Periphs);
|
|
(void)tmpreg;
|
|
}
|
|
|
|
/**
|
|
* @brief Check if APB2 peripheral clock is enabled or not
|
|
* @rmtoll APBENR2 SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
|
|
* APBENR2 TIM1EN LL_APB2_GRP1_IsEnabledClock\n
|
|
* APBENR2 SPI1EN LL_APB2_GRP1_IsEnabledClock\n
|
|
* APBENR2 USART1EN LL_APB2_GRP1_IsEnabledClock\n
|
|
* APBENR2 TIM14EN LL_APB2_GRP1_IsEnabledClock\n
|
|
* APBENR2 TIM15EN LL_APB2_GRP1_IsEnabledClock\n
|
|
* APBENR2 TIM16EN LL_APB2_GRP1_IsEnabledClock\n
|
|
* APBENR2 TIM17EN LL_APB2_GRP1_IsEnabledClock\n
|
|
* APBENR2 ADCEN LL_APB2_GRP1_IsEnabledClock
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM14
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ADC
|
|
* @note (*) peripheral not available on all devices
|
|
* @retval State of Periphs (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
|
|
{
|
|
return ((READ_BIT(RCC->APBENR2, Periphs) == (Periphs)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable APB2 peripherals clock.
|
|
* @rmtoll APBENR2 SYSCFGEN LL_APB2_GRP1_DisableClock\n
|
|
* APBENR2 TIM1EN LL_APB2_GRP1_DisableClock\n
|
|
* APBENR2 SPI1EN LL_APB2_GRP1_DisableClock\n
|
|
* APBENR2 USART1EN LL_APB2_GRP1_DisableClock\n
|
|
* APBENR2 TIM14EN LL_APB2_GRP1_DisableClock\n
|
|
* APBENR2 TIM15EN LL_APB2_GRP1_DisableClock\n
|
|
* APBENR2 TIM16EN LL_APB2_GRP1_DisableClock\n
|
|
* APBENR2 TIM17EN LL_APB2_GRP1_DisableClock\n
|
|
* APBENR2 ADCEN LL_APB2_GRP1_DisableClock
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM14
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ADC
|
|
* @note (*) peripheral not available on all devices
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
|
|
{
|
|
CLEAR_BIT(RCC->APBENR2, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @brief Force APB2 peripherals reset.
|
|
* @rmtoll APBRSTR2 SYSCFGRST LL_APB2_GRP1_ForceReset\n
|
|
* APBRSTR2 TIM1RST LL_APB2_GRP1_ForceReset\n
|
|
* APBRSTR2 SPI1RST LL_APB2_GRP1_ForceReset\n
|
|
* APBRSTR2 USART1RST LL_APB2_GRP1_ForceReset\n
|
|
* APBRSTR2 TIM14RST LL_APB2_GRP1_ForceReset\n
|
|
* APBRSTR2 TIM15RST LL_APB2_GRP1_ForceReset\n
|
|
* APBRSTR2 TIM16RST LL_APB2_GRP1_ForceReset\n
|
|
* APBRSTR2 TIM17RST LL_APB2_GRP1_ForceReset\n
|
|
* APBRSTR2 ADCRST LL_APB2_GRP1_ForceReset
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ALL
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM14
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ADC
|
|
* @note (*) peripheral not available on all devices
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
|
|
{
|
|
SET_BIT(RCC->APBRSTR2, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @brief Release APB2 peripherals reset.
|
|
* @rmtoll APBRSTR2 SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
|
|
* APBRSTR2 TIM1RST LL_APB2_GRP1_ReleaseReset\n
|
|
* APBRSTR2 SPI1RST LL_APB2_GRP1_ReleaseReset\n
|
|
* APBRSTR2 USART1RST LL_APB2_GRP1_ReleaseReset\n
|
|
* APBRSTR2 TIM14RST LL_APB2_GRP1_ReleaseReset\n
|
|
* APBRSTR2 TIM15RST LL_APB2_GRP1_ReleaseReset\n
|
|
* APBRSTR2 TIM16RST LL_APB2_GRP1_ReleaseReset\n
|
|
* APBRSTR2 TIM17RST LL_APB2_GRP1_ReleaseReset\n
|
|
* APBRSTR2 ADCRST LL_APB2_GRP1_ReleaseReset
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ALL
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM14
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ADC
|
|
* @note (*) peripheral not available on all devices
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
|
|
{
|
|
CLEAR_BIT(RCC->APBRSTR2, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @brief Enable APB2 peripheral clocks in Sleep and Stop modes
|
|
* @rmtoll APBSMENR2 SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR2 TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR2 SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR2 USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR2 TIM14SMEN LL_APB2_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR2 TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR2 TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR2 TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n
|
|
* APBSMENR2 ADCSMEN LL_APB2_GRP1_EnableClockStopSleep
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM14
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ADC
|
|
* @note (*) peripheral not available on all devices
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
|
|
{
|
|
__IO uint32_t tmpreg;
|
|
SET_BIT(RCC->APBSMENR2, Periphs);
|
|
/* Delay after an RCC peripheral clock enabling */
|
|
tmpreg = READ_BIT(RCC->APBSMENR2, Periphs);
|
|
(void)tmpreg;
|
|
}
|
|
|
|
/**
|
|
* @brief Disable APB2 peripheral clocks in Sleep and Stop modes
|
|
* @rmtoll APBSMENR2 SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR2 TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR2 SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR2 USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR2 TIM14SMEN LL_APB2_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR2 TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR2 TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR2 TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n
|
|
* APBSMENR2 ADCSMEN LL_APB2_GRP1_DisableClockStopSleep
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM14
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
|
|
* @arg @ref LL_APB2_GRP1_PERIPH_ADC
|
|
* @note (*) peripheral not available on all devices
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
|
|
{
|
|
CLEAR_BIT(RCC->APBSMENR2, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup BUS_LL_EF_IOP IOP
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enable IOP peripherals clock.
|
|
* @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_EnableClock\n
|
|
* IOPENR GPIOBEN LL_IOP_GRP1_EnableClock\n
|
|
* IOPENR GPIOCEN LL_IOP_GRP1_EnableClock\n
|
|
* IOPENR GPIODEN LL_IOP_GRP1_EnableClock\n
|
|
* IOPENR GPIOEEN LL_IOP_GRP1_EnableClock\n
|
|
* IOPENR GPIOFEN LL_IOP_GRP1_EnableClock
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_IOP_GRP1_EnableClock(uint32_t Periphs)
|
|
{
|
|
__IO uint32_t tmpreg;
|
|
SET_BIT(RCC->IOPENR, Periphs);
|
|
/* Delay after an RCC peripheral clock enabling */
|
|
tmpreg = READ_BIT(RCC->IOPENR, Periphs);
|
|
(void)tmpreg;
|
|
}
|
|
|
|
/**
|
|
* @brief Check if IOP peripheral clock is enabled or not
|
|
* @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_IsEnabledClock\n
|
|
* IOPENR GPIOBEN LL_IOP_GRP1_IsEnabledClock\n
|
|
* IOPENR GPIOCEN LL_IOP_GRP1_IsEnabledClock\n
|
|
* IOPENR GPIODEN LL_IOP_GRP1_IsEnabledClock\n
|
|
* IOPENR GPIOEEN LL_IOP_GRP1_IsEnabledClock\n
|
|
* IOPENR GPIOFEN LL_IOP_GRP1_IsEnabledClock
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
|
|
* @retval State of Periphs (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs)
|
|
{
|
|
return ((READ_BIT(RCC->IOPENR, Periphs) == Periphs) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable IOP peripherals clock.
|
|
* @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_DisableClock\n
|
|
* IOPENR GPIOBEN LL_IOP_GRP1_DisableClock\n
|
|
* IOPENR GPIOCEN LL_IOP_GRP1_DisableClock\n
|
|
* IOPENR GPIODEN LL_IOP_GRP1_DisableClock\n
|
|
* IOPENR GPIOEEN LL_IOP_GRP1_DisableClock\n
|
|
* IOPENR GPIOFEN LL_IOP_GRP1_DisableClock
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_IOP_GRP1_DisableClock(uint32_t Periphs)
|
|
{
|
|
CLEAR_BIT(RCC->IOPENR, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable IOP peripherals clock.
|
|
* @rmtoll IOPRSTR GPIOARST LL_IOP_GRP1_ForceReset\n
|
|
* IOPRSTR GPIOBRST LL_IOP_GRP1_ForceReset\n
|
|
* IOPRSTR GPIOCRST LL_IOP_GRP1_ForceReset\n
|
|
* IOPRSTR GPIODRST LL_IOP_GRP1_ForceReset\n
|
|
* IOPRSTR GPIOERST LL_IOP_GRP1_ForceReset\n
|
|
* IOPRSTR GPIOFRST LL_IOP_GRP1_ForceReset
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_ALL
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_IOP_GRP1_ForceReset(uint32_t Periphs)
|
|
{
|
|
SET_BIT(RCC->IOPRSTR, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @brief Release IOP peripherals reset.
|
|
* @rmtoll IOPRSTR GPIOARST LL_IOP_GRP1_ReleaseReset\n
|
|
* IOPRSTR GPIOBRST LL_IOP_GRP1_ReleaseReset\n
|
|
* IOPRSTR GPIOCRST LL_IOP_GRP1_ReleaseReset\n
|
|
* IOPRSTR GPIODRST LL_IOP_GRP1_ReleaseReset\n
|
|
* IOPRSTR GPIOERST LL_IOP_GRP1_ReleaseReset\n
|
|
* IOPRSTR GPIOFRST LL_IOP_GRP1_ReleaseReset
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_ALL
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_IOP_GRP1_ReleaseReset(uint32_t Periphs)
|
|
{
|
|
CLEAR_BIT(RCC->IOPRSTR, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @brief Enable IOP peripheral clocks in Sleep and Stop modes
|
|
* @rmtoll IOPSMENR GPIOASMEN LL_IOP_GRP1_EnableClockStopSleep\n
|
|
* IOPSMENR GPIOBSMEN LL_IOP_GRP1_EnableClockStopSleep\n
|
|
* IOPSMENR GPIOCSMEN LL_IOP_GRP1_EnableClockStopSleep\n
|
|
* IOPSMENR GPIODSMEN LL_IOP_GRP1_EnableClockStopSleep\n
|
|
* IOPSMENR GPIOESMEN LL_IOP_GRP1_EnableClockStopSleep\n
|
|
* IOPSMENR GPIOFSMEN LL_IOP_GRP1_EnableClockStopSleep
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_IOP_GRP1_EnableClockStopSleep(uint32_t Periphs)
|
|
{
|
|
__IO uint32_t tmpreg;
|
|
SET_BIT(RCC->IOPSMENR, Periphs);
|
|
/* Delay after an RCC peripheral clock enabling */
|
|
tmpreg = READ_BIT(RCC->IOPSMENR, Periphs);
|
|
(void)tmpreg;
|
|
}
|
|
|
|
/**
|
|
* @brief Disable IOP peripheral clocks in Sleep and Stop modes
|
|
* @rmtoll IOPSMENR GPIOASMEN LL_IOP_GRP1_DisableClockStopSleep\n
|
|
* IOPSMENR GPIOBSMEN LL_IOP_GRP1_DisableClockStopSleep\n
|
|
* IOPSMENR GPIOCSMEN LL_IOP_GRP1_DisableClockStopSleep\n
|
|
* IOPSMENR GPIODSMEN LL_IOP_GRP1_DisableClockStopSleep\n
|
|
* IOPSMENR GPIOESMEN LL_IOP_GRP1_DisableClockStopSleep\n
|
|
* IOPSMENR GPIOFSMEN LL_IOP_GRP1_DisableClockStopSleep
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOC
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOD
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOE
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_IOP_GRP1_DisableClockStopSleep(uint32_t Periphs)
|
|
{
|
|
CLEAR_BIT(RCC->IOPSMENR, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* RCC */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* STM32G0xx_LL_BUS_H */
|
|
|