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Code cleanup, replaced redundant files by symlinks

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This commit is contained in:
Kai-Bjoern Gemlau
2022-04-06 16:11:32 +02:00
parent 3338b657cf
commit 52bd90f963
72 changed files with 87 additions and 11104 deletions
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3
src/APP/Aufgabe1/ps7/core0/build/config.mk
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@@ -7,5 +7,4 @@ OPTIMIZE=-O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-section
DEBUG =-g3
#Linker flags
LDFLAGS = -nostartfiles -Xlinker --gc-sections
LDFLAGS = -nostartfiles -Xlinker --gc-sections -lm

23
src/APP/Aufgabe1/ps7/core0/build/includes.mk
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@@ -19,6 +19,7 @@ INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_l2cachec/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_uartps/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_emacps/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_scuc/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_ttcps/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/cortexa9/gcc"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/common"
@@ -26,3 +27,25 @@ INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/common"
INC += -I"$(SRC_DIR)/Xilinx/libsrc/ipipsu_v2_3/src/"
INC += -I"$(SRC_DIR)/Modules/MMU"
INC += -I"$(SRC_DIR)/Xilinx/libsrc/ipipsu_v2_3/src/"
#scugic.h fix
INC += -I"$(SRC_DIR)/Xilinx/libsrc/scugic_v3_9/src/"
#uart includes
INC += -I"$(SRC_DIR)/Xilinx/libsrc/uartps_v3_6/src/"
#xttcps includes
INC += -I"$(SRC_DIR)/Xilinx/libsrc/ttcps_v3_5/src/"
#gpio includes
INC += -I"$(SRC_DIR)/Xilinx/libsrc/gpiops_v3_3/src/"
#I2C includes
INC += -I"$(SRC_DIR)/Xilinx/libsrc/iicps_v3_6/src/"
#task set includes
INC += -I"$(SRC_DIR)/Modules/genericTaskset/if"

2
src/APP/Aufgabe1/ps7/core0/build/sources.mk
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@@ -14,7 +14,7 @@ SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/main.c
SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/app_hooks.c
SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/uartps_cfg.c
SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Ports/ARM-Cortex-A/Generic/GNU/os_cpu_a_vfp-none.S
SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Ports/ARM-Cortex-A/Generic/GNU/os_cpu_a_vfp-d32.S
SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Ports/ARM-Cortex-A/Generic/GNU/os_cpu_c.c
SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/Cache/ARM/armv7_generic_l1/GNU/cpu_cache_armv7_generic_l1_a.S

4
src/APP/Aufgabe1/ps7/core0/cfg/xparameters.h
View File

@@ -439,10 +439,10 @@
#define XPAR_UCOS_UARTPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_UART_1 */
#define XPAR_PS7_UART_1_DEVICE_ID 0
#define XPAR_PS7_UART_1_DEVICE_ID 2
#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 50000000
#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 9600
#define XPAR_PS7_UART_1_HAS_MODEM 0

1
src/APP/Aufgabe2/ps7/core0/build/config.mk
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@@ -1,6 +1,5 @@
#µController dependent flags
MCFLAGS =-mcpu=cortex-a9 -march=armv7-a -mthumb -mthumb-interwork -mfloat-abi=softfp -mfpu=neon
#Optimization
OPTIMIZE=-O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections

29
src/APP/Aufgabe2/ps7/core0/build/includes.mk
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@@ -1,29 +0,0 @@
INC += -I"$(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/cfg/"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Ports/ARM-Cortex-A/Generic/GNU/"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/ARM-Cortex-A/GNU/"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-Common"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Source"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-LIB"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/bsp/src/ipi"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/bsp/src/"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/bsp/src/$(ARCH)/"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_cpu_cortexa9/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_scugic/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_l2cachec/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_uartps/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_emacps/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_scuc/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/cortexa9"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/cortexa9/gcc"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/common"
INC += -I"$(SRC_DIR)/Xilinx/libsrc/ipipsu_v2_3/src/"
INC += -I"$(SRC_DIR)/Modules/MMU"

1
src/APP/Aufgabe2/ps7/core0/build/includes.mk Symbolic link
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@@ -0,0 +1 @@
../../../../Aufgabe1/ps7/core0/build/includes.mk

5
src/APP/Aufgabe2/ps7/core0/build/sources.mk
View File

@@ -8,7 +8,7 @@ SRC += $(SRC_DIR)/ucos_v1_42/ucos/bsp/src/$(ARCH)/asm_vectors.S
SRC += $(SRC_DIR)/ucos_v1_42/ucos/components/ucos_osii/src/bsp/$(ARCH)/ucos_osii_bsp.c
SRC += $(SRC_DIR)/ucos_v1_42/ucos/components/ucos_common/src/$(ARCH)/cpu_bsp.c
SRC += $(SRC_DIR)/Modules/MMU/mmu.c
SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/main.c
SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/app_hooks.c
@@ -36,6 +36,3 @@ SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-Common/Collections/slist.c
SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-Common/Auth/auth.c
-include $(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Source/subdir.mk
#mmu
SRC += $(SRC_DIR)/Modules/MMU/mmu.c

216
src/APP/Aufgabe2/ps7/core0/cfg/cpu_cfg.h
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@@ -1,216 +0,0 @@
/*
*********************************************************************************************************
* uC/CPU
* CPU CONFIGURATION & PORT LAYER
*
* (c) Copyright 2004-2015; Micrium, Inc.; Weston, FL
*
* All rights reserved. Protected by international copyright laws.
*
* uC/CPU is provided in source form to registered licensees ONLY. It is
* illegal to distribute this source code to any third party unless you receive
* written permission by an authorized Micrium representative. Knowledge of
* the source code may NOT be used to develop a similar product.
*
* Please help us continue to provide the Embedded community with the finest
* software available. Your honesty is greatly appreciated.
*
* You can find our product's user manual, API reference, release notes and
* more information at https://doc.micrium.com.
* You can contact us at www.micrium.com.
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* CPU CONFIGURATION FILE
*
* TEMPLATE
*
* Filename : cpu_cfg.h
* Version : V1.30.02
* Programmer(s) : SR
* ITJ
* JBL
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* MODULE
*********************************************************************************************************
*/
#ifndef CPU_CFG_MODULE_PRESENT
#define CPU_CFG_MODULE_PRESENT
/*
*********************************************************************************************************
* CPU NAME CONFIGURATION
*
* Note(s) : (1) Configure CPU_CFG_NAME_EN to enable/disable CPU host name feature :
*
* (a) CPU host name storage
* (b) CPU host name API functions
*
* (2) Configure CPU_CFG_NAME_SIZE with the desired ASCII string size of the CPU host name,
* including the terminating NULL character.
*
* See also 'cpu_core.h GLOBAL VARIABLES Note #1'.
*********************************************************************************************************
*/
/* Configure CPU host name feature (see Note #1) : */
#define CPU_CFG_NAME_EN DEF_DISABLED
/* DEF_DISABLED CPU host name DISABLED */
/* DEF_ENABLED CPU host name ENABLED */
/* Configure CPU host name ASCII string size ... */
#define CPU_CFG_NAME_SIZE 16
/*
*********************************************************************************************************
* CPU TIMESTAMP CONFIGURATION
*
* Note(s) : (1) Configure CPU_CFG_TS_xx_EN to enable/disable CPU timestamp features :
*
* (a) CPU_CFG_TS_32_EN enable/disable 32-bit CPU timestamp feature
* (b) CPU_CFG_TS_64_EN enable/disable 64-bit CPU timestamp feature
*
* (2) (a) Configure CPU_CFG_TS_TMR_SIZE with the CPU timestamp timer's word size :
*
* CPU_WORD_SIZE_08 8-bit word size
* CPU_WORD_SIZE_16 16-bit word size
* CPU_WORD_SIZE_32 32-bit word size
* CPU_WORD_SIZE_64 64-bit word size
*
* (b) If the size of the CPU timestamp timer is not a binary multiple of 8-bit octets
* (e.g. 20-bits or even 24-bits), then the next lower, binary-multiple octet word
* size SHOULD be configured (e.g. to 16-bits). However, the minimum supported word
* size for CPU timestamp timers is 8-bits.
*
* See also 'cpu_core.h FUNCTION PROTOTYPES CPU_TS_TmrRd() Note #2a'.
*********************************************************************************************************
*/
/* Configure CPU timestamp features (see Note #1) : */
#define CPU_CFG_TS_32_EN DEF_ENABLED
#define CPU_CFG_TS_64_EN DEF_ENABLED
/* DEF_DISABLED CPU timestamps DISABLED */
/* DEF_ENABLED CPU timestamps ENABLED */
/* Configure CPU timestamp timer word size ... */
/* ... (see Note #2) : */
#define CPU_CFG_TS_TMR_SIZE CPU_WORD_SIZE_64
/*
*********************************************************************************************************
* CPU INTERRUPTS DISABLED TIME MEASUREMENT CONFIGURATION
*
* Note(s) : (1) (a) Configure CPU_CFG_INT_DIS_MEAS_EN to enable/disable measuring CPU's interrupts
* disabled time :
*
* (a) Enabled, if CPU_CFG_INT_DIS_MEAS_EN #define'd in 'cpu_cfg.h'
*
* (b) Disabled, if CPU_CFG_INT_DIS_MEAS_EN NOT #define'd in 'cpu_cfg.h'
*
* See also 'cpu_core.h FUNCTION PROTOTYPES Note #1'.
*
* (b) Configure CPU_CFG_INT_DIS_MEAS_OVRHD_NBR with the number of times to measure &
* average the interrupts disabled time measurements overhead.
*
* See also 'cpu_core.c CPU_IntDisMeasInit() Note #3a'.
*********************************************************************************************************
*/
#if 0 /* Configure CPU interrupts disabled time ... */
#define CPU_CFG_INT_DIS_MEAS_EN /* ... measurements feature (see Note #1a). */
#endif
/* Configure number of interrupts disabled overhead ... */
#define CPU_CFG_INT_DIS_MEAS_OVRHD_NBR 1u /* ... time measurements (see Note #1b). */
/*
*********************************************************************************************************
* CPU COUNT ZEROS CONFIGURATION
*
* Note(s) : (1) (a) Configure CPU_CFG_LEAD_ZEROS_ASM_PRESENT to define count leading zeros bits
* function(s) in :
*
* (1) 'cpu_a.asm', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable assembly-optimized function(s)
*
* (2) 'cpu_core.c', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT NOT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
*
* (b) Configure CPU_CFG_TRAIL_ZEROS_ASM_PRESENT to define count trailing zeros bits
* function(s) in :
*
* (1) 'cpu_a.asm', if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable assembly-optimized function(s)
*
* (2) 'cpu_core.c', if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT NOT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
*********************************************************************************************************
*/
#if 0 /* Configure CPU count leading zeros bits ... */
#define CPU_CFG_LEAD_ZEROS_ASM_PRESENT /* ... assembly-version (see Note #1a). */
#endif
#if 0 /* Configure CPU count trailing zeros bits ... */
#define CPU_CFG_TRAIL_ZEROS_ASM_PRESENT /* ... assembly-version (see Note #1b). */
#endif
/*
*********************************************************************************************************
* CPU ENDIAN TYPE OVERRIDE
*
* Note(s) : (1) Configure CPU_CFG_ENDIAN_TYPE to override the default CPU endian type defined in cpu.h.
*
* (a) CPU_ENDIAN_TYPE_BIG Big- endian word order (CPU words' most significant
* octet @ lowest memory address)
* (b) CPU_ENDIAN_TYPE_LITTLE Little-endian word order (CPU words' least significant
* octet @ lowest memory address)
*
* (2) Defining CPU_CFG_ENDIAN_TYPE here is only valid for supported bi-endian architectures.
* See 'cpu.h CPU WORD CONFIGURATION Note #3' for details
*********************************************************************************************************
*/
#if 0
#define CPU_CFG_ENDIAN_TYPE CPU_ENDIAN_TYPE_BIG /* Defines CPU data word-memory order (see Note #2). */
#endif
/*
*********************************************************************************************************
* CACHE MANAGEMENT
*
* Note(s) : (1) Configure CPU_CFG_CACHE_MGMT_EN to enable the cache managment API.
*
* (2) Defining CPU_CFG_CACHE_MGMT_EN to DEF_ENABLED only enable the cache management function.
* Cache are assumed to be configured and enabled by the time CPU_init() is called.
*********************************************************************************************************
*/
#define CPU_CFG_CACHE_MGMT_EN DEF_DISABLED
/*
*********************************************************************************************************
* MODULE END
*********************************************************************************************************
*/
#endif /* End of CPU cfg module include. */
#define CPU_CACHE_CFG_L2C310_BASE_ADDR 0xF8F02000

1
src/APP/Aufgabe2/ps7/core0/cfg/cpu_cfg.h Symbolic link
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@@ -0,0 +1 @@
../../../../Aufgabe1/ps7/core0/cfg/cpu_cfg.h

171
src/APP/Aufgabe2/ps7/core0/cfg/lib_cfg.h
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@@ -1,171 +0,0 @@
/*
*********************************************************************************************************
* EXAMPLE CODE
*
* This file is provided as an example on how to use Micrium products.
*
* Please feel free to use any application code labeled as 'EXAMPLE CODE' in
* your application products. Example code may be used as is, in whole or in
* part, or may be used as a reference only. This file can be modified as
* required to meet the end-product requirements.
*
* Please help us continue to provide the Embedded community with the finest
* software available. Your honesty is greatly appreciated.
*
* You can find information about uC/LIB by visiting doc.micrium.com.
* You can contact us at: http://www.micrium.com
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* CUSTOM LIBRARY CONFIGURATION FILE
*
* TEMPLATE
*
* Filename : lib_cfg.h
* Version : V1.38.01.00
* Programmer(s) : FBJ
* JFD
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* MODULE
*********************************************************************************************************
*/
#ifndef LIB_CFG_MODULE_PRESENT
#define LIB_CFG_MODULE_PRESENT
/*
*********************************************************************************************************
*********************************************************************************************************
* MEMORY LIBRARY CONFIGURATION
*********************************************************************************************************
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* MEMORY LIBRARY ARGUMENT CHECK CONFIGURATION
*
* Note(s) : (1) Configure LIB_MEM_CFG_ARG_CHK_EXT_EN to enable/disable the memory library suite external
* argument check feature :
*
* (a) When ENABLED, arguments received from any port interface provided by the developer
* or application are checked/validated.
*
* (b) When DISABLED, NO arguments received from any port interface provided by the developer
* or application are checked/validated.
*********************************************************************************************************
*/
/* External argument check. */
/* Indicates if arguments received from any port ... */
/* ... interface provided by the developer or ... */
/* ... application are checked/validated. */
#define LIB_MEM_CFG_ARG_CHK_EXT_EN DEF_DISABLED
/*
*********************************************************************************************************
* MEMORY LIBRARY ASSEMBLY OPTIMIZATION CONFIGURATION
*
* Note(s) : (1) Configure LIB_MEM_CFG_OPTIMIZE_ASM_EN to enable/disable assembly-optimized memory function(s).
*********************************************************************************************************
*/
/* Assembly-optimized function(s). */
/* Enable/disable assembly-optimized memory ... */
/* ... function(s). [see Note #1] */
#define LIB_MEM_CFG_OPTIMIZE_ASM_EN DEF_DISABLED
/*
*********************************************************************************************************
* MEMORY ALLOCATION CONFIGURATION
*
* Note(s) : (1) Configure LIB_MEM_CFG_DBG_INFO_EN to enable/disable memory allocation usage tracking
* that associates a name with each segment or dynamic pool allocated.
*
* (2) (a) Configure LIB_MEM_CFG_HEAP_SIZE with the desired size of heap memory (in octets).
*
* (b) Configure LIB_MEM_CFG_HEAP_BASE_ADDR to specify a base address for heap memory :
*
* (1) Heap initialized to specified application memory, if LIB_MEM_CFG_HEAP_BASE_ADDR
* #define'd in 'lib_cfg.h';
* CANNOT #define to address 0x0
*
* (2) Heap declared to Mem_Heap[] in 'lib_mem.c', if LIB_MEM_CFG_HEAP_BASE_ADDR
* NOT #define'd in 'lib_cfg.h'
*********************************************************************************************************
*/
/* Allocation debugging information. */
/* Enable/disable allocation of debug information ... */
/* ... associated to each memory allocation. */
#define LIB_MEM_CFG_DBG_INFO_EN DEF_DISABLED
/* Heap memory size (in bytes). */
/* Configure the desired size of the heap memory. ... */
/* ... Set to 0 to disable heap allocation features. */
#define LIB_MEM_CFG_HEAP_SIZE 64*1024
/* Heap memory padding alignment (in bytes). */
/* Configure the desired size of padding alignment ... */
/* ... of each buffer allocated from the heap. */
#define LIB_MEM_CFG_HEAP_PADDING_ALIGN LIB_MEM_PADDING_ALIGN_NONE
#if 0 /* Remove this to have heap alloc at specified addr. */
#define LIB_MEM_CFG_HEAP_BASE_ADDR 0
#endif
/*
*********************************************************************************************************
*********************************************************************************************************
* STRING LIBRARY CONFIGURATION
*********************************************************************************************************
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* STRING FLOATING POINT CONFIGURATION
*
* Note(s) : (1) Configure LIB_STR_CFG_FP_EN to enable/disable floating point string function(s).
*
* (2) Configure LIB_STR_CFG_FP_MAX_NBR_DIG_SIG to configure the maximum number of significant
* digits to calculate &/or display for floating point string function(s).
*
* See also 'lib_str.h STRING FLOATING POINT DEFINES Note #1'.
*********************************************************************************************************
*/
/* Floating point feature(s). */
/* Enable/disable floating point to string functions. */
#define LIB_STR_CFG_FP_EN DEF_DISABLED
/* Floating point number of significant digits. */
/* Configure the maximum number of significant ... */
/* ... digits to calculate &/or display for ... */
/* ... floating point string function(s). */
#define LIB_STR_CFG_FP_MAX_NBR_DIG_SIG LIB_STR_FP_MAX_NBR_DIG_SIG_DFLT
/*
*********************************************************************************************************
* MODULE END
*********************************************************************************************************
*/
#endif /* End of lib cfg module include. */

1
src/APP/Aufgabe2/ps7/core0/cfg/lib_cfg.h Symbolic link
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@@ -0,0 +1 @@
../../../../Aufgabe1/ps7/core0/cfg/lib_cfg.h

42
src/APP/Aufgabe2/ps7/core0/cfg/mmu_cfg.h
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@@ -1,42 +0,0 @@
/*
* mmu_cfg.h
*
* Created on: 25.04.2018
* Author: kaige
*/
#ifndef SRC_APP_LWIPREWORK_PS7_CORE0_CFG_MMU_CFG_H_
#define SRC_APP_LWIPREWORK_PS7_CORE0_CFG_MMU_CFG_H_
#include "mmu.h"
/*------------------------------------------------------------------------------------------------*/
/*!
* \brief FIRST LEVEL TRANSLATION TABLE (FTT)
*
* \ingroup PAR_CPU_MMU
*
* This variable represents the first level translation table. Each entry within
* the table represents the configuration of a 1MB memory segment. If a memory
* portion below 1MB must be accessed, the entry represents a pointer to the
* linked coarse page table, which contains the information of that 1MB in detail.
*
* \note This table MUST be aligned at 16kB boundary.
*/
/*------------------------------------------------------------------------------------------------*/
const PAR_MEM_REGION_T PARMemTbl_Core[] = {
/* +-------------------------------------------------------------------------------------------+
* | virtual | physical | size | owner | permissions | HID Field |
* +-----------+-----------+---------------+------------------+-----------------+--------------+*/
// First 1MB is marked as non-cacheable/non-bufferable (contains 3x 64KB SRAM @ address 0x00000000
{ 0x00000000, 0x00000000, MMU_SIZE_1MB, PAR_AP_PRW__URW_, PAR_HID_TEX_CB_CACHED_MEMORY | PAR_HID_CACHE_INNER_CB | PAR_HID_CACHE_OUTER_CB },
// DDR Memory is marked as normal (only 512MB for now)
{ 0x00100000, 0x00100000, MMU_SIZE_16MB, PAR_AP_PRW__URW_, PAR_HID_TEX_CB_CACHED_MEMORY | PAR_HID_CACHE_INNER___ | PAR_HID_CACHE_OUTER___ },
// Device section
{ 0xE0000000, 0xE0000000, MMU_SIZE_512MB-MMU_SIZE_1MB, PAR_AP_PRW__URW_, PAR_HID_EXCLUSIVE_SYS_DEVICE },
// Upper 1MB section contains 1x 64KB SRAM @ address 0xFFFF0000
{ 0xFFF00000, 0xFFF00000, MMU_SIZE_1MB, PAR_AP_PRW__URW_, PAR_HID_TEX_CB_OUT_IN_NON_CACHABLE }
};
#endif /* SRC_APP_LWIPREWORK_PS7_CORE0_CFG_MMU_CFG_H_ */

1
src/APP/Aufgabe2/ps7/core0/cfg/mmu_cfg.h Symbolic link
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@@ -0,0 +1 @@
../../../../Aufgabe1/ps7/core0/cfg/mmu_cfg.h

145
src/APP/Aufgabe2/ps7/core0/cfg/os_cfg.h
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@@ -1,145 +0,0 @@
/*
*********************************************************************************************************
* uC/OS-II
* The Real-Time Kernel
* uC/OS-II Configuration File for V2.9x
*
* (c) Copyright 2005-2014, Micrium, Weston, FL
* All Rights Reserved
*
*
* File : OS_CFG.H
* By : Jean J. Labrosse
* Version : V2.92.11
*
* LICENSING TERMS:
* ---------------
* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research.
* If you plan on using uC/OS-II in a commercial product you need to contact Micrium to properly license
* its use in your product. We provide ALL the source code for your convenience and to help you experience
* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a
* licensing fee.
*********************************************************************************************************
*/
#ifndef OS_CFG_H
#define OS_CFG_H
/* ---------------------- MISCELLANEOUS ----------------------- */
#define OS_APP_HOOKS_EN 1u /* Application-defined hooks are called from the uC/OS-II hooks */
#define OS_ARG_CHK_EN 0u /* Enable (1) or Disable (0) argument checking */
#define OS_CPU_HOOKS_EN 1u /* uC/OS-II hooks are found in the processor port files */
#define OS_DEBUG_EN 1u /* Enable(1) debug variables */
#define OS_EVENT_MULTI_EN 1u /* Include code for OSEventPendMulti() */
#define OS_EVENT_NAME_EN 1u /* Enable names for Sem, Mutex, Mbox and Q */
#define OS_LOWEST_PRIO 63u /* Defines the lowest priority that can be assigned ... */
/* ... MUST NEVER be higher than 254! */
#define OS_MAX_EVENTS 20u /* Max. number of event control blocks in your application */
#define OS_MAX_FLAGS 5u /* Max. number of Event Flag Groups in your application */
#define OS_MAX_MEM_PART 5u /* Max. number of memory partitions */
#define OS_MAX_QS 6u /* Max. number of queue control blocks in your application */
#define OS_MAX_TASKS 20u /* Max. number of tasks in your application, MUST be >= 2 */
#define OS_SCHED_LOCK_EN 1u /* Include code for OSSchedLock() and OSSchedUnlock() */
#define OS_TICK_STEP_EN 1u /* Enable tick stepping feature for uC/OS-View */
#define OS_TICKS_PER_SEC 1000u /* Set the number of ticks in one second */
#define OS_TLS_TBL_SIZE 0u /* Size of Thread-Local Storage Table */
/* --------------------- TASK STACK SIZE ---------------------- */
#define OS_TASK_TMR_STK_SIZE 128u /* Timer task stack size (# of OS_STK wide entries) */
#define OS_TASK_STAT_STK_SIZE 128u /* Statistics task stack size (# of OS_STK wide entries) */
#define OS_TASK_IDLE_STK_SIZE 128u /* Idle task stack size (# of OS_STK wide entries) */
/* --------------------- TASK MANAGEMENT ---------------------- */
#define OS_TASK_CHANGE_PRIO_EN 1u /* Include code for OSTaskChangePrio() */
#define OS_TASK_CREATE_EN 1u /* Include code for OSTaskCreate() */
#define OS_TASK_CREATE_EXT_EN 1u /* Include code for OSTaskCreateExt() */
#define OS_TASK_DEL_EN 1u /* Include code for OSTaskDel() */
#define OS_TASK_NAME_EN 1u /* Enable task names */
#define OS_TASK_PROFILE_EN 1u /* Include variables in OS_TCB for profiling */
#define OS_TASK_QUERY_EN 1u /* Include code for OSTaskQuery() */
#define OS_TASK_REG_TBL_SIZE 1u /* Size of task variables array (#of INT32U entries) */
#define OS_TASK_STAT_EN 1u /* Enable (1) or Disable(0) the statistics task */
#define OS_TASK_STAT_STK_CHK_EN 1u /* Check task stacks from statistic task */
#define OS_TASK_SUSPEND_EN 1u /* Include code for OSTaskSuspend() and OSTaskResume() */
#define OS_TASK_SW_HOOK_EN 1u /* Include code for OSTaskSwHook() */
/* ----------------------- EVENT FLAGS ------------------------ */
#define OS_FLAG_EN 1u /* Enable (1) or Disable (0) code generation for EVENT FLAGS */
#define OS_FLAG_ACCEPT_EN 1u /* Include code for OSFlagAccept() */
#define OS_FLAG_DEL_EN 1u /* Include code for OSFlagDel() */
#define OS_FLAG_NAME_EN 1u /* Enable names for event flag group */
#define OS_FLAG_QUERY_EN 1u /* Include code for OSFlagQuery() */
#define OS_FLAG_WAIT_CLR_EN 1u /* Include code for Wait on Clear EVENT FLAGS */
#define OS_FLAGS_NBITS 16u /* Size in #bits of OS_FLAGS data type (8, 16 or 32) */
/* -------------------- MESSAGE MAILBOXES --------------------- */
#define OS_MBOX_EN 1u /* Enable (1) or Disable (0) code generation for MAILBOXES */
#define OS_MBOX_ACCEPT_EN 1u /* Include code for OSMboxAccept() */
#define OS_MBOX_DEL_EN 1u /* Include code for OSMboxDel() */
#define OS_MBOX_PEND_ABORT_EN 1u /* Include code for OSMboxPendAbort() */
#define OS_MBOX_POST_EN 1u /* Include code for OSMboxPost() */
#define OS_MBOX_POST_OPT_EN 1u /* Include code for OSMboxPostOpt() */
#define OS_MBOX_QUERY_EN 1u /* Include code for OSMboxQuery() */
/* --------------------- MEMORY MANAGEMENT -------------------- */
#define OS_MEM_EN 1u /* Enable (1) or Disable (0) code generation for MEMORY MANAGER */
#define OS_MEM_NAME_EN 1u /* Enable memory partition names */
#define OS_MEM_QUERY_EN 1u /* Include code for OSMemQuery() */
/* ---------------- MUTUAL EXCLUSION SEMAPHORES --------------- */
#define OS_MUTEX_EN 1u /* Enable (1) or Disable (0) code generation for MUTEX */
#define OS_MUTEX_ACCEPT_EN 1u /* Include code for OSMutexAccept() */
#define OS_MUTEX_DEL_EN 1u /* Include code for OSMutexDel() */
#define OS_MUTEX_QUERY_EN 1u /* Include code for OSMutexQuery() */
/* ---------------------- MESSAGE QUEUES ---------------------- */
#define OS_Q_EN 1u /* Enable (1) or Disable (0) code generation for QUEUES */
#define OS_Q_ACCEPT_EN 1u /* Include code for OSQAccept() */
#define OS_Q_DEL_EN 1u /* Include code for OSQDel() */
#define OS_Q_FLUSH_EN 1u /* Include code for OSQFlush() */
#define OS_Q_PEND_ABORT_EN 1u /* Include code for OSQPendAbort() */
#define OS_Q_POST_EN 1u /* Include code for OSQPost() */
#define OS_Q_POST_FRONT_EN 1u /* Include code for OSQPostFront() */
#define OS_Q_POST_OPT_EN 1u /* Include code for OSQPostOpt() */
#define OS_Q_QUERY_EN 1u /* Include code for OSQQuery() */
/* ------------------------ SEMAPHORES ------------------------ */
#define OS_SEM_EN 1u /* Enable (1) or Disable (0) code generation for SEMAPHORES */
#define OS_SEM_ACCEPT_EN 1u /* Include code for OSSemAccept() */
#define OS_SEM_DEL_EN 1u /* Include code for OSSemDel() */
#define OS_SEM_PEND_ABORT_EN 1u /* Include code for OSSemPendAbort() */
#define OS_SEM_QUERY_EN 1u /* Include code for OSSemQuery() */
#define OS_SEM_SET_EN 1u /* Include code for OSSemSet() */
/* --------------------- TIME MANAGEMENT ---------------------- */
#define OS_TIME_DLY_HMSM_EN 1u /* Include code for OSTimeDlyHMSM() */
#define OS_TIME_DLY_RESUME_EN 1u /* Include code for OSTimeDlyResume() */
#define OS_TIME_GET_SET_EN 1u /* Include code for OSTimeGet() and OSTimeSet() */
#define OS_TIME_TICK_HOOK_EN 1u /* Include code for OSTimeTickHook() */
/* --------------------- TIMER MANAGEMENT --------------------- */
#define OS_TMR_EN 0u /* Enable (1) or Disable (0) code generation for TIMERS */
#define OS_TMR_CFG_MAX 16u /* Maximum number of timers */
#define OS_TMR_CFG_NAME_EN 1u /* Determine timer names */
#define OS_TMR_CFG_WHEEL_SIZE 7u /* Size of timer wheel (#Spokes) */
#define OS_TMR_CFG_TICKS_PER_SEC 10u /* Rate at which timer management task runs (Hz) */
#endif

1
src/APP/Aufgabe2/ps7/core0/cfg/os_cfg.h Symbolic link
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../../../../Aufgabe1/ps7/core0/cfg/os_cfg.h

686
src/APP/Aufgabe2/ps7/core0/cfg/xparameters.h
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/******************************************************************/
/* Definition for CPU ID */
#define XPAR_CPU_ID 0
/* Definitions for peripheral PS7_CORTEXA9_0 */
#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
#define XPAR_PS7_CORTEXA9_1_CPU_CLK_FREQ_HZ XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ
/******************************************************************/
/* Canonical definitions for peripheral PS7_CORTEXA9_0 */
#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
#define XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
/******************************************************************/
#undef DEF_DISABLED
#undef DEF_ENABLED
#define DEF_ENABLED 1
#define DEF_DISABLED 0
#include "xparameters_ps.h"
/******************************************************************/
/* Definitions for driver BRAM */
#define XPAR_XBRAM_NUM_INSTANCES 1
/* Definitions for peripheral AXI_BRAM_CTRL_0 */
#define XPAR_AXI_BRAM_CTRL_0_DEVICE_ID 0
#define XPAR_AXI_BRAM_CTRL_0_DATA_WIDTH 32
#define XPAR_AXI_BRAM_CTRL_0_ECC 0
#define XPAR_AXI_BRAM_CTRL_0_FAULT_INJECT 0
#define XPAR_AXI_BRAM_CTRL_0_CE_FAILING_REGISTERS 0
#define XPAR_AXI_BRAM_CTRL_0_UE_FAILING_REGISTERS 0
#define XPAR_AXI_BRAM_CTRL_0_ECC_STATUS_REGISTERS 0
#define XPAR_AXI_BRAM_CTRL_0_CE_COUNTER_WIDTH 0
#define XPAR_AXI_BRAM_CTRL_0_ECC_ONOFF_REGISTER 0
#define XPAR_AXI_BRAM_CTRL_0_ECC_ONOFF_RESET_VALUE 0
#define XPAR_AXI_BRAM_CTRL_0_WRITE_ACCESS 0
#define XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR 0x40000000
#define XPAR_AXI_BRAM_CTRL_0_S_AXI_HIGHADDR 0x40001FFF
#define XPAR_AXI_BRAM_CTRL_0_S_AXI_CTRL_BASEADDR 0xFFFFFFFF
#define XPAR_AXI_BRAM_CTRL_0_S_AXI_CTRL_HIGHADDR 0xFFFFFFFF
/******************************************************************/
/* Canonical definitions for peripheral AXI_BRAM_CTRL_0 */
#define XPAR_BRAM_0_DEVICE_ID XPAR_AXI_BRAM_CTRL_0_DEVICE_ID
#define XPAR_BRAM_0_DATA_WIDTH 32
#define XPAR_BRAM_0_ECC 0
#define XPAR_BRAM_0_FAULT_INJECT 0
#define XPAR_BRAM_0_CE_FAILING_REGISTERS 0
#define XPAR_BRAM_0_UE_FAILING_REGISTERS 0
#define XPAR_BRAM_0_ECC_STATUS_REGISTERS 0
#define XPAR_BRAM_0_CE_COUNTER_WIDTH 0
#define XPAR_BRAM_0_ECC_ONOFF_REGISTER 0
#define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 0
#define XPAR_BRAM_0_WRITE_ACCESS 0
#define XPAR_BRAM_0_BASEADDR 0x40000000
#define XPAR_BRAM_0_HIGHADDR 0x40001FFF
/******************************************************************/
/* Definitions for peripheral PS7_DDR_0 */
#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
/******************************************************************/
/* Definitions for driver DEVCFG */
#define XPAR_XDCFG_NUM_INSTANCES 1
/* Definitions for peripheral PS7_DEV_CFG_0 */
#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0
#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000
#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FF
/******************************************************************/
/* Canonical definitions for peripheral PS7_DEV_CFG_0 */
#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
#define XPAR_XDCFG_0_BASEADDR 0xF8007000
#define XPAR_XDCFG_0_HIGHADDR 0xF80070FF
/******************************************************************/
/* Definitions for driver DMAPS */
#define XPAR_XDMAPS_NUM_INSTANCES 2
/* Definitions for peripheral PS7_DMA_NS */
#define XPAR_PS7_DMA_NS_DEVICE_ID 0
#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF
/* Definitions for peripheral PS7_DMA_S */
#define XPAR_PS7_DMA_S_DEVICE_ID 1
#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF
/******************************************************************/
/* Canonical definitions for peripheral PS7_DMA_NS */
#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
#define XPAR_XDMAPS_0_BASEADDR 0xF8004000
#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF
/* Canonical definitions for peripheral PS7_DMA_S */
#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
#define XPAR_XDMAPS_1_BASEADDR 0xF8003000
#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF
/******************************************************************/
/* Definitions for peripheral PS7_AFI_0 */
#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
/* Definitions for peripheral PS7_AFI_1 */
#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000
#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF
/* Definitions for peripheral PS7_AFI_2 */
#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000
#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF
/* Definitions for peripheral PS7_AFI_3 */
#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000
#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
/* Definitions for peripheral PS7_DDRC_0 */
#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
/* Definitions for peripheral PS7_GLOBALTIMER_0 */
#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200
#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF
/* Definitions for peripheral PS7_GPV_0 */
#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000
#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF
/* Definitions for peripheral PS7_INTC_DIST_0 */
#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000
#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF
/* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
/* Definitions for peripheral PS7_OCMC_0 */
#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000
#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF
/* Definitions for peripheral PS7_PL310_0 */
#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000
#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF
/* Definitions for peripheral PS7_PMU_0 */
#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000
#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF
#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000
#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF
/* Definitions for peripheral PS7_QSPI_LINEAR_0 */
#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFDFFFFFF
/* Definitions for peripheral PS7_RAM_0 */
#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
/* Definitions for peripheral PS7_RAM_1 */
#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000
#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
/* Definitions for peripheral PS7_SLCR_0 */
#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF
/******************************************************************/
/* Definitions for driver GPIO */
#define XPAR_XGPIO_NUM_INSTANCES 1
/* Definitions for peripheral AXI_GPIO_0 */
#define XPAR_AXI_GPIO_0_BASEADDR 0x41200000
#define XPAR_AXI_GPIO_0_HIGHADDR 0x4120FFFF
#define XPAR_AXI_GPIO_0_DEVICE_ID 0
#define XPAR_AXI_GPIO_0_INTERRUPT_PRESENT 0
#define XPAR_AXI_GPIO_0_IS_DUAL 0
/******************************************************************/
/* Canonical definitions for peripheral AXI_GPIO_0 */
#define XPAR_GPIO_0_BASEADDR 0x41200000
#define XPAR_GPIO_0_HIGHADDR 0x4120FFFF
#define XPAR_GPIO_0_DEVICE_ID XPAR_AXI_GPIO_0_DEVICE_ID
#define XPAR_GPIO_0_INTERRUPT_PRESENT 0
#define XPAR_GPIO_0_IS_DUAL 0
/******************************************************************/
/* Definitions for driver GPIOPS */
#define XPAR_XGPIOPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_GPIO_0 */
#define XPAR_PS7_GPIO_0_DEVICE_ID 0
#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
/******************************************************************/
/* Canonical definitions for peripheral PS7_GPIO_0 */
#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
/******************************************************************/
///* Definitions for driver IICPS */
//#define XPAR_XIICPS_NUM_INSTANCES 1
//
///* Definitions for peripheral PS7_I2C_0 */
//#define XPAR_PS7_I2C_0_DEVICE_ID 0
//#define XPAR_PS7_I2C_0_BASEADDR 0xE0004000
//#define XPAR_PS7_I2C_0_HIGHADDR 0xE0004FFF
//#define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 111111115
/******************************************************************/
/* Canonical definitions for peripheral PS7_I2C_0 */
#define XPAR_XIICPS_0_DEVICE_ID XPAR_PS7_I2C_0_DEVICE_ID
#define XPAR_XIICPS_0_BASEADDR 0xE0004000
#define XPAR_XIICPS_0_HIGHADDR 0xE0004FFF
#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 111111115
/******************************************************************/
/* Definitions for driver QSPIPS */
#define XPAR_XQSPIPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_QSPI_0 */
#define XPAR_PS7_QSPI_0_DEVICE_ID 0
#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000
#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000
#define XPAR_PS7_QSPI_0_QSPI_MODE 2
/******************************************************************/
/* Canonical definitions for peripheral PS7_QSPI_0 */
#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID
#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000
#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000
#define XPAR_XQSPIPS_0_QSPI_MODE 2
/******************************************************************/
/* Definitions for driver SCUWDT */
#define XPAR_XSCUWDT_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SCUWDT_0 */
#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF
/******************************************************************/
/* Canonical definitions for peripheral PS7_SCUWDT_0 */
#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
/******************************************************************/
/* Definitions for driver UCOS_EMACPS */
#define XPAR_UCOS_EMACPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_ETHERNET_0 */
#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0
#define XPAR_PS7_ETHERNET_0_BASEADDR 0x00000000
#define XPAR_PS7_ETHERNET_0_HIGHADDR 0x00000000
#define XPAR_PS7_ETHERNET_0_CLOCK_FREQ_HZ 0
/******************************************************************/
/* Canonical definitions for peripheral PS7_ETHERNET_0 */
#define XPAR_UCOS_EMACPS_0_NUM_INSTANCES 0
#define XPAR_UCOS_EMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID
#define XPAR_UCOS_EMACPS_0_BASEADDR 0x00000000
#define XPAR_UCOS_EMACPS_0_HIGHADDR 0x00000000
#define XPAR_UCOS_EMACPS_0_CLOCK_FREQ_HZ 0
/******************************************************************/
/* Definitions for driver UCOS_L2CACHEC */
#define XPAR_UCOS_L2CACHEC_NUM_INSTANCES 1
/* Definitions for peripheral PS7_L2CACHEC_0 */
#define XPAR_PS7_L2CACHEC_0_DEVICE_ID 0
#define XPAR_PS7_L2CACHEC_0_BASEADDR 0xF8F02000
#define XPAR_PS7_L2CACHEC_0_HIGHADDR 0xF8F02FFF
/******************************************************************/
/* Definitions for driver UCOS_SCUC */
#define XPAR_UCOS_L2CACHEC_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SCUC_0 */
#define XPAR_PS7_SCUC_0_DEVICE_ID 0
#define XPAR_PS7_SCUC_0_BASEADDR 0xF8F00000
#define XPAR_PS7_SCUC_0_HIGHADDR 0xF8F000FC
/******************************************************************/
/***Definitions for Core_nIRQ/nFIQ interrupts ****/
/* Definitions for driver UCOS_SCUGIC */
#define XPAR_XSCUGIC_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SCUGIC_0 */
#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0
#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100
#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FF
#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000
/******************************************************************/
/* Canonical definitions for peripheral PS7_SCUGIC_0 */
#define XPAR_SCUGIC_0_DEVICE_ID 0
#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100
#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FF
#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000
/******************************************************************/
/* Definitions for driver UCOS_SCUTIMER */
#define XPAR_UCOS_SCUC_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SCUTIMER_0 */
#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F
/******************************************************************/
/* Definitions for driver UCOS_SDPS */
#define XPAR_UCOS_SDPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SD_0 */
#define XPAR_PS7_SD_0_DEVICE_ID 0
#define XPAR_PS7_SD_0_BASEADDR 0xE0100000
#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
/******************************************************************/
/* Canonical definitions for peripheral PS7_SD_0 */
#define XPAR_UCOS_SDPS_0_NUM_INSTANCES 0
#define XPAR_UCOS_SDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID
#define XPAR_UCOS_SDPS_0_BASEADDR 0xE0100000
#define XPAR_UCOS_SDPS_0_HIGHADDR 0xE0100FFF
#define XPAR_UCOS_SDPS_0_SDIO_CLK_FREQ_HZ 50000000
/******************************************************************/
///* Definitions for driver UCOS_TTCPS */
//#define XPAR_UCOS_TTCPS_NUM_INSTANCES 3
//
///* Definitions for peripheral PS7_TTC_0 */
//#define XPAR_PS7_TTC_0_DEVICE_ID 0
//#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000
//#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115
//#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0
//#define XPAR_PS7_TTC_1_DEVICE_ID 1
//#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004
//#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115
//#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0
//#define XPAR_PS7_TTC_2_DEVICE_ID 2
//#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008
//#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115
//#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0
/******************************************************************/
/* Definitions for driver UCOS_UARTPS */
#define XPAR_UCOS_UARTPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_UART_1 */
#define XPAR_PS7_UART_1_DEVICE_ID 2
#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 9600
#define XPAR_PS7_UART_1_HAS_MODEM 0
/******************************************************************/
/* Canonical definitions for peripheral PS7_UART_1 */
#define XPAR_UCOS_UARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
#define XPAR_UCOS_UARTPS_0_BASEADDR 0xE0001000
#define XPAR_UCOS_UARTPS_0_HIGHADDR 0xE0001FFF
#define XPAR_UCOS_UARTPS_0_UART_CLK_FREQ_HZ 50000000
#define XPAR_UCOS_UARTPS_0_HAS_MODEM 0
/******************************************************************/
/* Definitions for driver UCOS_USBPS */
#define XPAR_UCOS_USBPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_USB_0 */
#define XPAR_PS7_USB_0_DEVICE_ID 0
#define XPAR_PS7_USB_0_BASEADDR 0xE0002000
#define XPAR_PS7_USB_0_HIGHADDR 0xE0002FFF
/******************************************************************/
/* Canonical definitions for peripheral PS7_USB_0 */
#define XPAR_UCOS_USBPS_0_DEVICE_ID XPAR_PS7_USB_0_DEVICE_ID
#define XPAR_UCOS_USBPS_0_BASEADDR 0xE0002000
#define XPAR_UCOS_USBPS_0_HIGHADDR 0xE0002FFF
/******************************************************************/
/* Definitions for driver XADCPS */
#define XPAR_XADCPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_XADC_0 */
#define XPAR_PS7_XADC_0_DEVICE_ID 0
#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100
#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120
/******************************************************************/
/* Canonical definitions for peripheral PS7_XADC_0 */
#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
#define XPAR_XADCPS_0_BASEADDR 0xF8007100
#define XPAR_XADCPS_0_HIGHADDR 0xF8007120
/******************************************************************/
//UCOS STDOUT
#define UCOS_STDOUT_DRIVER UCOS_UART_PS7_UART
#define UCOS_STDOUT_DEVICE_ID 0
#define STDOUT_BASEADDRESS
//UCOS Ethernet
#define UCOS_ETHERNET_DRIVER UCOS_ETHERNET_EMACPS
//UCOS TASK PARAMETERS
#define UCOS_START_TASK_PRIO 5
#define UCOS_START_TASK_STACK_SIZE 784
#define UCOS_START_DEBUG_TRACE DEF_ENABLED
#define NET_TASK_CFG_RX_PRIO 30
#define NET_TASK_CFG_RX_STACK_SIZE 3072
#define NET_TASK_CFG_TXDEALLOC_PRIO 6
#define NET_TASK_CFG_TXDEALLOC_STACK_SIZE 2048
#define NET_TASK_CFG_TMR_PRIO 18
#define NET_TASK_CFG_TMR_STACK_SIZE 2048
#define HTTPc_OS_CFG_TASK_PRIO 20
#define HTTPc_OS_CFG_TASK_STK_SIZE 2048
#define UCOS_HTTPc_OS_CFG_TASK_DELAY 1
#define UCOS_HTTPc_OS_CFG_MSG_Q_SIZE 5
#define UCOS_HTTPc_OS_CFG_TIMEOUT 2000
#define UCOS_HTTPc_OS_CFG_INACTIVITY_TIMEOUT 30
#define UCOS_AMP_MASTER DEF_ENABLED
#define UCOS_CFG_INIT_CAN DEF_ENABLED
#define UCOS_CFG_INIT_NET DEF_ENABLED
#define UCOS_CFG_INIT_FS DEF_DISABLED
#define UCOS_CFG_INIT_OPENAMP DEF_DISABLED
#define UCOS_CFG_INIT_USBD DEF_DISABLED
#define UCOS_CFG_INIT_USBH DEF_DISABLED
#define UCOS_ETHERNET_ADDRESS "10.10.110.2"
#define UCOS_ETHERNET_GATEWAY "10.10.110.1"
#define UCOS_ETHERNET_SUBMASK "255.255.255.0"
#define UCOS_ETHERNET_DHCP DEF_ENABLED
#define UCOS_IF_RX_BUF_NBR 12
#define UCOS_IF_TX_LARGE_BUF_NBR 8
#define UCOS_IF_TX_SMALL_BUF_NBR 8
#define UCOS_IF_RX_DESC_NBR 0
#define UCOS_IF_TX_DESC_NBR 0
#define UCOS_IF_DEDIC_MEM_ADDR 0
#define UCOS_IF_DEDIC_MEM_SIZE 0
#define UCOS_IF_HW_ADDR "50:E5:49:E6:8D:28"
#define UCOS_PHY_BUS_ADDR 255
#define UCOS_PHY_BUS_MODE UCOS_NET_PHY_BUS_MODE_GMII
#define UCOS_PHY_TYPE UCOS_NET_PHY_TYPE_INT
#define UCOS_PHY_SPEED UCOS_NET_PHY_SPD_AUTO
#define UCOS_PHY_DUPLEX UCOS_NET_PHY_DUPLEX_AUTO
#define UCOS_USB_DRIVER UCOS_USB_NONE
#define UCOS_USB_DEVICE_ID 0
#define UCOS_USB_TYPE UCOS_USB_TYPE_DEVICE
#define UCOS_RAMDISK_EN DEF_DISABLED
#define UCOS_RAMDISK_SIZE 128
#define UCOS_RAMDISK_SECTOR_SIZE 512
#define UCOS_RAMDISK_BASE_ADDRESS 0
#define UCOS_SDCARD_EN DEF_DISABLED
#define XPAR_PS7_ETHERNET_0_INT_SOURCE 54
#define XPAR_PS7_SD_0_INT_SOURCE 56
#define XPAR_PS7_UART_1_INT_SOURCE 82
#define XPAR_PS7_USB_0_INT_SOURCE 53
#define UCOS_ZYNQ_CONFIG_MMU DEF_DISABLED
#define UCOS_ZYNQ_ENABLE_MMU DEF_DISABLED
#define UCOS_ZYNQ_CONFIG_CACHES DEF_DISABLED
#define UCOS_ZYNQ_ENABLE_CACHES DEF_DISABLED
#define UCOS_ZYNQ_ENABLE_OPTIMS DEF_DISABLED
#define ZYNQ_ENABLE_EARLY_L1_I_EN DEF_DISABLED
#define ZYNQ_ENABLE_EARLY_L1_D_EN DEF_DISABLED
#define UCOS_CPU_TYPE UCOS_CPU_TYPE_PS7
//Parameters added by Kai Gemlau
#define UCOS_SMP_ENABLE DEF_DISABLED
/******************************************************************/
/* Definitions for driver TTCPS */
#define XPAR_XTTCPS_NUM_INSTANCES 3U
/* Definitions for peripheral PS7_TTC_0 */
#define XPAR_PS7_TTC_0_DEVICE_ID 0U
#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000U
#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115U
#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0U
#define XPAR_PS7_TTC_1_DEVICE_ID 1U
#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004U
#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115U
#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0U
#define XPAR_PS7_TTC_2_DEVICE_ID 2U
#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008U
#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115U
#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0U
/******************************************************************/
/* Canonical definitions for peripheral PS7_TTC_0 */
#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PS7_TTC_0_DEVICE_ID
#define XPAR_XTTCPS_0_BASEADDR 0xF8001000U
#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 111111115U
#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0U
#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PS7_TTC_1_DEVICE_ID
#define XPAR_XTTCPS_1_BASEADDR 0xF8001004U
#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 111111115U
#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0U
#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PS7_TTC_2_DEVICE_ID
#define XPAR_XTTCPS_2_BASEADDR 0xF8001008U
#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 111111115U
#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0U
/******************************************************************/
/* Definitions for driver GPIOPS */
#define XPAR_XGPIOPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_GPIO_0 */
#define XPAR_PS7_GPIO_0_DEVICE_ID 0
#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
/******************************************************************/
/* Canonical definitions for peripheral PS7_GPIO_0 */
#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
/******************************************************************/
/* Definitions for driver IICPS */
#define XPAR_XIICPS_NUM_INSTANCES 2
/* Definitions for peripheral PS7_I2C_0 */
#define XPAR_PS7_I2C_0_DEVICE_ID 0
#define XPAR_PS7_I2C_0_BASEADDR 0xE0004000
#define XPAR_PS7_I2C_0_HIGHADDR 0xE0004FFF
#define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 111111115
/* Definitions for peripheral PS7_I2C_1 */
#define XPAR_PS7_I2C_1_DEVICE_ID 1
#define XPAR_PS7_I2C_1_BASEADDR 0xE0005000
#define XPAR_PS7_I2C_1_HIGHADDR 0xE0005FFF
#define XPAR_PS7_I2C_1_I2C_CLK_FREQ_HZ 111111115
/******************************************************************/
/* Canonical definitions for peripheral PS7_I2C_0 */
#define XPAR_XIICPS_0_DEVICE_ID XPAR_PS7_I2C_0_DEVICE_ID
#define XPAR_XIICPS_0_BASEADDR 0xE0004000
#define XPAR_XIICPS_0_HIGHADDR 0xE0004FFF
#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 111111115
/* Canonical definitions for peripheral PS7_I2C_1 */
#define XPAR_XIICPS_1_DEVICE_ID XPAR_PS7_I2C_1_DEVICE_ID
#define XPAR_XIICPS_1_BASEADDR 0xE0005000
#define XPAR_XIICPS_1_HIGHADDR 0xE0005FFF
#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 111111115
/******************************************************************/
/* Definitions for driver UARTPS */
#define XPAR_XUARTPS_NUM_INSTANCES 1

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src/APP/Aufgabe2/ps7/core0/cfg/xparameters.h Symbolic link
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../../../../Aufgabe1/ps7/core0/cfg/xparameters.h

325
src/APP/Aufgabe2/ps7/core0/cfg/xparameters_ps.h
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/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xparameters_ps.h
*
* This file contains the address definitions for the hard peripherals
* attached to the ARM Cortex A9 core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------- -------- ---------------------------------------------------
* 1.00a ecm/sdm 02/01/10 Initial version
* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
* driver tcl
* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#ifndef _XPARAMETERS_PS_H_
#define _XPARAMETERS_PS_H_
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions *****************************/
/*
* This block contains constant declarations for the peripherals
* within the hardblock
*/
/* Canonical definitions for DDR MEMORY */
#define XPAR_DDR_MEM_BASEADDR 0x00000000U
#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
/* Canonical definitions for Interrupts */
#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID
#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID
#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID
#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID
#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID
#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID
#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR
#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR
/* Canonical definitions for DMAC */
/* Canonical definitions for WDT */
/* Canonical definitions for SLCR */
#define XPAR_XSLCR_NUM_INSTANCES 1U
#define XPAR_XSLCR_0_DEVICE_ID 0U
#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR
/* Canonical definitions for SCU GIC */
#define XPAR_SCUGIC_NUM_INSTANCES 1U
#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000100U)
#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
#define XPAR_SCUGIC_ACK_BEFORE 0U
/* Canonical definitions for Global Timer */
#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U
#define XPAR_GLOBAL_TMR_DEVICE_ID 0U
#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U)
#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID
/* Xilinx Parallel Flash Library (XilFlash) User Settings */
#define XPAR_AXI_EMC
#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
/*
* This block contains constant declarations for the peripherals
* within the hardblock. These have been put for bacwards compatibilty
*/
#define XPS_PERIPHERAL_BASEADDR 0xE0000000U
#define XPS_UART0_BASEADDR 0xE0000000U
#define XPS_UART1_BASEADDR 0xE0001000U
#define XPS_USB0_BASEADDR 0xE0002000U
#define XPS_USB1_BASEADDR 0xE0003000U
#define XPS_I2C0_BASEADDR 0xE0004000U
#define XPS_I2C1_BASEADDR 0xE0005000U
#define XPS_SPI0_BASEADDR 0xE0006000U
#define XPS_SPI1_BASEADDR 0xE0007000U
#define XPS_CAN0_BASEADDR 0xE0008000U
#define XPS_CAN1_BASEADDR 0xE0009000U
#define XPS_GPIO_BASEADDR 0xE000A000U
#define XPS_GEM0_BASEADDR 0xE000B000U
#define XPS_GEM1_BASEADDR 0xE000C000U
#define XPS_QSPI_BASEADDR 0xE000D000U
#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000U
#define XPS_SDIO0_BASEADDR 0xE0100000U
#define XPS_SDIO1_BASEADDR 0xE0101000U
#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U
#define XPS_NAND_BASEADDR 0xE1000000U
#define XPS_PARPORT0_BASEADDR 0xE2000000U
#define XPS_PARPORT1_BASEADDR 0xE4000000U
#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000U
#define XPS_SYS_CTRL_BASEADDR 0xF8000000U /* AKA SLCR */
#define XPS_TTC0_BASEADDR 0xF8001000U
#define XPS_TTC1_BASEADDR 0xF8002000U
#define XPS_DMAC0_SEC_BASEADDR 0xF8003000U
#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000U
#define XPS_WDT_BASEADDR 0xF8005000U
#define XPS_DDR_CTRL_BASEADDR 0xF8006000U
#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U
#define XPS_AFI0_BASEADDR 0xF8008000U
#define XPS_AFI1_BASEADDR 0xF8009000U
#define XPS_AFI2_BASEADDR 0xF800A000U
#define XPS_AFI3_BASEADDR 0xF800B000U
#define XPS_OCM_BASEADDR 0xF800C000U
#define XPS_EFUSE_BASEADDR 0xF800D000U
#define XPS_CORESIGHT_BASEADDR 0xF8800000U
#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U
#define XPS_SCU_PERIPH_BASE 0xF8F00000U
#define XPS_L2CC_BASEADDR 0xF8F02000U
#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U
#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U
#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U
#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U
#define XPS_PERIPH_APB_BASEADDR 0xF8000000U
/* Shared Peripheral Interrupts (SPI) */
#define XPS_CORE_PARITY0_INT_ID 32U
#define XPS_CORE_PARITY1_INT_ID 33U
#define XPS_L2CC_INT_ID 34U
#define XPS_OCMINTR_INT_ID 35U
#define XPS_ECC_INT_ID 36U
#define XPS_PMU0_INT_ID 37U
#define XPS_PMU1_INT_ID 38U
#define XPS_SYSMON_INT_ID 39U
#define XPS_DVC_INT_ID 40U
#define XPS_WDT_INT_ID 41U
#define XPS_TTC0_0_INT_ID 42U
#define XPS_TTC0_1_INT_ID 43U
#define XPS_TTC0_2_INT_ID 44U
#define XPS_DMA0_ABORT_INT_ID 45U
#define XPS_DMA0_INT_ID 46U
#define XPS_DMA1_INT_ID 47U
#define XPS_DMA2_INT_ID 48U
#define XPS_DMA3_INT_ID 49U
#define XPS_SMC_INT_ID 50U
#define XPS_QSPI_INT_ID 51U
#define XPS_GPIO_INT_ID 52U
#define XPS_USB0_INT_ID 53U
#define XPS_GEM0_INT_ID 54U
#define XPS_GEM0_WAKE_INT_ID 55U
#define XPS_SDIO0_INT_ID 56U
#define XPS_I2C0_INT_ID 57U
#define XPS_SPI0_INT_ID 58U
#define XPS_UART0_INT_ID 59U
#define XPS_CAN0_INT_ID 60U
#define XPS_FPGA0_INT_ID 61U
#define XPS_FPGA1_INT_ID 62U
#define XPS_FPGA2_INT_ID 63U
#define XPS_FPGA3_INT_ID 64U
#define XPS_FPGA4_INT_ID 65U
#define XPS_FPGA5_INT_ID 66U
#define XPS_FPGA6_INT_ID 67U
#define XPS_FPGA7_INT_ID 68U
#define XPS_TTC1_0_INT_ID 69U
#define XPS_TTC1_1_INT_ID 70U
#define XPS_TTC1_2_INT_ID 71U
#define XPS_DMA4_INT_ID 72U
#define XPS_DMA5_INT_ID 73U
#define XPS_DMA6_INT_ID 74U
#define XPS_DMA7_INT_ID 75U
#define XPS_USB1_INT_ID 76U
#define XPS_GEM1_INT_ID 77U
#define XPS_GEM1_WAKE_INT_ID 78U
#define XPS_SDIO1_INT_ID 79U
#define XPS_I2C1_INT_ID 80U
#define XPS_SPI1_INT_ID 81U
#define XPS_UART1_INT_ID 82U
#define XPS_CAN1_INT_ID 83U
#define XPS_FPGA8_INT_ID 84U
#define XPS_FPGA9_INT_ID 85U
#define XPS_FPGA10_INT_ID 86U
#define XPS_FPGA11_INT_ID 87U
#define XPS_FPGA12_INT_ID 88U
#define XPS_FPGA13_INT_ID 89U
#define XPS_FPGA14_INT_ID 90U
#define XPS_FPGA15_INT_ID 91U
/* Private Peripheral Interrupts (PPI) */
#define XPS_GLOBAL_TMR_INT_ID 27U /* SCU Global Timer interrupt */
#define XPS_FIQ_INT_ID 28U /* FIQ from FPGA fabric */
#define XPS_SCU_TMR_INT_ID 29U /* SCU Private Timer interrupt */
#define XPS_SCU_WDT_INT_ID 30U /* SCU Private WDT interrupt */
#define XPS_IRQ_INT_ID 31U /* IRQ from FPGA fabric */
/* REDEFINES for TEST APP */
/* Definitions for UART */
#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID
#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID
#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID
#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID
#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID
#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID
#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID
#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID
#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID
#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID
#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID
#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID
#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID
#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID
#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID
#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
#define XPAR_PS7_TTC_0_INTR XPS_TTC0_0_INT_ID
#define XPAR_PS7_TTC_1_INTR XPS_TTC0_1_INT_ID
#define XPAR_PS7_TTC_2_INTR XPS_TTC0_2_INT_ID
#define XPAR_PS7_TTC_3_INTR XPS_TTC1_0_INT_ID
#define XPAR_PS7_TTC_4_INTR XPS_TTC1_1_INT_ID
#define XPAR_PS7_TTC_5_INTR XPS_TTC1_2_INT_ID
#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
/* For backwards compatibilty */
#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
#define XPAR_SCUTIMER_DEVICE_ID 0U
#define XPAR_SCUWDT_DEVICE_ID 0U
#ifdef __cplusplus
}
#endif
#endif /* protection macro */

1
src/APP/Aufgabe2/ps7/core0/cfg/xparameters_ps.h Symbolic link
View File

@@ -0,0 +1 @@
../../../../Aufgabe1/ps7/core0/cfg/xparameters_ps.h

291
src/APP/Aufgabe2/ps7/core0/linker/lscript.ld
View File

@@ -1,291 +0,0 @@
/*******************************************************************/
/* */
/* This file is automatically generated by linker script generator.*/
/* */
/* Version: */
/* */
/* Copyright (c) 2010-2016 Xilinx, Inc. All rights reserved. */
/* */
/* Description : Cortex-A9 Linker Script */
/* */
/*******************************************************************/
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
/* Define Memories in the system */
MEMORY
{
axi_bram_ctrl_0_Mem0 : ORIGIN = 0x40000000, LENGTH = 0x2000
ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x3FF00000
ps7_qspi_linear_0 : ORIGIN = 0xFC000000, LENGTH = 0x2000000
ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000
ps7_ram_1 : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00
ps7_ddr_core_0 : ORIGIN = 0x100000, LENGTH = 0x700000
ps7_ddr_core_1 : ORIGIN = 0x800000, LENGTH = 0x800000
}
/* Specify the default entry point to the program */
ENTRY(_vector_table)
/* Define the sections, and where they are mapped in memory */
SECTIONS
{
.text : {
KEEP (*(.vectors))
*(.boot)
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
*(.plt)
*(.gnu_warning)
*(.gcc_execpt_table)
*(.glue_7)
*(.glue_7t)
*(.vfp11_veneer)
*(.ARM.extab)
*(.gnu.linkonce.armextab.*)
} > ps7_ddr_core_0
.init : {
KEEP (*(.init))
} > ps7_ddr_core_0
.fini : {
KEEP (*(.fini))
} > ps7_ddr_core_0
.rodata : {
__rodata_start = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
__rodata_end = .;
} > ps7_ddr_core_0
.rodata1 : {
__rodata1_start = .;
*(.rodata1)
*(.rodata1.*)
__rodata1_end = .;
} > ps7_ddr_core_0
.sdata2 : {
__sdata2_start = .;
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
__sdata2_end = .;
} > ps7_ddr_core_0
.sbss2 : {
__sbss2_start = .;
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
__sbss2_end = .;
} > ps7_ddr_core_0
.data : {
__data_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.jcr)
*(.got)
*(.got.plt)
__data_end = .;
} > ps7_ddr_core_0
.data1 : {
__data1_start = .;
*(.data1)
*(.data1.*)
__data1_end = .;
} > ps7_ddr_core_0
.got : {
*(.got)
} > ps7_ddr_core_0
.ctors : {
__CTOR_LIST__ = .;
___CTORS_LIST___ = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
___CTORS_END___ = .;
} > ps7_ddr_core_0
.dtors : {
__DTOR_LIST__ = .;
___DTORS_LIST___ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
___DTORS_END___ = .;
} > ps7_ddr_core_0
.fixup : {
__fixup_start = .;
*(.fixup)
__fixup_end = .;
} > ps7_ddr_core_0
.eh_frame : {
*(.eh_frame)
} > ps7_ddr_core_0
.eh_framehdr : {
__eh_framehdr_start = .;
*(.eh_framehdr)
__eh_framehdr_end = .;
} > ps7_ddr_core_0
.gcc_except_table : {
*(.gcc_except_table)
} > ps7_ddr_core_0
.mmu_tbl (ALIGN(16384)) : {
__mmu_tbl_start = .;
*(.mmu_tbl)
__mmu_tbl_end = .;
} > ps7_ddr_core_0
.ARM.exidx : {
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidix.*.*)
__exidx_end = .;
} > ps7_ddr_core_0
.preinit_array : {
__preinit_array_start = .;
KEEP (*(SORT(.preinit_array.*)))
KEEP (*(.preinit_array))
__preinit_array_end = .;
} > ps7_ddr_core_0
.init_array : {
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
} > ps7_ddr_core_0
.fini_array : {
__fini_array_start = .;
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array))
__fini_array_end = .;
} > ps7_ddr_core_0
.ARM.attributes : {
__ARM.attributes_start = .;
*(.ARM.attributes)
__ARM.attributes_end = .;
} > ps7_ddr_core_0
.sdata : {
__sdata_start = .;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
__sdata_end = .;
} > ps7_ddr_core_0
.sbss (NOLOAD) : {
__sbss_start = .;
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
__sbss_end = .;
} > ps7_ddr_core_0
.tdata : {
__tdata_start = .;
*(.tdata)
*(.tdata.*)
*(.gnu.linkonce.td.*)
__tdata_end = .;
} > ps7_ddr_core_0
.tbss : {
__tbss_start = .;
*(.tbss)
*(.tbss.*)
*(.gnu.linkonce.tb.*)
__tbss_end = .;
} > ps7_ddr_core_0
.bss (NOLOAD) : {
__bss_start = .;
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
__bss_end = .;
} > ps7_ddr_core_0
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
/* Generate Stack and Heap definitions */
.heap (NOLOAD) : {
. = ALIGN(16);
_heap = .;
HeapBase = .;
_heap_start = .;
. += _HEAP_SIZE;
_heap_end = .;
HeapLimit = .;
} > ps7_ddr_core_0
.stack (NOLOAD) : {
. = ALIGN(16);
_stack_end = .;
. += _STACK_SIZE;
. = ALIGN(16);
_stack = .;
__stack = _stack;
. = ALIGN(16);
_irq_stack_end = .;
. += _IRQ_STACK_SIZE;
. = ALIGN(16);
__irq_stack = .;
_supervisor_stack_end = .;
. += _SUPERVISOR_STACK_SIZE;
. = ALIGN(16);
__supervisor_stack = .;
_abort_stack_end = .;
. += _ABORT_STACK_SIZE;
. = ALIGN(16);
__abort_stack = .;
_fiq_stack_end = .;
. += _FIQ_STACK_SIZE;
. = ALIGN(16);
__fiq_stack = .;
_undef_stack_end = .;
. += _UNDEF_STACK_SIZE;
. = ALIGN(16);
__undef_stack = .;
} > ps7_ddr_core_0
_end = .;
}

1
src/APP/Aufgabe2/ps7/core0/linker/lscript.ld Symbolic link
View File

@@ -0,0 +1 @@
../../../../Aufgabe1/ps7/core0/linker/lscript.ld

1
src/APP/Aufgabe3/ps7/core0/build/config.mk
View File

@@ -1,6 +1,5 @@
#µController dependent flags
MCFLAGS =-mcpu=cortex-a9 -march=armv7-a -mthumb -mthumb-interwork -mfloat-abi=softfp -mfpu=neon
#Optimization
OPTIMIZE=-O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections

48
src/APP/Aufgabe3/ps7/core0/build/includes.mk
View File

@@ -1,48 +0,0 @@
INC += -I"$(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/cfg/"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Ports/ARM-Cortex-A/Generic/GNU/"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/ARM-Cortex-A/GNU/"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-Common"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Source"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-LIB"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/bsp/src/ipi"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/bsp/src/"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/bsp/src/$(ARCH)/"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_cpu_cortexa9/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_scugic/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_l2cachec/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_uartps/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_emacps/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_scuc/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_ttcps/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/cortexa9"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/cortexa9/gcc"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/common"
INC += -I"$(SRC_DIR)/Xilinx/libsrc/ipipsu_v2_3/src/"
INC += -I"$(SRC_DIR)/Modules/MMU"
INC += -I"$(SRC_DIR)/Xilinx/libsrc/ipipsu_v2_3/src/"
#scugic.h fix
INC += -I"$(SRC_DIR)/Xilinx/libsrc/scugic_v3_9/src/"
#uart includes
INC += -I"$(SRC_DIR)/Xilinx/libsrc/uartps_v3_6/src/"
#xttcps includes
INC += -I"$(SRC_DIR)/Xilinx/libsrc/ttcps_v3_5/src/"
#gpio includes
INC += -I"$(SRC_DIR)/Xilinx/libsrc/gpiops_v3_3/src/"

1
src/APP/Aufgabe3/ps7/core0/build/includes.mk Symbolic link
View File

@@ -0,0 +1 @@
../../../../Aufgabe1/ps7/core0/build/includes.mk

5
src/APP/Aufgabe3/ps7/core0/build/sources.mk
View File

@@ -8,7 +8,7 @@ SRC += $(SRC_DIR)/ucos_v1_42/ucos/bsp/src/$(ARCH)/asm_vectors.S
SRC += $(SRC_DIR)/ucos_v1_42/ucos/components/ucos_osii/src/bsp/$(ARCH)/ucos_osii_bsp.c
SRC += $(SRC_DIR)/ucos_v1_42/ucos/components/ucos_common/src/$(ARCH)/cpu_bsp.c
SRC += $(SRC_DIR)/Modules/MMU/mmu.c
SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/main.c
SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/app_hooks.c
@@ -42,9 +42,6 @@ SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-Common/Auth/auth.c
-include $(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Source/subdir.mk
#mmu
SRC += $(SRC_DIR)/Modules/MMU/mmu.c
#src for triple timer counter
SRC +=$(SRC_DIR)/Xilinx/libsrc/ttcps_v3_5/src/xttcps.c

216
src/APP/Aufgabe3/ps7/core0/cfg/cpu_cfg.h
View File

@@ -1,216 +0,0 @@
/*
*********************************************************************************************************
* uC/CPU
* CPU CONFIGURATION & PORT LAYER
*
* (c) Copyright 2004-2015; Micrium, Inc.; Weston, FL
*
* All rights reserved. Protected by international copyright laws.
*
* uC/CPU is provided in source form to registered licensees ONLY. It is
* illegal to distribute this source code to any third party unless you receive
* written permission by an authorized Micrium representative. Knowledge of
* the source code may NOT be used to develop a similar product.
*
* Please help us continue to provide the Embedded community with the finest
* software available. Your honesty is greatly appreciated.
*
* You can find our product's user manual, API reference, release notes and
* more information at https://doc.micrium.com.
* You can contact us at www.micrium.com.
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* CPU CONFIGURATION FILE
*
* TEMPLATE
*
* Filename : cpu_cfg.h
* Version : V1.30.02
* Programmer(s) : SR
* ITJ
* JBL
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* MODULE
*********************************************************************************************************
*/
#ifndef CPU_CFG_MODULE_PRESENT
#define CPU_CFG_MODULE_PRESENT
/*
*********************************************************************************************************
* CPU NAME CONFIGURATION
*
* Note(s) : (1) Configure CPU_CFG_NAME_EN to enable/disable CPU host name feature :
*
* (a) CPU host name storage
* (b) CPU host name API functions
*
* (2) Configure CPU_CFG_NAME_SIZE with the desired ASCII string size of the CPU host name,
* including the terminating NULL character.
*
* See also 'cpu_core.h GLOBAL VARIABLES Note #1'.
*********************************************************************************************************
*/
/* Configure CPU host name feature (see Note #1) : */
#define CPU_CFG_NAME_EN DEF_DISABLED
/* DEF_DISABLED CPU host name DISABLED */
/* DEF_ENABLED CPU host name ENABLED */
/* Configure CPU host name ASCII string size ... */
#define CPU_CFG_NAME_SIZE 16
/*
*********************************************************************************************************
* CPU TIMESTAMP CONFIGURATION
*
* Note(s) : (1) Configure CPU_CFG_TS_xx_EN to enable/disable CPU timestamp features :
*
* (a) CPU_CFG_TS_32_EN enable/disable 32-bit CPU timestamp feature
* (b) CPU_CFG_TS_64_EN enable/disable 64-bit CPU timestamp feature
*
* (2) (a) Configure CPU_CFG_TS_TMR_SIZE with the CPU timestamp timer's word size :
*
* CPU_WORD_SIZE_08 8-bit word size
* CPU_WORD_SIZE_16 16-bit word size
* CPU_WORD_SIZE_32 32-bit word size
* CPU_WORD_SIZE_64 64-bit word size
*
* (b) If the size of the CPU timestamp timer is not a binary multiple of 8-bit octets
* (e.g. 20-bits or even 24-bits), then the next lower, binary-multiple octet word
* size SHOULD be configured (e.g. to 16-bits). However, the minimum supported word
* size for CPU timestamp timers is 8-bits.
*
* See also 'cpu_core.h FUNCTION PROTOTYPES CPU_TS_TmrRd() Note #2a'.
*********************************************************************************************************
*/
/* Configure CPU timestamp features (see Note #1) : */
#define CPU_CFG_TS_32_EN DEF_ENABLED
#define CPU_CFG_TS_64_EN DEF_ENABLED
/* DEF_DISABLED CPU timestamps DISABLED */
/* DEF_ENABLED CPU timestamps ENABLED */
/* Configure CPU timestamp timer word size ... */
/* ... (see Note #2) : */
#define CPU_CFG_TS_TMR_SIZE CPU_WORD_SIZE_64
/*
*********************************************************************************************************
* CPU INTERRUPTS DISABLED TIME MEASUREMENT CONFIGURATION
*
* Note(s) : (1) (a) Configure CPU_CFG_INT_DIS_MEAS_EN to enable/disable measuring CPU's interrupts
* disabled time :
*
* (a) Enabled, if CPU_CFG_INT_DIS_MEAS_EN #define'd in 'cpu_cfg.h'
*
* (b) Disabled, if CPU_CFG_INT_DIS_MEAS_EN NOT #define'd in 'cpu_cfg.h'
*
* See also 'cpu_core.h FUNCTION PROTOTYPES Note #1'.
*
* (b) Configure CPU_CFG_INT_DIS_MEAS_OVRHD_NBR with the number of times to measure &
* average the interrupts disabled time measurements overhead.
*
* See also 'cpu_core.c CPU_IntDisMeasInit() Note #3a'.
*********************************************************************************************************
*/
#if 0 /* Configure CPU interrupts disabled time ... */
#define CPU_CFG_INT_DIS_MEAS_EN /* ... measurements feature (see Note #1a). */
#endif
/* Configure number of interrupts disabled overhead ... */
#define CPU_CFG_INT_DIS_MEAS_OVRHD_NBR 1u /* ... time measurements (see Note #1b). */
/*
*********************************************************************************************************
* CPU COUNT ZEROS CONFIGURATION
*
* Note(s) : (1) (a) Configure CPU_CFG_LEAD_ZEROS_ASM_PRESENT to define count leading zeros bits
* function(s) in :
*
* (1) 'cpu_a.asm', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable assembly-optimized function(s)
*
* (2) 'cpu_core.c', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT NOT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
*
* (b) Configure CPU_CFG_TRAIL_ZEROS_ASM_PRESENT to define count trailing zeros bits
* function(s) in :
*
* (1) 'cpu_a.asm', if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable assembly-optimized function(s)
*
* (2) 'cpu_core.c', if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT NOT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
*********************************************************************************************************
*/
#if 0 /* Configure CPU count leading zeros bits ... */
#define CPU_CFG_LEAD_ZEROS_ASM_PRESENT /* ... assembly-version (see Note #1a). */
#endif
#if 0 /* Configure CPU count trailing zeros bits ... */
#define CPU_CFG_TRAIL_ZEROS_ASM_PRESENT /* ... assembly-version (see Note #1b). */
#endif
/*
*********************************************************************************************************
* CPU ENDIAN TYPE OVERRIDE
*
* Note(s) : (1) Configure CPU_CFG_ENDIAN_TYPE to override the default CPU endian type defined in cpu.h.
*
* (a) CPU_ENDIAN_TYPE_BIG Big- endian word order (CPU words' most significant
* octet @ lowest memory address)
* (b) CPU_ENDIAN_TYPE_LITTLE Little-endian word order (CPU words' least significant
* octet @ lowest memory address)
*
* (2) Defining CPU_CFG_ENDIAN_TYPE here is only valid for supported bi-endian architectures.
* See 'cpu.h CPU WORD CONFIGURATION Note #3' for details
*********************************************************************************************************
*/
#if 0
#define CPU_CFG_ENDIAN_TYPE CPU_ENDIAN_TYPE_BIG /* Defines CPU data word-memory order (see Note #2). */
#endif
/*
*********************************************************************************************************
* CACHE MANAGEMENT
*
* Note(s) : (1) Configure CPU_CFG_CACHE_MGMT_EN to enable the cache managment API.
*
* (2) Defining CPU_CFG_CACHE_MGMT_EN to DEF_ENABLED only enable the cache management function.
* Cache are assumed to be configured and enabled by the time CPU_init() is called.
*********************************************************************************************************
*/
#define CPU_CFG_CACHE_MGMT_EN DEF_DISABLED
/*
*********************************************************************************************************
* MODULE END
*********************************************************************************************************
*/
#endif /* End of CPU cfg module include. */
#define CPU_CACHE_CFG_L2C310_BASE_ADDR 0xF8F02000

1
src/APP/Aufgabe3/ps7/core0/cfg/cpu_cfg.h Symbolic link
View File

@@ -0,0 +1 @@
../../../../Aufgabe1/ps7/core0/cfg/cpu_cfg.h

171
src/APP/Aufgabe3/ps7/core0/cfg/lib_cfg.h
View File

@@ -1,171 +0,0 @@
/*
*********************************************************************************************************
* EXAMPLE CODE
*
* This file is provided as an example on how to use Micrium products.
*
* Please feel free to use any application code labeled as 'EXAMPLE CODE' in
* your application products. Example code may be used as is, in whole or in
* part, or may be used as a reference only. This file can be modified as
* required to meet the end-product requirements.
*
* Please help us continue to provide the Embedded community with the finest
* software available. Your honesty is greatly appreciated.
*
* You can find information about uC/LIB by visiting doc.micrium.com.
* You can contact us at: http://www.micrium.com
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* CUSTOM LIBRARY CONFIGURATION FILE
*
* TEMPLATE
*
* Filename : lib_cfg.h
* Version : V1.38.01.00
* Programmer(s) : FBJ
* JFD
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* MODULE
*********************************************************************************************************
*/
#ifndef LIB_CFG_MODULE_PRESENT
#define LIB_CFG_MODULE_PRESENT
/*
*********************************************************************************************************
*********************************************************************************************************
* MEMORY LIBRARY CONFIGURATION
*********************************************************************************************************
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* MEMORY LIBRARY ARGUMENT CHECK CONFIGURATION
*
* Note(s) : (1) Configure LIB_MEM_CFG_ARG_CHK_EXT_EN to enable/disable the memory library suite external
* argument check feature :
*
* (a) When ENABLED, arguments received from any port interface provided by the developer
* or application are checked/validated.
*
* (b) When DISABLED, NO arguments received from any port interface provided by the developer
* or application are checked/validated.
*********************************************************************************************************
*/
/* External argument check. */
/* Indicates if arguments received from any port ... */
/* ... interface provided by the developer or ... */
/* ... application are checked/validated. */
#define LIB_MEM_CFG_ARG_CHK_EXT_EN DEF_DISABLED
/*
*********************************************************************************************************
* MEMORY LIBRARY ASSEMBLY OPTIMIZATION CONFIGURATION
*
* Note(s) : (1) Configure LIB_MEM_CFG_OPTIMIZE_ASM_EN to enable/disable assembly-optimized memory function(s).
*********************************************************************************************************
*/
/* Assembly-optimized function(s). */
/* Enable/disable assembly-optimized memory ... */
/* ... function(s). [see Note #1] */
#define LIB_MEM_CFG_OPTIMIZE_ASM_EN DEF_DISABLED
/*
*********************************************************************************************************
* MEMORY ALLOCATION CONFIGURATION
*
* Note(s) : (1) Configure LIB_MEM_CFG_DBG_INFO_EN to enable/disable memory allocation usage tracking
* that associates a name with each segment or dynamic pool allocated.
*
* (2) (a) Configure LIB_MEM_CFG_HEAP_SIZE with the desired size of heap memory (in octets).
*
* (b) Configure LIB_MEM_CFG_HEAP_BASE_ADDR to specify a base address for heap memory :
*
* (1) Heap initialized to specified application memory, if LIB_MEM_CFG_HEAP_BASE_ADDR
* #define'd in 'lib_cfg.h';
* CANNOT #define to address 0x0
*
* (2) Heap declared to Mem_Heap[] in 'lib_mem.c', if LIB_MEM_CFG_HEAP_BASE_ADDR
* NOT #define'd in 'lib_cfg.h'
*********************************************************************************************************
*/
/* Allocation debugging information. */
/* Enable/disable allocation of debug information ... */
/* ... associated to each memory allocation. */
#define LIB_MEM_CFG_DBG_INFO_EN DEF_DISABLED
/* Heap memory size (in bytes). */
/* Configure the desired size of the heap memory. ... */
/* ... Set to 0 to disable heap allocation features. */
#define LIB_MEM_CFG_HEAP_SIZE 64*1024
/* Heap memory padding alignment (in bytes). */
/* Configure the desired size of padding alignment ... */
/* ... of each buffer allocated from the heap. */
#define LIB_MEM_CFG_HEAP_PADDING_ALIGN LIB_MEM_PADDING_ALIGN_NONE
#if 0 /* Remove this to have heap alloc at specified addr. */
#define LIB_MEM_CFG_HEAP_BASE_ADDR 0
#endif
/*
*********************************************************************************************************
*********************************************************************************************************
* STRING LIBRARY CONFIGURATION
*********************************************************************************************************
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* STRING FLOATING POINT CONFIGURATION
*
* Note(s) : (1) Configure LIB_STR_CFG_FP_EN to enable/disable floating point string function(s).
*
* (2) Configure LIB_STR_CFG_FP_MAX_NBR_DIG_SIG to configure the maximum number of significant
* digits to calculate &/or display for floating point string function(s).
*
* See also 'lib_str.h STRING FLOATING POINT DEFINES Note #1'.
*********************************************************************************************************
*/
/* Floating point feature(s). */
/* Enable/disable floating point to string functions. */
#define LIB_STR_CFG_FP_EN DEF_DISABLED
/* Floating point number of significant digits. */
/* Configure the maximum number of significant ... */
/* ... digits to calculate &/or display for ... */
/* ... floating point string function(s). */
#define LIB_STR_CFG_FP_MAX_NBR_DIG_SIG LIB_STR_FP_MAX_NBR_DIG_SIG_DFLT
/*
*********************************************************************************************************
* MODULE END
*********************************************************************************************************
*/
#endif /* End of lib cfg module include. */

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src/APP/Aufgabe3/ps7/core0/cfg/lib_cfg.h Symbolic link
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src/APP/Aufgabe3/ps7/core0/cfg/mmu_cfg.h
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/*
* mmu_cfg.h
*
* Created on: 25.04.2018
* Author: kaige
*/
#ifndef SRC_APP_LWIPREWORK_PS7_CORE0_CFG_MMU_CFG_H_
#define SRC_APP_LWIPREWORK_PS7_CORE0_CFG_MMU_CFG_H_
#include "mmu.h"
/*------------------------------------------------------------------------------------------------*/
/*!
* \brief FIRST LEVEL TRANSLATION TABLE (FTT)
*
* \ingroup PAR_CPU_MMU
*
* This variable represents the first level translation table. Each entry within
* the table represents the configuration of a 1MB memory segment. If a memory
* portion below 1MB must be accessed, the entry represents a pointer to the
* linked coarse page table, which contains the information of that 1MB in detail.
*
* \note This table MUST be aligned at 16kB boundary.
*/
/*------------------------------------------------------------------------------------------------*/
const PAR_MEM_REGION_T PARMemTbl_Core[] = {
/* +-------------------------------------------------------------------------------------------+
* | virtual | physical | size | owner | permissions | HID Field |
* +-----------+-----------+---------------+------------------+-----------------+--------------+*/
// First 1MB is marked as non-cacheable/non-bufferable (contains 3x 64KB SRAM @ address 0x00000000
{ 0x00000000, 0x00000000, MMU_SIZE_1MB, PAR_AP_PRW__URW_, PAR_HID_TEX_CB_CACHED_MEMORY | PAR_HID_CACHE_INNER_CB | PAR_HID_CACHE_OUTER_CB },
// DDR Memory is marked as normal (only 512MB for now)
{ 0x00100000, 0x00100000, MMU_SIZE_16MB, PAR_AP_PRW__URW_, PAR_HID_TEX_CB_CACHED_MEMORY | PAR_HID_CACHE_INNER___ | PAR_HID_CACHE_OUTER___ },
// Device section
{ 0xE0000000, 0xE0000000, MMU_SIZE_512MB-MMU_SIZE_1MB, PAR_AP_PRW__URW_, PAR_HID_EXCLUSIVE_SYS_DEVICE },
// Upper 1MB section contains 1x 64KB SRAM @ address 0xFFFF0000
{ 0xFFF00000, 0xFFF00000, MMU_SIZE_1MB, PAR_AP_PRW__URW_, PAR_HID_TEX_CB_OUT_IN_NON_CACHABLE }
};
#endif /* SRC_APP_LWIPREWORK_PS7_CORE0_CFG_MMU_CFG_H_ */

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src/APP/Aufgabe3/ps7/core0/cfg/mmu_cfg.h Symbolic link
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src/APP/Aufgabe3/ps7/core0/cfg/os_cfg.h
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/*
*********************************************************************************************************
* uC/OS-II
* The Real-Time Kernel
* uC/OS-II Configuration File for V2.9x
*
* (c) Copyright 2005-2014, Micrium, Weston, FL
* All Rights Reserved
*
*
* File : OS_CFG.H
* By : Jean J. Labrosse
* Version : V2.92.11
*
* LICENSING TERMS:
* ---------------
* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research.
* If you plan on using uC/OS-II in a commercial product you need to contact Micrium to properly license
* its use in your product. We provide ALL the source code for your convenience and to help you experience
* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a
* licensing fee.
*********************************************************************************************************
*/
#ifndef OS_CFG_H
#define OS_CFG_H
/* ---------------------- MISCELLANEOUS ----------------------- */
#define OS_APP_HOOKS_EN 1u /* Application-defined hooks are called from the uC/OS-II hooks */
#define OS_ARG_CHK_EN 0u /* Enable (1) or Disable (0) argument checking */
#define OS_CPU_HOOKS_EN 1u /* uC/OS-II hooks are found in the processor port files */
#define OS_DEBUG_EN 1u /* Enable(1) debug variables */
#define OS_EVENT_MULTI_EN 1u /* Include code for OSEventPendMulti() */
#define OS_EVENT_NAME_EN 1u /* Enable names for Sem, Mutex, Mbox and Q */
#define OS_LOWEST_PRIO 63u /* Defines the lowest priority that can be assigned ... */
/* ... MUST NEVER be higher than 254! */
#define OS_MAX_EVENTS 20u /* Max. number of event control blocks in your application */
#define OS_MAX_FLAGS 5u /* Max. number of Event Flag Groups in your application */
#define OS_MAX_MEM_PART 5u /* Max. number of memory partitions */
#define OS_MAX_QS 6u /* Max. number of queue control blocks in your application */
#define OS_MAX_TASKS 20u /* Max. number of tasks in your application, MUST be >= 2 */
#define OS_SCHED_LOCK_EN 1u /* Include code for OSSchedLock() and OSSchedUnlock() */
#define OS_TICK_STEP_EN 1u /* Enable tick stepping feature for uC/OS-View */
#define OS_TICKS_PER_SEC 1000u /* Set the number of ticks in one second */
#define OS_TLS_TBL_SIZE 0u /* Size of Thread-Local Storage Table */
/* --------------------- TASK STACK SIZE ---------------------- */
#define OS_TASK_TMR_STK_SIZE 128u /* Timer task stack size (# of OS_STK wide entries) */
#define OS_TASK_STAT_STK_SIZE 128u /* Statistics task stack size (# of OS_STK wide entries) */
#define OS_TASK_IDLE_STK_SIZE 128u /* Idle task stack size (# of OS_STK wide entries) */
/* --------------------- TASK MANAGEMENT ---------------------- */
#define OS_TASK_CHANGE_PRIO_EN 1u /* Include code for OSTaskChangePrio() */
#define OS_TASK_CREATE_EN 1u /* Include code for OSTaskCreate() */
#define OS_TASK_CREATE_EXT_EN 1u /* Include code for OSTaskCreateExt() */
#define OS_TASK_DEL_EN 1u /* Include code for OSTaskDel() */
#define OS_TASK_NAME_EN 1u /* Enable task names */
#define OS_TASK_PROFILE_EN 1u /* Include variables in OS_TCB for profiling */
#define OS_TASK_QUERY_EN 1u /* Include code for OSTaskQuery() */
#define OS_TASK_REG_TBL_SIZE 1u /* Size of task variables array (#of INT32U entries) */
#define OS_TASK_STAT_EN 1u /* Enable (1) or Disable(0) the statistics task */
#define OS_TASK_STAT_STK_CHK_EN 1u /* Check task stacks from statistic task */
#define OS_TASK_SUSPEND_EN 1u /* Include code for OSTaskSuspend() and OSTaskResume() */
#define OS_TASK_SW_HOOK_EN 1u /* Include code for OSTaskSwHook() */
/* ----------------------- EVENT FLAGS ------------------------ */
#define OS_FLAG_EN 1u /* Enable (1) or Disable (0) code generation for EVENT FLAGS */
#define OS_FLAG_ACCEPT_EN 1u /* Include code for OSFlagAccept() */
#define OS_FLAG_DEL_EN 1u /* Include code for OSFlagDel() */
#define OS_FLAG_NAME_EN 1u /* Enable names for event flag group */
#define OS_FLAG_QUERY_EN 1u /* Include code for OSFlagQuery() */
#define OS_FLAG_WAIT_CLR_EN 1u /* Include code for Wait on Clear EVENT FLAGS */
#define OS_FLAGS_NBITS 16u /* Size in #bits of OS_FLAGS data type (8, 16 or 32) */
/* -------------------- MESSAGE MAILBOXES --------------------- */
#define OS_MBOX_EN 1u /* Enable (1) or Disable (0) code generation for MAILBOXES */
#define OS_MBOX_ACCEPT_EN 1u /* Include code for OSMboxAccept() */
#define OS_MBOX_DEL_EN 1u /* Include code for OSMboxDel() */
#define OS_MBOX_PEND_ABORT_EN 1u /* Include code for OSMboxPendAbort() */
#define OS_MBOX_POST_EN 1u /* Include code for OSMboxPost() */
#define OS_MBOX_POST_OPT_EN 1u /* Include code for OSMboxPostOpt() */
#define OS_MBOX_QUERY_EN 1u /* Include code for OSMboxQuery() */
/* --------------------- MEMORY MANAGEMENT -------------------- */
#define OS_MEM_EN 1u /* Enable (1) or Disable (0) code generation for MEMORY MANAGER */
#define OS_MEM_NAME_EN 1u /* Enable memory partition names */
#define OS_MEM_QUERY_EN 1u /* Include code for OSMemQuery() */
/* ---------------- MUTUAL EXCLUSION SEMAPHORES --------------- */
#define OS_MUTEX_EN 1u /* Enable (1) or Disable (0) code generation for MUTEX */
#define OS_MUTEX_ACCEPT_EN 1u /* Include code for OSMutexAccept() */
#define OS_MUTEX_DEL_EN 1u /* Include code for OSMutexDel() */
#define OS_MUTEX_QUERY_EN 1u /* Include code for OSMutexQuery() */
/* ---------------------- MESSAGE QUEUES ---------------------- */
#define OS_Q_EN 1u /* Enable (1) or Disable (0) code generation for QUEUES */
#define OS_Q_ACCEPT_EN 1u /* Include code for OSQAccept() */
#define OS_Q_DEL_EN 1u /* Include code for OSQDel() */
#define OS_Q_FLUSH_EN 1u /* Include code for OSQFlush() */
#define OS_Q_PEND_ABORT_EN 1u /* Include code for OSQPendAbort() */
#define OS_Q_POST_EN 1u /* Include code for OSQPost() */
#define OS_Q_POST_FRONT_EN 1u /* Include code for OSQPostFront() */
#define OS_Q_POST_OPT_EN 1u /* Include code for OSQPostOpt() */
#define OS_Q_QUERY_EN 1u /* Include code for OSQQuery() */
/* ------------------------ SEMAPHORES ------------------------ */
#define OS_SEM_EN 1u /* Enable (1) or Disable (0) code generation for SEMAPHORES */
#define OS_SEM_ACCEPT_EN 1u /* Include code for OSSemAccept() */
#define OS_SEM_DEL_EN 1u /* Include code for OSSemDel() */
#define OS_SEM_PEND_ABORT_EN 1u /* Include code for OSSemPendAbort() */
#define OS_SEM_QUERY_EN 1u /* Include code for OSSemQuery() */
#define OS_SEM_SET_EN 1u /* Include code for OSSemSet() */
/* --------------------- TIME MANAGEMENT ---------------------- */
#define OS_TIME_DLY_HMSM_EN 1u /* Include code for OSTimeDlyHMSM() */
#define OS_TIME_DLY_RESUME_EN 1u /* Include code for OSTimeDlyResume() */
#define OS_TIME_GET_SET_EN 1u /* Include code for OSTimeGet() and OSTimeSet() */
#define OS_TIME_TICK_HOOK_EN 1u /* Include code for OSTimeTickHook() */
/* --------------------- TIMER MANAGEMENT --------------------- */
#define OS_TMR_EN 0u /* Enable (1) or Disable (0) code generation for TIMERS */
#define OS_TMR_CFG_MAX 16u /* Maximum number of timers */
#define OS_TMR_CFG_NAME_EN 1u /* Determine timer names */
#define OS_TMR_CFG_WHEEL_SIZE 7u /* Size of timer wheel (#Spokes) */
#define OS_TMR_CFG_TICKS_PER_SEC 10u /* Rate at which timer management task runs (Hz) */
#endif

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src/APP/Aufgabe3/ps7/core0/cfg/os_cfg.h Symbolic link
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src/APP/Aufgabe3/ps7/core0/cfg/xparameters.h
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/******************************************************************/
/* Definition for CPU ID */
#define XPAR_CPU_ID 0
/* Definitions for peripheral PS7_CORTEXA9_0 */
#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
#define XPAR_PS7_CORTEXA9_1_CPU_CLK_FREQ_HZ XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ
/******************************************************************/
/* Canonical definitions for peripheral PS7_CORTEXA9_0 */
#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
#define XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
/******************************************************************/
#undef DEF_DISABLED
#undef DEF_ENABLED
#define DEF_ENABLED 1
#define DEF_DISABLED 0
#include "xparameters_ps.h"
/******************************************************************/
/* Definitions for driver BRAM */
#define XPAR_XBRAM_NUM_INSTANCES 1
/* Definitions for peripheral AXI_BRAM_CTRL_0 */
#define XPAR_AXI_BRAM_CTRL_0_DEVICE_ID 0
#define XPAR_AXI_BRAM_CTRL_0_DATA_WIDTH 32
#define XPAR_AXI_BRAM_CTRL_0_ECC 0
#define XPAR_AXI_BRAM_CTRL_0_FAULT_INJECT 0
#define XPAR_AXI_BRAM_CTRL_0_CE_FAILING_REGISTERS 0
#define XPAR_AXI_BRAM_CTRL_0_UE_FAILING_REGISTERS 0
#define XPAR_AXI_BRAM_CTRL_0_ECC_STATUS_REGISTERS 0
#define XPAR_AXI_BRAM_CTRL_0_CE_COUNTER_WIDTH 0
#define XPAR_AXI_BRAM_CTRL_0_ECC_ONOFF_REGISTER 0
#define XPAR_AXI_BRAM_CTRL_0_ECC_ONOFF_RESET_VALUE 0
#define XPAR_AXI_BRAM_CTRL_0_WRITE_ACCESS 0
#define XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR 0x40000000
#define XPAR_AXI_BRAM_CTRL_0_S_AXI_HIGHADDR 0x40001FFF
#define XPAR_AXI_BRAM_CTRL_0_S_AXI_CTRL_BASEADDR 0xFFFFFFFF
#define XPAR_AXI_BRAM_CTRL_0_S_AXI_CTRL_HIGHADDR 0xFFFFFFFF
/******************************************************************/
/* Canonical definitions for peripheral AXI_BRAM_CTRL_0 */
#define XPAR_BRAM_0_DEVICE_ID XPAR_AXI_BRAM_CTRL_0_DEVICE_ID
#define XPAR_BRAM_0_DATA_WIDTH 32
#define XPAR_BRAM_0_ECC 0
#define XPAR_BRAM_0_FAULT_INJECT 0
#define XPAR_BRAM_0_CE_FAILING_REGISTERS 0
#define XPAR_BRAM_0_UE_FAILING_REGISTERS 0
#define XPAR_BRAM_0_ECC_STATUS_REGISTERS 0
#define XPAR_BRAM_0_CE_COUNTER_WIDTH 0
#define XPAR_BRAM_0_ECC_ONOFF_REGISTER 0
#define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 0
#define XPAR_BRAM_0_WRITE_ACCESS 0
#define XPAR_BRAM_0_BASEADDR 0x40000000
#define XPAR_BRAM_0_HIGHADDR 0x40001FFF
/******************************************************************/
/* Definitions for peripheral PS7_DDR_0 */
#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
/******************************************************************/
/* Definitions for driver DEVCFG */
#define XPAR_XDCFG_NUM_INSTANCES 1
/* Definitions for peripheral PS7_DEV_CFG_0 */
#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0
#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000
#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FF
/******************************************************************/
/* Canonical definitions for peripheral PS7_DEV_CFG_0 */
#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
#define XPAR_XDCFG_0_BASEADDR 0xF8007000
#define XPAR_XDCFG_0_HIGHADDR 0xF80070FF
/******************************************************************/
/* Definitions for driver DMAPS */
#define XPAR_XDMAPS_NUM_INSTANCES 2
/* Definitions for peripheral PS7_DMA_NS */
#define XPAR_PS7_DMA_NS_DEVICE_ID 0
#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF
/* Definitions for peripheral PS7_DMA_S */
#define XPAR_PS7_DMA_S_DEVICE_ID 1
#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF
/******************************************************************/
/* Canonical definitions for peripheral PS7_DMA_NS */
#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
#define XPAR_XDMAPS_0_BASEADDR 0xF8004000
#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF
/* Canonical definitions for peripheral PS7_DMA_S */
#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
#define XPAR_XDMAPS_1_BASEADDR 0xF8003000
#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF
/******************************************************************/
/* Definitions for peripheral PS7_AFI_0 */
#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
/* Definitions for peripheral PS7_AFI_1 */
#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000
#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF
/* Definitions for peripheral PS7_AFI_2 */
#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000
#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF
/* Definitions for peripheral PS7_AFI_3 */
#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000
#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
/* Definitions for peripheral PS7_DDRC_0 */
#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
/* Definitions for peripheral PS7_GLOBALTIMER_0 */
#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200
#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF
/* Definitions for peripheral PS7_GPV_0 */
#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000
#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF
/* Definitions for peripheral PS7_INTC_DIST_0 */
#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000
#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF
/* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
/* Definitions for peripheral PS7_OCMC_0 */
#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000
#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF
/* Definitions for peripheral PS7_PL310_0 */
#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000
#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF
/* Definitions for peripheral PS7_PMU_0 */
#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000
#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF
#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000
#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF
/* Definitions for peripheral PS7_QSPI_LINEAR_0 */
#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFDFFFFFF
/* Definitions for peripheral PS7_RAM_0 */
#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
/* Definitions for peripheral PS7_RAM_1 */
#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000
#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
/* Definitions for peripheral PS7_SLCR_0 */
#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF
/******************************************************************/
/* Definitions for driver GPIO */
#define XPAR_XGPIO_NUM_INSTANCES 1
/* Definitions for peripheral AXI_GPIO_0 */
#define XPAR_AXI_GPIO_0_BASEADDR 0x41200000
#define XPAR_AXI_GPIO_0_HIGHADDR 0x4120FFFF
#define XPAR_AXI_GPIO_0_DEVICE_ID 0
#define XPAR_AXI_GPIO_0_INTERRUPT_PRESENT 0
#define XPAR_AXI_GPIO_0_IS_DUAL 0
/******************************************************************/
/* Canonical definitions for peripheral AXI_GPIO_0 */
#define XPAR_GPIO_0_BASEADDR 0x41200000
#define XPAR_GPIO_0_HIGHADDR 0x4120FFFF
#define XPAR_GPIO_0_DEVICE_ID XPAR_AXI_GPIO_0_DEVICE_ID
#define XPAR_GPIO_0_INTERRUPT_PRESENT 0
#define XPAR_GPIO_0_IS_DUAL 0
/******************************************************************/
/* Definitions for driver GPIOPS */
#define XPAR_XGPIOPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_GPIO_0 */
#define XPAR_PS7_GPIO_0_DEVICE_ID 0
#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
/******************************************************************/
/* Canonical definitions for peripheral PS7_GPIO_0 */
#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
/******************************************************************/
///* Definitions for driver IICPS */
//#define XPAR_XIICPS_NUM_INSTANCES 1
//
///* Definitions for peripheral PS7_I2C_0 */
//#define XPAR_PS7_I2C_0_DEVICE_ID 0
//#define XPAR_PS7_I2C_0_BASEADDR 0xE0004000
//#define XPAR_PS7_I2C_0_HIGHADDR 0xE0004FFF
//#define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 111111115
/******************************************************************/
/* Canonical definitions for peripheral PS7_I2C_0 */
#define XPAR_XIICPS_0_DEVICE_ID XPAR_PS7_I2C_0_DEVICE_ID
#define XPAR_XIICPS_0_BASEADDR 0xE0004000
#define XPAR_XIICPS_0_HIGHADDR 0xE0004FFF
#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 111111115
/******************************************************************/
/* Definitions for driver QSPIPS */
#define XPAR_XQSPIPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_QSPI_0 */
#define XPAR_PS7_QSPI_0_DEVICE_ID 0
#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000
#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000
#define XPAR_PS7_QSPI_0_QSPI_MODE 2
/******************************************************************/
/* Canonical definitions for peripheral PS7_QSPI_0 */
#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID
#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000
#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000
#define XPAR_XQSPIPS_0_QSPI_MODE 2
/******************************************************************/
/* Definitions for driver SCUWDT */
#define XPAR_XSCUWDT_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SCUWDT_0 */
#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF
/******************************************************************/
/* Canonical definitions for peripheral PS7_SCUWDT_0 */
#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
/******************************************************************/
/* Definitions for driver UCOS_EMACPS */
#define XPAR_UCOS_EMACPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_ETHERNET_0 */
#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0
#define XPAR_PS7_ETHERNET_0_BASEADDR 0x00000000
#define XPAR_PS7_ETHERNET_0_HIGHADDR 0x00000000
#define XPAR_PS7_ETHERNET_0_CLOCK_FREQ_HZ 0
/******************************************************************/
/* Canonical definitions for peripheral PS7_ETHERNET_0 */
#define XPAR_UCOS_EMACPS_0_NUM_INSTANCES 0
#define XPAR_UCOS_EMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID
#define XPAR_UCOS_EMACPS_0_BASEADDR 0x00000000
#define XPAR_UCOS_EMACPS_0_HIGHADDR 0x00000000
#define XPAR_UCOS_EMACPS_0_CLOCK_FREQ_HZ 0
/******************************************************************/
/* Definitions for driver UCOS_L2CACHEC */
#define XPAR_UCOS_L2CACHEC_NUM_INSTANCES 1
/* Definitions for peripheral PS7_L2CACHEC_0 */
#define XPAR_PS7_L2CACHEC_0_DEVICE_ID 0
#define XPAR_PS7_L2CACHEC_0_BASEADDR 0xF8F02000
#define XPAR_PS7_L2CACHEC_0_HIGHADDR 0xF8F02FFF
/******************************************************************/
/* Definitions for driver UCOS_SCUC */
#define XPAR_UCOS_L2CACHEC_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SCUC_0 */
#define XPAR_PS7_SCUC_0_DEVICE_ID 0
#define XPAR_PS7_SCUC_0_BASEADDR 0xF8F00000
#define XPAR_PS7_SCUC_0_HIGHADDR 0xF8F000FC
/******************************************************************/
/***Definitions for Core_nIRQ/nFIQ interrupts ****/
/* Definitions for driver UCOS_SCUGIC */
#define XPAR_XSCUGIC_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SCUGIC_0 */
#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0
#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100
#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FF
#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000
/******************************************************************/
/* Canonical definitions for peripheral PS7_SCUGIC_0 */
#define XPAR_SCUGIC_0_DEVICE_ID 0
#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100
#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FF
#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000
/******************************************************************/
/* Definitions for driver UCOS_SCUTIMER */
#define XPAR_UCOS_SCUC_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SCUTIMER_0 */
#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F
/******************************************************************/
/* Definitions for driver UCOS_SDPS */
#define XPAR_UCOS_SDPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SD_0 */
#define XPAR_PS7_SD_0_DEVICE_ID 0
#define XPAR_PS7_SD_0_BASEADDR 0xE0100000
#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
/******************************************************************/
/* Canonical definitions for peripheral PS7_SD_0 */
#define XPAR_UCOS_SDPS_0_NUM_INSTANCES 0
#define XPAR_UCOS_SDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID
#define XPAR_UCOS_SDPS_0_BASEADDR 0xE0100000
#define XPAR_UCOS_SDPS_0_HIGHADDR 0xE0100FFF
#define XPAR_UCOS_SDPS_0_SDIO_CLK_FREQ_HZ 50000000
/******************************************************************/
///* Definitions for driver UCOS_TTCPS */
//#define XPAR_UCOS_TTCPS_NUM_INSTANCES 3
//
///* Definitions for peripheral PS7_TTC_0 */
//#define XPAR_PS7_TTC_0_DEVICE_ID 0
//#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000
//#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115
//#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0
//#define XPAR_PS7_TTC_1_DEVICE_ID 1
//#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004
//#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115
//#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0
//#define XPAR_PS7_TTC_2_DEVICE_ID 2
//#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008
//#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115
//#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0
/******************************************************************/
/* Definitions for driver UCOS_UARTPS */
#define XPAR_UCOS_UARTPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_UART_1 */
#define XPAR_PS7_UART_1_DEVICE_ID 0
#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 50000000
#define XPAR_PS7_UART_1_HAS_MODEM 0
/******************************************************************/
/* Canonical definitions for peripheral PS7_UART_1 */
#define XPAR_UCOS_UARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
#define XPAR_UCOS_UARTPS_0_BASEADDR 0xE0001000
#define XPAR_UCOS_UARTPS_0_HIGHADDR 0xE0001FFF
#define XPAR_UCOS_UARTPS_0_UART_CLK_FREQ_HZ 50000000
#define XPAR_UCOS_UARTPS_0_HAS_MODEM 0
/******************************************************************/
/* Definitions for driver UCOS_USBPS */
#define XPAR_UCOS_USBPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_USB_0 */
#define XPAR_PS7_USB_0_DEVICE_ID 0
#define XPAR_PS7_USB_0_BASEADDR 0xE0002000
#define XPAR_PS7_USB_0_HIGHADDR 0xE0002FFF
/******************************************************************/
/* Canonical definitions for peripheral PS7_USB_0 */
#define XPAR_UCOS_USBPS_0_DEVICE_ID XPAR_PS7_USB_0_DEVICE_ID
#define XPAR_UCOS_USBPS_0_BASEADDR 0xE0002000
#define XPAR_UCOS_USBPS_0_HIGHADDR 0xE0002FFF
/******************************************************************/
/* Definitions for driver XADCPS */
#define XPAR_XADCPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_XADC_0 */
#define XPAR_PS7_XADC_0_DEVICE_ID 0
#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100
#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120
/******************************************************************/
/* Canonical definitions for peripheral PS7_XADC_0 */
#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
#define XPAR_XADCPS_0_BASEADDR 0xF8007100
#define XPAR_XADCPS_0_HIGHADDR 0xF8007120
/******************************************************************/
//UCOS STDOUT
#define UCOS_STDOUT_DRIVER UCOS_UART_PS7_UART
#define UCOS_STDOUT_DEVICE_ID 0
#define STDOUT_BASEADDRESS
//UCOS Ethernet
#define UCOS_ETHERNET_DRIVER UCOS_ETHERNET_EMACPS
//UCOS TASK PARAMETERS
#define UCOS_START_TASK_PRIO 5
#define UCOS_START_TASK_STACK_SIZE 784
#define UCOS_START_DEBUG_TRACE DEF_ENABLED
#define NET_TASK_CFG_RX_PRIO 30
#define NET_TASK_CFG_RX_STACK_SIZE 3072
#define NET_TASK_CFG_TXDEALLOC_PRIO 6
#define NET_TASK_CFG_TXDEALLOC_STACK_SIZE 2048
#define NET_TASK_CFG_TMR_PRIO 18
#define NET_TASK_CFG_TMR_STACK_SIZE 2048
#define HTTPc_OS_CFG_TASK_PRIO 20
#define HTTPc_OS_CFG_TASK_STK_SIZE 2048
#define UCOS_HTTPc_OS_CFG_TASK_DELAY 1
#define UCOS_HTTPc_OS_CFG_MSG_Q_SIZE 5
#define UCOS_HTTPc_OS_CFG_TIMEOUT 2000
#define UCOS_HTTPc_OS_CFG_INACTIVITY_TIMEOUT 30
#define UCOS_AMP_MASTER DEF_ENABLED
#define UCOS_CFG_INIT_CAN DEF_ENABLED
#define UCOS_CFG_INIT_NET DEF_ENABLED
#define UCOS_CFG_INIT_FS DEF_DISABLED
#define UCOS_CFG_INIT_OPENAMP DEF_DISABLED
#define UCOS_CFG_INIT_USBD DEF_DISABLED
#define UCOS_CFG_INIT_USBH DEF_DISABLED
#define UCOS_ETHERNET_ADDRESS "10.10.110.2"
#define UCOS_ETHERNET_GATEWAY "10.10.110.1"
#define UCOS_ETHERNET_SUBMASK "255.255.255.0"
#define UCOS_ETHERNET_DHCP DEF_ENABLED
#define UCOS_IF_RX_BUF_NBR 12
#define UCOS_IF_TX_LARGE_BUF_NBR 8
#define UCOS_IF_TX_SMALL_BUF_NBR 8
#define UCOS_IF_RX_DESC_NBR 0
#define UCOS_IF_TX_DESC_NBR 0
#define UCOS_IF_DEDIC_MEM_ADDR 0
#define UCOS_IF_DEDIC_MEM_SIZE 0
#define UCOS_IF_HW_ADDR "50:E5:49:E6:8D:28"
#define UCOS_PHY_BUS_ADDR 255
#define UCOS_PHY_BUS_MODE UCOS_NET_PHY_BUS_MODE_GMII
#define UCOS_PHY_TYPE UCOS_NET_PHY_TYPE_INT
#define UCOS_PHY_SPEED UCOS_NET_PHY_SPD_AUTO
#define UCOS_PHY_DUPLEX UCOS_NET_PHY_DUPLEX_AUTO
#define UCOS_USB_DRIVER UCOS_USB_NONE
#define UCOS_USB_DEVICE_ID 0
#define UCOS_USB_TYPE UCOS_USB_TYPE_DEVICE
#define UCOS_RAMDISK_EN DEF_DISABLED
#define UCOS_RAMDISK_SIZE 128
#define UCOS_RAMDISK_SECTOR_SIZE 512
#define UCOS_RAMDISK_BASE_ADDRESS 0
#define UCOS_SDCARD_EN DEF_DISABLED
#define XPAR_PS7_ETHERNET_0_INT_SOURCE 54
#define XPAR_PS7_SD_0_INT_SOURCE 56
#define XPAR_PS7_UART_1_INT_SOURCE 82
#define XPAR_PS7_USB_0_INT_SOURCE 53
#define UCOS_ZYNQ_CONFIG_MMU DEF_DISABLED
#define UCOS_ZYNQ_ENABLE_MMU DEF_DISABLED
#define UCOS_ZYNQ_CONFIG_CACHES DEF_DISABLED
#define UCOS_ZYNQ_ENABLE_CACHES DEF_DISABLED
#define UCOS_ZYNQ_ENABLE_OPTIMS DEF_DISABLED
#define ZYNQ_ENABLE_EARLY_L1_I_EN DEF_DISABLED
#define ZYNQ_ENABLE_EARLY_L1_D_EN DEF_DISABLED
#define UCOS_CPU_TYPE UCOS_CPU_TYPE_PS7
//Parameters added by Kai Gemlau
#define UCOS_SMP_ENABLE DEF_DISABLED
/******************************************************************/
/* Definitions for driver TTCPS */
#define XPAR_XTTCPS_NUM_INSTANCES 3U
/* Definitions for peripheral PS7_TTC_0 */
#define XPAR_PS7_TTC_0_DEVICE_ID 0U
#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000U
#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115U
#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0U
#define XPAR_PS7_TTC_1_DEVICE_ID 1U
#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004U
#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115U
#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0U
#define XPAR_PS7_TTC_2_DEVICE_ID 2U
#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008U
#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115U
#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0U
/******************************************************************/
/* Canonical definitions for peripheral PS7_TTC_0 */
#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PS7_TTC_0_DEVICE_ID
#define XPAR_XTTCPS_0_BASEADDR 0xF8001000U
#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 111111115U
#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0U
#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PS7_TTC_1_DEVICE_ID
#define XPAR_XTTCPS_1_BASEADDR 0xF8001004U
#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 111111115U
#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0U
#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PS7_TTC_2_DEVICE_ID
#define XPAR_XTTCPS_2_BASEADDR 0xF8001008U
#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 111111115U
#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0U
/******************************************************************/
/* Definitions for driver GPIOPS */
#define XPAR_XGPIOPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_GPIO_0 */
#define XPAR_PS7_GPIO_0_DEVICE_ID 0
#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
/******************************************************************/
/* Canonical definitions for peripheral PS7_GPIO_0 */
#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
/******************************************************************/
/* Definitions for driver IICPS */
#define XPAR_XIICPS_NUM_INSTANCES 2
/* Definitions for peripheral PS7_I2C_0 */
#define XPAR_PS7_I2C_0_DEVICE_ID 0
#define XPAR_PS7_I2C_0_BASEADDR 0xE0004000
#define XPAR_PS7_I2C_0_HIGHADDR 0xE0004FFF
#define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 111111115
/* Definitions for peripheral PS7_I2C_1 */
#define XPAR_PS7_I2C_1_DEVICE_ID 1
#define XPAR_PS7_I2C_1_BASEADDR 0xE0005000
#define XPAR_PS7_I2C_1_HIGHADDR 0xE0005FFF
#define XPAR_PS7_I2C_1_I2C_CLK_FREQ_HZ 111111115
/******************************************************************/
/* Canonical definitions for peripheral PS7_I2C_0 */
#define XPAR_XIICPS_0_DEVICE_ID XPAR_PS7_I2C_0_DEVICE_ID
#define XPAR_XIICPS_0_BASEADDR 0xE0004000
#define XPAR_XIICPS_0_HIGHADDR 0xE0004FFF
#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 111111115
/* Canonical definitions for peripheral PS7_I2C_1 */
#define XPAR_XIICPS_1_DEVICE_ID XPAR_PS7_I2C_1_DEVICE_ID
#define XPAR_XIICPS_1_BASEADDR 0xE0005000
#define XPAR_XIICPS_1_HIGHADDR 0xE0005FFF
#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 111111115
/******************************************************************/

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src/APP/Aufgabe3/ps7/core0/cfg/xparameters.h Symbolic link
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../../../../Aufgabe1/ps7/core0/cfg/xparameters.h

325
src/APP/Aufgabe3/ps7/core0/cfg/xparameters_ps.h
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/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xparameters_ps.h
*
* This file contains the address definitions for the hard peripherals
* attached to the ARM Cortex A9 core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------- -------- ---------------------------------------------------
* 1.00a ecm/sdm 02/01/10 Initial version
* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
* driver tcl
* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#ifndef _XPARAMETERS_PS_H_
#define _XPARAMETERS_PS_H_
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions *****************************/
/*
* This block contains constant declarations for the peripherals
* within the hardblock
*/
/* Canonical definitions for DDR MEMORY */
#define XPAR_DDR_MEM_BASEADDR 0x00000000U
#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
/* Canonical definitions for Interrupts */
#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID
#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID
#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID
#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID
#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID
#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID
#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR
#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR
/* Canonical definitions for DMAC */
/* Canonical definitions for WDT */
/* Canonical definitions for SLCR */
#define XPAR_XSLCR_NUM_INSTANCES 1U
#define XPAR_XSLCR_0_DEVICE_ID 0U
#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR
/* Canonical definitions for SCU GIC */
#define XPAR_SCUGIC_NUM_INSTANCES 1U
#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000100U)
#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
#define XPAR_SCUGIC_ACK_BEFORE 0U
/* Canonical definitions for Global Timer */
#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U
#define XPAR_GLOBAL_TMR_DEVICE_ID 0U
#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U)
#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID
/* Xilinx Parallel Flash Library (XilFlash) User Settings */
#define XPAR_AXI_EMC
#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
/*
* This block contains constant declarations for the peripherals
* within the hardblock. These have been put for bacwards compatibilty
*/
#define XPS_PERIPHERAL_BASEADDR 0xE0000000U
#define XPS_UART0_BASEADDR 0xE0000000U
#define XPS_UART1_BASEADDR 0xE0001000U
#define XPS_USB0_BASEADDR 0xE0002000U
#define XPS_USB1_BASEADDR 0xE0003000U
#define XPS_I2C0_BASEADDR 0xE0004000U
#define XPS_I2C1_BASEADDR 0xE0005000U
#define XPS_SPI0_BASEADDR 0xE0006000U
#define XPS_SPI1_BASEADDR 0xE0007000U
#define XPS_CAN0_BASEADDR 0xE0008000U
#define XPS_CAN1_BASEADDR 0xE0009000U
#define XPS_GPIO_BASEADDR 0xE000A000U
#define XPS_GEM0_BASEADDR 0xE000B000U
#define XPS_GEM1_BASEADDR 0xE000C000U
#define XPS_QSPI_BASEADDR 0xE000D000U
#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000U
#define XPS_SDIO0_BASEADDR 0xE0100000U
#define XPS_SDIO1_BASEADDR 0xE0101000U
#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U
#define XPS_NAND_BASEADDR 0xE1000000U
#define XPS_PARPORT0_BASEADDR 0xE2000000U
#define XPS_PARPORT1_BASEADDR 0xE4000000U
#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000U
#define XPS_SYS_CTRL_BASEADDR 0xF8000000U /* AKA SLCR */
#define XPS_TTC0_BASEADDR 0xF8001000U
#define XPS_TTC1_BASEADDR 0xF8002000U
#define XPS_DMAC0_SEC_BASEADDR 0xF8003000U
#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000U
#define XPS_WDT_BASEADDR 0xF8005000U
#define XPS_DDR_CTRL_BASEADDR 0xF8006000U
#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U
#define XPS_AFI0_BASEADDR 0xF8008000U
#define XPS_AFI1_BASEADDR 0xF8009000U
#define XPS_AFI2_BASEADDR 0xF800A000U
#define XPS_AFI3_BASEADDR 0xF800B000U
#define XPS_OCM_BASEADDR 0xF800C000U
#define XPS_EFUSE_BASEADDR 0xF800D000U
#define XPS_CORESIGHT_BASEADDR 0xF8800000U
#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U
#define XPS_SCU_PERIPH_BASE 0xF8F00000U
#define XPS_L2CC_BASEADDR 0xF8F02000U
#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U
#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U
#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U
#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U
#define XPS_PERIPH_APB_BASEADDR 0xF8000000U
/* Shared Peripheral Interrupts (SPI) */
#define XPS_CORE_PARITY0_INT_ID 32U
#define XPS_CORE_PARITY1_INT_ID 33U
#define XPS_L2CC_INT_ID 34U
#define XPS_OCMINTR_INT_ID 35U
#define XPS_ECC_INT_ID 36U
#define XPS_PMU0_INT_ID 37U
#define XPS_PMU1_INT_ID 38U
#define XPS_SYSMON_INT_ID 39U
#define XPS_DVC_INT_ID 40U
#define XPS_WDT_INT_ID 41U
#define XPS_TTC0_0_INT_ID 42U
#define XPS_TTC0_1_INT_ID 43U
#define XPS_TTC0_2_INT_ID 44U
#define XPS_DMA0_ABORT_INT_ID 45U
#define XPS_DMA0_INT_ID 46U
#define XPS_DMA1_INT_ID 47U
#define XPS_DMA2_INT_ID 48U
#define XPS_DMA3_INT_ID 49U
#define XPS_SMC_INT_ID 50U
#define XPS_QSPI_INT_ID 51U
#define XPS_GPIO_INT_ID 52U
#define XPS_USB0_INT_ID 53U
#define XPS_GEM0_INT_ID 54U
#define XPS_GEM0_WAKE_INT_ID 55U
#define XPS_SDIO0_INT_ID 56U
#define XPS_I2C0_INT_ID 57U
#define XPS_SPI0_INT_ID 58U
#define XPS_UART0_INT_ID 59U
#define XPS_CAN0_INT_ID 60U
#define XPS_FPGA0_INT_ID 61U
#define XPS_FPGA1_INT_ID 62U
#define XPS_FPGA2_INT_ID 63U
#define XPS_FPGA3_INT_ID 64U
#define XPS_FPGA4_INT_ID 65U
#define XPS_FPGA5_INT_ID 66U
#define XPS_FPGA6_INT_ID 67U
#define XPS_FPGA7_INT_ID 68U
#define XPS_TTC1_0_INT_ID 69U
#define XPS_TTC1_1_INT_ID 70U
#define XPS_TTC1_2_INT_ID 71U
#define XPS_DMA4_INT_ID 72U
#define XPS_DMA5_INT_ID 73U
#define XPS_DMA6_INT_ID 74U
#define XPS_DMA7_INT_ID 75U
#define XPS_USB1_INT_ID 76U
#define XPS_GEM1_INT_ID 77U
#define XPS_GEM1_WAKE_INT_ID 78U
#define XPS_SDIO1_INT_ID 79U
#define XPS_I2C1_INT_ID 80U
#define XPS_SPI1_INT_ID 81U
#define XPS_UART1_INT_ID 82U
#define XPS_CAN1_INT_ID 83U
#define XPS_FPGA8_INT_ID 84U
#define XPS_FPGA9_INT_ID 85U
#define XPS_FPGA10_INT_ID 86U
#define XPS_FPGA11_INT_ID 87U
#define XPS_FPGA12_INT_ID 88U
#define XPS_FPGA13_INT_ID 89U
#define XPS_FPGA14_INT_ID 90U
#define XPS_FPGA15_INT_ID 91U
/* Private Peripheral Interrupts (PPI) */
#define XPS_GLOBAL_TMR_INT_ID 27U /* SCU Global Timer interrupt */
#define XPS_FIQ_INT_ID 28U /* FIQ from FPGA fabric */
#define XPS_SCU_TMR_INT_ID 29U /* SCU Private Timer interrupt */
#define XPS_SCU_WDT_INT_ID 30U /* SCU Private WDT interrupt */
#define XPS_IRQ_INT_ID 31U /* IRQ from FPGA fabric */
/* REDEFINES for TEST APP */
/* Definitions for UART */
#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID
#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID
#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID
#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID
#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID
#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID
#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID
#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID
#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID
#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID
#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID
#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID
#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID
#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID
#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID
#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
#define XPAR_PS7_TTC_0_INTR XPS_TTC0_0_INT_ID
#define XPAR_PS7_TTC_1_INTR XPS_TTC0_1_INT_ID
#define XPAR_PS7_TTC_2_INTR XPS_TTC0_2_INT_ID
#define XPAR_PS7_TTC_3_INTR XPS_TTC1_0_INT_ID
#define XPAR_PS7_TTC_4_INTR XPS_TTC1_1_INT_ID
#define XPAR_PS7_TTC_5_INTR XPS_TTC1_2_INT_ID
#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
/* For backwards compatibilty */
#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
#define XPAR_SCUTIMER_DEVICE_ID 0U
#define XPAR_SCUWDT_DEVICE_ID 0U
#ifdef __cplusplus
}
#endif
#endif /* protection macro */

1
src/APP/Aufgabe3/ps7/core0/cfg/xparameters_ps.h Symbolic link
View File

@@ -0,0 +1 @@
../../../../Aufgabe1/ps7/core0/cfg/xparameters_ps.h

291
src/APP/Aufgabe3/ps7/core0/linker/lscript.ld
View File

@@ -1,291 +0,0 @@
/*******************************************************************/
/* */
/* This file is automatically generated by linker script generator.*/
/* */
/* Version: */
/* */
/* Copyright (c) 2010-2016 Xilinx, Inc. All rights reserved. */
/* */
/* Description : Cortex-A9 Linker Script */
/* */
/*******************************************************************/
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
/* Define Memories in the system */
MEMORY
{
axi_bram_ctrl_0_Mem0 : ORIGIN = 0x40000000, LENGTH = 0x2000
ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x3FF00000
ps7_qspi_linear_0 : ORIGIN = 0xFC000000, LENGTH = 0x2000000
ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000
ps7_ram_1 : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00
ps7_ddr_core_0 : ORIGIN = 0x100000, LENGTH = 0x700000
ps7_ddr_core_1 : ORIGIN = 0x800000, LENGTH = 0x800000
}
/* Specify the default entry point to the program */
ENTRY(_vector_table)
/* Define the sections, and where they are mapped in memory */
SECTIONS
{
.text : {
KEEP (*(.vectors))
*(.boot)
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
*(.plt)
*(.gnu_warning)
*(.gcc_execpt_table)
*(.glue_7)
*(.glue_7t)
*(.vfp11_veneer)
*(.ARM.extab)
*(.gnu.linkonce.armextab.*)
} > ps7_ddr_core_0
.init : {
KEEP (*(.init))
} > ps7_ddr_core_0
.fini : {
KEEP (*(.fini))
} > ps7_ddr_core_0
.rodata : {
__rodata_start = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
__rodata_end = .;
} > ps7_ddr_core_0
.rodata1 : {
__rodata1_start = .;
*(.rodata1)
*(.rodata1.*)
__rodata1_end = .;
} > ps7_ddr_core_0
.sdata2 : {
__sdata2_start = .;
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
__sdata2_end = .;
} > ps7_ddr_core_0
.sbss2 : {
__sbss2_start = .;
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
__sbss2_end = .;
} > ps7_ddr_core_0
.data : {
__data_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.jcr)
*(.got)
*(.got.plt)
__data_end = .;
} > ps7_ddr_core_0
.data1 : {
__data1_start = .;
*(.data1)
*(.data1.*)
__data1_end = .;
} > ps7_ddr_core_0
.got : {
*(.got)
} > ps7_ddr_core_0
.ctors : {
__CTOR_LIST__ = .;
___CTORS_LIST___ = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
___CTORS_END___ = .;
} > ps7_ddr_core_0
.dtors : {
__DTOR_LIST__ = .;
___DTORS_LIST___ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
___DTORS_END___ = .;
} > ps7_ddr_core_0
.fixup : {
__fixup_start = .;
*(.fixup)
__fixup_end = .;
} > ps7_ddr_core_0
.eh_frame : {
*(.eh_frame)
} > ps7_ddr_core_0
.eh_framehdr : {
__eh_framehdr_start = .;
*(.eh_framehdr)
__eh_framehdr_end = .;
} > ps7_ddr_core_0
.gcc_except_table : {
*(.gcc_except_table)
} > ps7_ddr_core_0
.mmu_tbl (ALIGN(16384)) : {
__mmu_tbl_start = .;
*(.mmu_tbl)
__mmu_tbl_end = .;
} > ps7_ddr_core_0
.ARM.exidx : {
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidix.*.*)
__exidx_end = .;
} > ps7_ddr_core_0
.preinit_array : {
__preinit_array_start = .;
KEEP (*(SORT(.preinit_array.*)))
KEEP (*(.preinit_array))
__preinit_array_end = .;
} > ps7_ddr_core_0
.init_array : {
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
} > ps7_ddr_core_0
.fini_array : {
__fini_array_start = .;
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array))
__fini_array_end = .;
} > ps7_ddr_core_0
.ARM.attributes : {
__ARM.attributes_start = .;
*(.ARM.attributes)
__ARM.attributes_end = .;
} > ps7_ddr_core_0
.sdata : {
__sdata_start = .;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
__sdata_end = .;
} > ps7_ddr_core_0
.sbss (NOLOAD) : {
__sbss_start = .;
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
__sbss_end = .;
} > ps7_ddr_core_0
.tdata : {
__tdata_start = .;
*(.tdata)
*(.tdata.*)
*(.gnu.linkonce.td.*)
__tdata_end = .;
} > ps7_ddr_core_0
.tbss : {
__tbss_start = .;
*(.tbss)
*(.tbss.*)
*(.gnu.linkonce.tb.*)
__tbss_end = .;
} > ps7_ddr_core_0
.bss (NOLOAD) : {
__bss_start = .;
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
__bss_end = .;
} > ps7_ddr_core_0
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
/* Generate Stack and Heap definitions */
.heap (NOLOAD) : {
. = ALIGN(16);
_heap = .;
HeapBase = .;
_heap_start = .;
. += _HEAP_SIZE;
_heap_end = .;
HeapLimit = .;
} > ps7_ddr_core_0
.stack (NOLOAD) : {
. = ALIGN(16);
_stack_end = .;
. += _STACK_SIZE;
. = ALIGN(16);
_stack = .;
__stack = _stack;
. = ALIGN(16);
_irq_stack_end = .;
. += _IRQ_STACK_SIZE;
. = ALIGN(16);
__irq_stack = .;
_supervisor_stack_end = .;
. += _SUPERVISOR_STACK_SIZE;
. = ALIGN(16);
__supervisor_stack = .;
_abort_stack_end = .;
. += _ABORT_STACK_SIZE;
. = ALIGN(16);
__abort_stack = .;
_fiq_stack_end = .;
. += _FIQ_STACK_SIZE;
. = ALIGN(16);
__fiq_stack = .;
_undef_stack_end = .;
. += _UNDEF_STACK_SIZE;
. = ALIGN(16);
__undef_stack = .;
} > ps7_ddr_core_0
_end = .;
}

1
src/APP/Aufgabe3/ps7/core0/linker/lscript.ld Symbolic link
View File

@@ -0,0 +1 @@
../../../../Aufgabe1/ps7/core0/linker/lscript.ld

262
src/APP/Aufgabe3/ps7/core0/src/app_hooks.c
View File

@@ -1,262 +0,0 @@
/*
*********************************************************************************************************
* EXAMPLE CODE
*
* This file is provided as an example on how to use Micrium products.
*
* Please feel free to use any application code labeled as 'EXAMPLE CODE' in
* your application products. Example code may be used as is, in whole or in
* part, or may be used as a reference only. This file can be modified as
* required to meet the end-product requirements.
*
* Please help us continue to provide the Embedded community with the finest
* software available. Your honesty is greatly appreciated.
*
* You can find our product's user manual, API reference, release notes and
* more information at https://doc.micrium.com.
* You can contact us at www.micrium.com.
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* uC/OS-II
* Application Hooks
*
* Filename : app_hooks.c
* Version : V1.00
* Programmer(s) : FT
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* INCLUDE FILES
*********************************************************************************************************
*/
#include <ucos_ii.h>
/*
*********************************************************************************************************
* EXTERN GLOBAL VARIABLES
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* LOCAL CONSTANTS
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* LOCAL DATA TYPES
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* LOCAL TABLES
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* LOCAL GLOBAL VARIABLES
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* LOCAL FUNCTION PROTOTYPES
*********************************************************************************************************
*/
/*
**********************************************************************************************************
**********************************************************************************************************
** GLOBAL FUNCTIONS
**********************************************************************************************************
**********************************************************************************************************
*/
/*
*********************************************************************************************************
*********************************************************************************************************
** uC/OS-II APP HOOKS
*********************************************************************************************************
*********************************************************************************************************
*/
#if (OS_APP_HOOKS_EN > 0)
/*
*********************************************************************************************************
* TASK CREATION HOOK (APPLICATION)
*
* Description : This function is called when a task is created.
*
* Argument(s) : ptcb is a pointer to the task control block of the task being created.
*
* Note(s) : (1) Interrupts are disabled during this call.
*********************************************************************************************************
*/
void App_TaskCreateHook (OS_TCB *ptcb)
{
#if (APP_CFG_PROBE_OS_PLUGIN_EN == DEF_ENABLED) && (OS_PROBE_HOOKS_EN > 0)
OSProbe_TaskCreateHook(ptcb);
#endif
}
/*
*********************************************************************************************************
* TASK DELETION HOOK (APPLICATION)
*
* Description : This function is called when a task is deleted.
*
* Argument(s) : ptcb is a pointer to the task control block of the task being deleted.
*
* Note(s) : (1) Interrupts are disabled during this call.
*********************************************************************************************************
*/
void App_TaskDelHook (OS_TCB *ptcb)
{
(void)ptcb;
}
/*
*********************************************************************************************************
* IDLE TASK HOOK (APPLICATION)
*
* Description : This function is called by OSTaskIdleHook(), which is called by the idle task. This hook
* has been added to allow you to do such things as STOP the CPU to conserve power.
*
* Argument(s) : none.
*
* Note(s) : (1) Interrupts are enabled during this call.
*********************************************************************************************************
*/
#if OS_VERSION >= 251
void App_TaskIdleHook (void)
{
__asm volatile( "dsb" );
__asm volatile( "wfi" );
__asm volatile( "isb" );
}
#endif
/*
*********************************************************************************************************
* STATISTIC TASK HOOK (APPLICATION)
*
* Description : This function is called by OSTaskStatHook(), which is called every second by uC/OS-II's
* statistics task. This allows your application to add functionality to the statistics task.
*
* Argument(s) : none.
*********************************************************************************************************
*/
void App_TaskStatHook (void)
{
}
/*
*********************************************************************************************************
* TASK RETURN HOOK (APPLICATION)
*
* Description: This function is called if a task accidentally returns. In other words, a task should
* either be an infinite loop or delete itself when done.
*
* Arguments : ptcb is a pointer to the task control block of the task that is returning.
*
* Note(s) : none
*********************************************************************************************************
*/
#if OS_VERSION >= 289
void App_TaskReturnHook (OS_TCB *ptcb)
{
(void)ptcb;
}
#endif
/*
*********************************************************************************************************
* TASK SWITCH HOOK (APPLICATION)
*
* Description : This function is called when a task switch is performed. This allows you to perform other
* operations during a context switch.
*
* Argument(s) : none.
*
* Note(s) : (1) Interrupts are disabled during this call.
*
* (2) It is assumed that the global pointer 'OSTCBHighRdy' points to the TCB of the task that
* will be 'switched in' (i.e. the highest priority task) and, 'OSTCBCur' points to the
* task being switched out (i.e. the preempted task).
*********************************************************************************************************
*/
#if OS_TASK_SW_HOOK_EN > 0
void App_TaskSwHook (void)
{
#if (APP_CFG_PROBE_OS_PLUGIN_EN > 0) && (OS_PROBE_HOOKS_EN > 0)
OSProbe_TaskSwHook();
#endif
}
#endif
/*
*********************************************************************************************************
* OS_TCBInit() HOOK (APPLICATION)
*
* Description : This function is called by OSTCBInitHook(), which is called by OS_TCBInit() after setting
* up most of the TCB.
*
* Argument(s) : ptcb is a pointer to the TCB of the task being created.
*
* Note(s) : (1) Interrupts may or may not be ENABLED during this call.
*********************************************************************************************************
*/
#if OS_VERSION >= 204
void App_TCBInitHook (OS_TCB *ptcb)
{
(void)ptcb;
}
#endif
/*
*********************************************************************************************************
* TICK HOOK (APPLICATION)
*
* Description : This function is called every tick.
*
* Argument(s) : none.
*
* Note(s) : (1) Interrupts may or may not be ENABLED during this call.
*********************************************************************************************************
*/
#if OS_TIME_TICK_HOOK_EN > 0
void App_TimeTickHook (void)
{
#if (APP_CFG_PROBE_OS_PLUGIN_EN == DEF_ENABLED) && (OS_PROBE_HOOKS_EN > 0)
OSProbe_TickHook();
#endif
}
#endif
#endif

1
src/APP/Aufgabe3/ps7/core0/src/app_hooks.c Symbolic link
View File

@@ -0,0 +1 @@
../../../../Aufgabe2/ps7/core0/src/app_hooks.c

17
src/APP/Aufgabe3/ps7/core0/src/uartps_cfg.c
View File

@@ -1,17 +0,0 @@
#include "ucos_uartps.h"
#include "xparameters.h"
#include "xparameters_ps.h"
/*
* The uart configuration table for devices
*/
UCOS_UARTPS_Config UCOS_UARTPS_ConfigTable[] = {
{
XPAR_PS7_UART_1_DEVICE_ID,
XPAR_PS7_UART_1_BASEADDR,
XPAR_PS7_UART_1_UART_CLK_FREQ_HZ,
XPAR_PS7_UART_1_HAS_MODEM,
XPAR_PS7_UART_1_INT_SOURCE
}
};

1
src/APP/Aufgabe3/ps7/core0/src/uartps_cfg.c Symbolic link
View File

@@ -0,0 +1 @@
../../../../Aufgabe1/ps7/core0/src/uartps_cfg.c

63
src/APP/Aufgabe3/ps7/core0/src/xiicps_g.c
View File

@@ -1,63 +0,0 @@
/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
*(a) running on a Xilinx device, or
*(b) that interact with a Xilinx device through a bus or interconnect.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Driver configuration
*
*******************************************************************/
#include "xparameters.h"
#include "xparameters_ps.h"
#include "xiicps.h"
/*
* The configuration table for devices
*/
XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES] =
{
{
XPAR_PS7_I2C_0_DEVICE_ID,
XPAR_PS7_I2C_0_BASEADDR,
XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ
},
{
XPAR_PS7_I2C_1_DEVICE_ID,
XPAR_PS7_I2C_1_BASEADDR,
XPAR_PS7_I2C_1_I2C_CLK_FREQ_HZ
}
};

1
src/APP/Aufgabe4/ps7/core0/build/config.mk
View File

@@ -1,6 +1,5 @@
#µController dependent flags
MCFLAGS =-mcpu=cortex-a9 -march=armv7-a -mthumb -mthumb-interwork -mfloat-abi=softfp -mfpu=neon
#Optimization
OPTIMIZE=-O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections

52
src/APP/Aufgabe4/ps7/core0/build/includes.mk
View File

@@ -1,52 +0,0 @@
INC += -I"$(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/cfg/"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Ports/ARM-Cortex-A/Generic/GNU/"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/ARM-Cortex-A/GNU/"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-Common"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Source"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-LIB"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/bsp/src/ipi"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/bsp/src/"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/bsp/src/$(ARCH)/"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_cpu_cortexa9/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_scugic/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_l2cachec/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_uartps/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_emacps/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_scuc/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_ttcps/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/cortexa9"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/cortexa9/gcc"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/common"
INC += -I"$(SRC_DIR)/Xilinx/libsrc/ipipsu_v2_3/src/"
INC += -I"$(SRC_DIR)/Modules/MMU"
INC += -I"$(SRC_DIR)/Xilinx/libsrc/ipipsu_v2_3/src/"
#scugic.h fix
INC += -I"$(SRC_DIR)/Xilinx/libsrc/scugic_v3_9/src/"
#uart includes
INC += -I"$(SRC_DIR)/Xilinx/libsrc/uartps_v3_6/src/"
#xttcps includes
INC += -I"$(SRC_DIR)/Xilinx/libsrc/ttcps_v3_5/src/"
#gpio includes
INC += -I"$(SRC_DIR)/Xilinx/libsrc/gpiops_v3_3/src/"
#I2C includes
INC += -I"$(SRC_DIR)/Xilinx/libsrc/iicps_v3_6/src/"
#task set includes
INC += -I"$(SRC_DIR)/Modules/genericTaskset/if"

1
src/APP/Aufgabe4/ps7/core0/build/includes.mk Symbolic link
View File

@@ -0,0 +1 @@
../../../../Aufgabe1/ps7/core0/build/includes.mk

7
src/APP/Aufgabe4/ps7/core0/build/sources.mk
View File

@@ -8,14 +8,12 @@ SRC += $(SRC_DIR)/ucos_v1_42/ucos/bsp/src/$(ARCH)/asm_vectors.S
SRC += $(SRC_DIR)/ucos_v1_42/ucos/components/ucos_osii/src/bsp/$(ARCH)/ucos_osii_bsp.c
SRC += $(SRC_DIR)/ucos_v1_42/ucos/components/ucos_common/src/$(ARCH)/cpu_bsp.c
SRC += $(SRC_DIR)/Modules/MMU/mmu.c
SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/main.c
SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/app_hooks.c
SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/uartps_cfg.c
SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/imu.c
SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/xttcps_g.c
SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/xgpiops_g.c
SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/xiicps_g.c
SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Ports/ARM-Cortex-A/Generic/GNU/os_cpu_a_vfp-d32.S
@@ -43,9 +41,6 @@ SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-Common/Auth/auth.c
-include $(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Source/subdir.mk
#mmu
SRC += $(SRC_DIR)/Modules/MMU/mmu.c
#src for triple timer counter
SRC +=$(SRC_DIR)/Xilinx/libsrc/ttcps_v3_5/src/xttcps.c

216
src/APP/Aufgabe4/ps7/core0/cfg/cpu_cfg.h
View File

@@ -1,216 +0,0 @@
/*
*********************************************************************************************************
* uC/CPU
* CPU CONFIGURATION & PORT LAYER
*
* (c) Copyright 2004-2015; Micrium, Inc.; Weston, FL
*
* All rights reserved. Protected by international copyright laws.
*
* uC/CPU is provided in source form to registered licensees ONLY. It is
* illegal to distribute this source code to any third party unless you receive
* written permission by an authorized Micrium representative. Knowledge of
* the source code may NOT be used to develop a similar product.
*
* Please help us continue to provide the Embedded community with the finest
* software available. Your honesty is greatly appreciated.
*
* You can find our product's user manual, API reference, release notes and
* more information at https://doc.micrium.com.
* You can contact us at www.micrium.com.
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* CPU CONFIGURATION FILE
*
* TEMPLATE
*
* Filename : cpu_cfg.h
* Version : V1.30.02
* Programmer(s) : SR
* ITJ
* JBL
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* MODULE
*********************************************************************************************************
*/
#ifndef CPU_CFG_MODULE_PRESENT
#define CPU_CFG_MODULE_PRESENT
/*
*********************************************************************************************************
* CPU NAME CONFIGURATION
*
* Note(s) : (1) Configure CPU_CFG_NAME_EN to enable/disable CPU host name feature :
*
* (a) CPU host name storage
* (b) CPU host name API functions
*
* (2) Configure CPU_CFG_NAME_SIZE with the desired ASCII string size of the CPU host name,
* including the terminating NULL character.
*
* See also 'cpu_core.h GLOBAL VARIABLES Note #1'.
*********************************************************************************************************
*/
/* Configure CPU host name feature (see Note #1) : */
#define CPU_CFG_NAME_EN DEF_DISABLED
/* DEF_DISABLED CPU host name DISABLED */
/* DEF_ENABLED CPU host name ENABLED */
/* Configure CPU host name ASCII string size ... */
#define CPU_CFG_NAME_SIZE 16
/*
*********************************************************************************************************
* CPU TIMESTAMP CONFIGURATION
*
* Note(s) : (1) Configure CPU_CFG_TS_xx_EN to enable/disable CPU timestamp features :
*
* (a) CPU_CFG_TS_32_EN enable/disable 32-bit CPU timestamp feature
* (b) CPU_CFG_TS_64_EN enable/disable 64-bit CPU timestamp feature
*
* (2) (a) Configure CPU_CFG_TS_TMR_SIZE with the CPU timestamp timer's word size :
*
* CPU_WORD_SIZE_08 8-bit word size
* CPU_WORD_SIZE_16 16-bit word size
* CPU_WORD_SIZE_32 32-bit word size
* CPU_WORD_SIZE_64 64-bit word size
*
* (b) If the size of the CPU timestamp timer is not a binary multiple of 8-bit octets
* (e.g. 20-bits or even 24-bits), then the next lower, binary-multiple octet word
* size SHOULD be configured (e.g. to 16-bits). However, the minimum supported word
* size for CPU timestamp timers is 8-bits.
*
* See also 'cpu_core.h FUNCTION PROTOTYPES CPU_TS_TmrRd() Note #2a'.
*********************************************************************************************************
*/
/* Configure CPU timestamp features (see Note #1) : */
#define CPU_CFG_TS_32_EN DEF_ENABLED
#define CPU_CFG_TS_64_EN DEF_ENABLED
/* DEF_DISABLED CPU timestamps DISABLED */
/* DEF_ENABLED CPU timestamps ENABLED */
/* Configure CPU timestamp timer word size ... */
/* ... (see Note #2) : */
#define CPU_CFG_TS_TMR_SIZE CPU_WORD_SIZE_64
/*
*********************************************************************************************************
* CPU INTERRUPTS DISABLED TIME MEASUREMENT CONFIGURATION
*
* Note(s) : (1) (a) Configure CPU_CFG_INT_DIS_MEAS_EN to enable/disable measuring CPU's interrupts
* disabled time :
*
* (a) Enabled, if CPU_CFG_INT_DIS_MEAS_EN #define'd in 'cpu_cfg.h'
*
* (b) Disabled, if CPU_CFG_INT_DIS_MEAS_EN NOT #define'd in 'cpu_cfg.h'
*
* See also 'cpu_core.h FUNCTION PROTOTYPES Note #1'.
*
* (b) Configure CPU_CFG_INT_DIS_MEAS_OVRHD_NBR with the number of times to measure &
* average the interrupts disabled time measurements overhead.
*
* See also 'cpu_core.c CPU_IntDisMeasInit() Note #3a'.
*********************************************************************************************************
*/
#if 0 /* Configure CPU interrupts disabled time ... */
#define CPU_CFG_INT_DIS_MEAS_EN /* ... measurements feature (see Note #1a). */
#endif
/* Configure number of interrupts disabled overhead ... */
#define CPU_CFG_INT_DIS_MEAS_OVRHD_NBR 1u /* ... time measurements (see Note #1b). */
/*
*********************************************************************************************************
* CPU COUNT ZEROS CONFIGURATION
*
* Note(s) : (1) (a) Configure CPU_CFG_LEAD_ZEROS_ASM_PRESENT to define count leading zeros bits
* function(s) in :
*
* (1) 'cpu_a.asm', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable assembly-optimized function(s)
*
* (2) 'cpu_core.c', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT NOT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
*
* (b) Configure CPU_CFG_TRAIL_ZEROS_ASM_PRESENT to define count trailing zeros bits
* function(s) in :
*
* (1) 'cpu_a.asm', if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable assembly-optimized function(s)
*
* (2) 'cpu_core.c', if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT NOT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
*********************************************************************************************************
*/
#if 0 /* Configure CPU count leading zeros bits ... */
#define CPU_CFG_LEAD_ZEROS_ASM_PRESENT /* ... assembly-version (see Note #1a). */
#endif
#if 0 /* Configure CPU count trailing zeros bits ... */
#define CPU_CFG_TRAIL_ZEROS_ASM_PRESENT /* ... assembly-version (see Note #1b). */
#endif
/*
*********************************************************************************************************
* CPU ENDIAN TYPE OVERRIDE
*
* Note(s) : (1) Configure CPU_CFG_ENDIAN_TYPE to override the default CPU endian type defined in cpu.h.
*
* (a) CPU_ENDIAN_TYPE_BIG Big- endian word order (CPU words' most significant
* octet @ lowest memory address)
* (b) CPU_ENDIAN_TYPE_LITTLE Little-endian word order (CPU words' least significant
* octet @ lowest memory address)
*
* (2) Defining CPU_CFG_ENDIAN_TYPE here is only valid for supported bi-endian architectures.
* See 'cpu.h CPU WORD CONFIGURATION Note #3' for details
*********************************************************************************************************
*/
#if 0
#define CPU_CFG_ENDIAN_TYPE CPU_ENDIAN_TYPE_BIG /* Defines CPU data word-memory order (see Note #2). */
#endif
/*
*********************************************************************************************************
* CACHE MANAGEMENT
*
* Note(s) : (1) Configure CPU_CFG_CACHE_MGMT_EN to enable the cache managment API.
*
* (2) Defining CPU_CFG_CACHE_MGMT_EN to DEF_ENABLED only enable the cache management function.
* Cache are assumed to be configured and enabled by the time CPU_init() is called.
*********************************************************************************************************
*/
#define CPU_CFG_CACHE_MGMT_EN DEF_DISABLED
/*
*********************************************************************************************************
* MODULE END
*********************************************************************************************************
*/
#endif /* End of CPU cfg module include. */
#define CPU_CACHE_CFG_L2C310_BASE_ADDR 0xF8F02000

1
src/APP/Aufgabe4/ps7/core0/cfg/cpu_cfg.h Symbolic link
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@@ -0,0 +1 @@
../../../../Aufgabe1/ps7/core0/cfg/cpu_cfg.h

171
src/APP/Aufgabe4/ps7/core0/cfg/lib_cfg.h
View File

@@ -1,171 +0,0 @@
/*
*********************************************************************************************************
* EXAMPLE CODE
*
* This file is provided as an example on how to use Micrium products.
*
* Please feel free to use any application code labeled as 'EXAMPLE CODE' in
* your application products. Example code may be used as is, in whole or in
* part, or may be used as a reference only. This file can be modified as
* required to meet the end-product requirements.
*
* Please help us continue to provide the Embedded community with the finest
* software available. Your honesty is greatly appreciated.
*
* You can find information about uC/LIB by visiting doc.micrium.com.
* You can contact us at: http://www.micrium.com
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* CUSTOM LIBRARY CONFIGURATION FILE
*
* TEMPLATE
*
* Filename : lib_cfg.h
* Version : V1.38.01.00
* Programmer(s) : FBJ
* JFD
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* MODULE
*********************************************************************************************************
*/
#ifndef LIB_CFG_MODULE_PRESENT
#define LIB_CFG_MODULE_PRESENT
/*
*********************************************************************************************************
*********************************************************************************************************
* MEMORY LIBRARY CONFIGURATION
*********************************************************************************************************
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* MEMORY LIBRARY ARGUMENT CHECK CONFIGURATION
*
* Note(s) : (1) Configure LIB_MEM_CFG_ARG_CHK_EXT_EN to enable/disable the memory library suite external
* argument check feature :
*
* (a) When ENABLED, arguments received from any port interface provided by the developer
* or application are checked/validated.
*
* (b) When DISABLED, NO arguments received from any port interface provided by the developer
* or application are checked/validated.
*********************************************************************************************************
*/
/* External argument check. */
/* Indicates if arguments received from any port ... */
/* ... interface provided by the developer or ... */
/* ... application are checked/validated. */
#define LIB_MEM_CFG_ARG_CHK_EXT_EN DEF_DISABLED
/*
*********************************************************************************************************
* MEMORY LIBRARY ASSEMBLY OPTIMIZATION CONFIGURATION
*
* Note(s) : (1) Configure LIB_MEM_CFG_OPTIMIZE_ASM_EN to enable/disable assembly-optimized memory function(s).
*********************************************************************************************************
*/
/* Assembly-optimized function(s). */
/* Enable/disable assembly-optimized memory ... */
/* ... function(s). [see Note #1] */
#define LIB_MEM_CFG_OPTIMIZE_ASM_EN DEF_DISABLED
/*
*********************************************************************************************************
* MEMORY ALLOCATION CONFIGURATION
*
* Note(s) : (1) Configure LIB_MEM_CFG_DBG_INFO_EN to enable/disable memory allocation usage tracking
* that associates a name with each segment or dynamic pool allocated.
*
* (2) (a) Configure LIB_MEM_CFG_HEAP_SIZE with the desired size of heap memory (in octets).
*
* (b) Configure LIB_MEM_CFG_HEAP_BASE_ADDR to specify a base address for heap memory :
*
* (1) Heap initialized to specified application memory, if LIB_MEM_CFG_HEAP_BASE_ADDR
* #define'd in 'lib_cfg.h';
* CANNOT #define to address 0x0
*
* (2) Heap declared to Mem_Heap[] in 'lib_mem.c', if LIB_MEM_CFG_HEAP_BASE_ADDR
* NOT #define'd in 'lib_cfg.h'
*********************************************************************************************************
*/
/* Allocation debugging information. */
/* Enable/disable allocation of debug information ... */
/* ... associated to each memory allocation. */
#define LIB_MEM_CFG_DBG_INFO_EN DEF_DISABLED
/* Heap memory size (in bytes). */
/* Configure the desired size of the heap memory. ... */
/* ... Set to 0 to disable heap allocation features. */
#define LIB_MEM_CFG_HEAP_SIZE 64*1024
/* Heap memory padding alignment (in bytes). */
/* Configure the desired size of padding alignment ... */
/* ... of each buffer allocated from the heap. */
#define LIB_MEM_CFG_HEAP_PADDING_ALIGN LIB_MEM_PADDING_ALIGN_NONE
#if 0 /* Remove this to have heap alloc at specified addr. */
#define LIB_MEM_CFG_HEAP_BASE_ADDR 0
#endif
/*
*********************************************************************************************************
*********************************************************************************************************
* STRING LIBRARY CONFIGURATION
*********************************************************************************************************
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* STRING FLOATING POINT CONFIGURATION
*
* Note(s) : (1) Configure LIB_STR_CFG_FP_EN to enable/disable floating point string function(s).
*
* (2) Configure LIB_STR_CFG_FP_MAX_NBR_DIG_SIG to configure the maximum number of significant
* digits to calculate &/or display for floating point string function(s).
*
* See also 'lib_str.h STRING FLOATING POINT DEFINES Note #1'.
*********************************************************************************************************
*/
/* Floating point feature(s). */
/* Enable/disable floating point to string functions. */
#define LIB_STR_CFG_FP_EN DEF_DISABLED
/* Floating point number of significant digits. */
/* Configure the maximum number of significant ... */
/* ... digits to calculate &/or display for ... */
/* ... floating point string function(s). */
#define LIB_STR_CFG_FP_MAX_NBR_DIG_SIG LIB_STR_FP_MAX_NBR_DIG_SIG_DFLT
/*
*********************************************************************************************************
* MODULE END
*********************************************************************************************************
*/
#endif /* End of lib cfg module include. */

1
src/APP/Aufgabe4/ps7/core0/cfg/lib_cfg.h Symbolic link
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@@ -0,0 +1 @@
../../../../Aufgabe1/ps7/core0/cfg/lib_cfg.h

42
src/APP/Aufgabe4/ps7/core0/cfg/mmu_cfg.h
View File

@@ -1,42 +0,0 @@
/*
* mmu_cfg.h
*
* Created on: 25.04.2018
* Author: kaige
*/
#ifndef SRC_APP_LWIPREWORK_PS7_CORE0_CFG_MMU_CFG_H_
#define SRC_APP_LWIPREWORK_PS7_CORE0_CFG_MMU_CFG_H_
#include "mmu.h"
/*------------------------------------------------------------------------------------------------*/
/*!
* \brief FIRST LEVEL TRANSLATION TABLE (FTT)
*
* \ingroup PAR_CPU_MMU
*
* This variable represents the first level translation table. Each entry within
* the table represents the configuration of a 1MB memory segment. If a memory
* portion below 1MB must be accessed, the entry represents a pointer to the
* linked coarse page table, which contains the information of that 1MB in detail.
*
* \note This table MUST be aligned at 16kB boundary.
*/
/*------------------------------------------------------------------------------------------------*/
const PAR_MEM_REGION_T PARMemTbl_Core[] = {
/* +-------------------------------------------------------------------------------------------+
* | virtual | physical | size | owner | permissions | HID Field |
* +-----------+-----------+---------------+------------------+-----------------+--------------+*/
// First 1MB is marked as non-cacheable/non-bufferable (contains 3x 64KB SRAM @ address 0x00000000
{ 0x00000000, 0x00000000, MMU_SIZE_1MB, PAR_AP_PRW__URW_, PAR_HID_TEX_CB_CACHED_MEMORY | PAR_HID_CACHE_INNER_CB | PAR_HID_CACHE_OUTER_CB },
// DDR Memory is marked as normal (only 512MB for now)
{ 0x00100000, 0x00100000, MMU_SIZE_16MB, PAR_AP_PRW__URW_, PAR_HID_TEX_CB_CACHED_MEMORY | PAR_HID_CACHE_INNER___ | PAR_HID_CACHE_OUTER___ },
// Device section
{ 0xE0000000, 0xE0000000, MMU_SIZE_512MB-MMU_SIZE_1MB, PAR_AP_PRW__URW_, PAR_HID_EXCLUSIVE_SYS_DEVICE },
// Upper 1MB section contains 1x 64KB SRAM @ address 0xFFFF0000
{ 0xFFF00000, 0xFFF00000, MMU_SIZE_1MB, PAR_AP_PRW__URW_, PAR_HID_TEX_CB_OUT_IN_NON_CACHABLE }
};
#endif /* SRC_APP_LWIPREWORK_PS7_CORE0_CFG_MMU_CFG_H_ */

1
src/APP/Aufgabe4/ps7/core0/cfg/mmu_cfg.h Symbolic link
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@@ -0,0 +1 @@
../../../../Aufgabe1/ps7/core0/cfg/mmu_cfg.h

145
src/APP/Aufgabe4/ps7/core0/cfg/os_cfg.h
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@@ -1,145 +0,0 @@
/*
*********************************************************************************************************
* uC/OS-II
* The Real-Time Kernel
* uC/OS-II Configuration File for V2.9x
*
* (c) Copyright 2005-2014, Micrium, Weston, FL
* All Rights Reserved
*
*
* File : OS_CFG.H
* By : Jean J. Labrosse
* Version : V2.92.11
*
* LICENSING TERMS:
* ---------------
* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research.
* If you plan on using uC/OS-II in a commercial product you need to contact Micrium to properly license
* its use in your product. We provide ALL the source code for your convenience and to help you experience
* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a
* licensing fee.
*********************************************************************************************************
*/
#ifndef OS_CFG_H
#define OS_CFG_H
/* ---------------------- MISCELLANEOUS ----------------------- */
#define OS_APP_HOOKS_EN 1u /* Application-defined hooks are called from the uC/OS-II hooks */
#define OS_ARG_CHK_EN 0u /* Enable (1) or Disable (0) argument checking */
#define OS_CPU_HOOKS_EN 1u /* uC/OS-II hooks are found in the processor port files */
#define OS_DEBUG_EN 1u /* Enable(1) debug variables */
#define OS_EVENT_MULTI_EN 1u /* Include code for OSEventPendMulti() */
#define OS_EVENT_NAME_EN 1u /* Enable names for Sem, Mutex, Mbox and Q */
#define OS_LOWEST_PRIO 63u /* Defines the lowest priority that can be assigned ... */
/* ... MUST NEVER be higher than 254! */
#define OS_MAX_EVENTS 20u /* Max. number of event control blocks in your application */
#define OS_MAX_FLAGS 5u /* Max. number of Event Flag Groups in your application */
#define OS_MAX_MEM_PART 5u /* Max. number of memory partitions */
#define OS_MAX_QS 6u /* Max. number of queue control blocks in your application */
#define OS_MAX_TASKS 20u /* Max. number of tasks in your application, MUST be >= 2 */
#define OS_SCHED_LOCK_EN 1u /* Include code for OSSchedLock() and OSSchedUnlock() */
#define OS_TICK_STEP_EN 1u /* Enable tick stepping feature for uC/OS-View */
#define OS_TICKS_PER_SEC 1000u /* Set the number of ticks in one second */
#define OS_TLS_TBL_SIZE 0u /* Size of Thread-Local Storage Table */
/* --------------------- TASK STACK SIZE ---------------------- */
#define OS_TASK_TMR_STK_SIZE 128u /* Timer task stack size (# of OS_STK wide entries) */
#define OS_TASK_STAT_STK_SIZE 128u /* Statistics task stack size (# of OS_STK wide entries) */
#define OS_TASK_IDLE_STK_SIZE 128u /* Idle task stack size (# of OS_STK wide entries) */
/* --------------------- TASK MANAGEMENT ---------------------- */
#define OS_TASK_CHANGE_PRIO_EN 1u /* Include code for OSTaskChangePrio() */
#define OS_TASK_CREATE_EN 1u /* Include code for OSTaskCreate() */
#define OS_TASK_CREATE_EXT_EN 1u /* Include code for OSTaskCreateExt() */
#define OS_TASK_DEL_EN 1u /* Include code for OSTaskDel() */
#define OS_TASK_NAME_EN 1u /* Enable task names */
#define OS_TASK_PROFILE_EN 1u /* Include variables in OS_TCB for profiling */
#define OS_TASK_QUERY_EN 1u /* Include code for OSTaskQuery() */
#define OS_TASK_REG_TBL_SIZE 1u /* Size of task variables array (#of INT32U entries) */
#define OS_TASK_STAT_EN 1u /* Enable (1) or Disable(0) the statistics task */
#define OS_TASK_STAT_STK_CHK_EN 1u /* Check task stacks from statistic task */
#define OS_TASK_SUSPEND_EN 1u /* Include code for OSTaskSuspend() and OSTaskResume() */
#define OS_TASK_SW_HOOK_EN 1u /* Include code for OSTaskSwHook() */
/* ----------------------- EVENT FLAGS ------------------------ */
#define OS_FLAG_EN 1u /* Enable (1) or Disable (0) code generation for EVENT FLAGS */
#define OS_FLAG_ACCEPT_EN 1u /* Include code for OSFlagAccept() */
#define OS_FLAG_DEL_EN 1u /* Include code for OSFlagDel() */
#define OS_FLAG_NAME_EN 1u /* Enable names for event flag group */
#define OS_FLAG_QUERY_EN 1u /* Include code for OSFlagQuery() */
#define OS_FLAG_WAIT_CLR_EN 1u /* Include code for Wait on Clear EVENT FLAGS */
#define OS_FLAGS_NBITS 16u /* Size in #bits of OS_FLAGS data type (8, 16 or 32) */
/* -------------------- MESSAGE MAILBOXES --------------------- */
#define OS_MBOX_EN 1u /* Enable (1) or Disable (0) code generation for MAILBOXES */
#define OS_MBOX_ACCEPT_EN 1u /* Include code for OSMboxAccept() */
#define OS_MBOX_DEL_EN 1u /* Include code for OSMboxDel() */
#define OS_MBOX_PEND_ABORT_EN 1u /* Include code for OSMboxPendAbort() */
#define OS_MBOX_POST_EN 1u /* Include code for OSMboxPost() */
#define OS_MBOX_POST_OPT_EN 1u /* Include code for OSMboxPostOpt() */
#define OS_MBOX_QUERY_EN 1u /* Include code for OSMboxQuery() */
/* --------------------- MEMORY MANAGEMENT -------------------- */
#define OS_MEM_EN 1u /* Enable (1) or Disable (0) code generation for MEMORY MANAGER */
#define OS_MEM_NAME_EN 1u /* Enable memory partition names */
#define OS_MEM_QUERY_EN 1u /* Include code for OSMemQuery() */
/* ---------------- MUTUAL EXCLUSION SEMAPHORES --------------- */
#define OS_MUTEX_EN 1u /* Enable (1) or Disable (0) code generation for MUTEX */
#define OS_MUTEX_ACCEPT_EN 1u /* Include code for OSMutexAccept() */
#define OS_MUTEX_DEL_EN 1u /* Include code for OSMutexDel() */
#define OS_MUTEX_QUERY_EN 1u /* Include code for OSMutexQuery() */
/* ---------------------- MESSAGE QUEUES ---------------------- */
#define OS_Q_EN 1u /* Enable (1) or Disable (0) code generation for QUEUES */
#define OS_Q_ACCEPT_EN 1u /* Include code for OSQAccept() */
#define OS_Q_DEL_EN 1u /* Include code for OSQDel() */
#define OS_Q_FLUSH_EN 1u /* Include code for OSQFlush() */
#define OS_Q_PEND_ABORT_EN 1u /* Include code for OSQPendAbort() */
#define OS_Q_POST_EN 1u /* Include code for OSQPost() */
#define OS_Q_POST_FRONT_EN 1u /* Include code for OSQPostFront() */
#define OS_Q_POST_OPT_EN 1u /* Include code for OSQPostOpt() */
#define OS_Q_QUERY_EN 1u /* Include code for OSQQuery() */
/* ------------------------ SEMAPHORES ------------------------ */
#define OS_SEM_EN 1u /* Enable (1) or Disable (0) code generation for SEMAPHORES */
#define OS_SEM_ACCEPT_EN 1u /* Include code for OSSemAccept() */
#define OS_SEM_DEL_EN 1u /* Include code for OSSemDel() */
#define OS_SEM_PEND_ABORT_EN 1u /* Include code for OSSemPendAbort() */
#define OS_SEM_QUERY_EN 1u /* Include code for OSSemQuery() */
#define OS_SEM_SET_EN 1u /* Include code for OSSemSet() */
/* --------------------- TIME MANAGEMENT ---------------------- */
#define OS_TIME_DLY_HMSM_EN 1u /* Include code for OSTimeDlyHMSM() */
#define OS_TIME_DLY_RESUME_EN 1u /* Include code for OSTimeDlyResume() */
#define OS_TIME_GET_SET_EN 1u /* Include code for OSTimeGet() and OSTimeSet() */
#define OS_TIME_TICK_HOOK_EN 1u /* Include code for OSTimeTickHook() */
/* --------------------- TIMER MANAGEMENT --------------------- */
#define OS_TMR_EN 0u /* Enable (1) or Disable (0) code generation for TIMERS */
#define OS_TMR_CFG_MAX 16u /* Maximum number of timers */
#define OS_TMR_CFG_NAME_EN 1u /* Determine timer names */
#define OS_TMR_CFG_WHEEL_SIZE 7u /* Size of timer wheel (#Spokes) */
#define OS_TMR_CFG_TICKS_PER_SEC 10u /* Rate at which timer management task runs (Hz) */
#endif

1
src/APP/Aufgabe4/ps7/core0/cfg/os_cfg.h Symbolic link
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../../../../Aufgabe1/ps7/core0/cfg/os_cfg.h

681
src/APP/Aufgabe4/ps7/core0/cfg/xparameters.h
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/******************************************************************/
/* Definition for CPU ID */
#define XPAR_CPU_ID 0
/* Definitions for peripheral PS7_CORTEXA9_0 */
#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
#define XPAR_PS7_CORTEXA9_1_CPU_CLK_FREQ_HZ XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ
/******************************************************************/
/* Canonical definitions for peripheral PS7_CORTEXA9_0 */
#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
#define XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
/******************************************************************/
#undef DEF_DISABLED
#undef DEF_ENABLED
#define DEF_ENABLED 1
#define DEF_DISABLED 0
#include "xparameters_ps.h"
/******************************************************************/
/* Definitions for driver BRAM */
#define XPAR_XBRAM_NUM_INSTANCES 1
/* Definitions for peripheral AXI_BRAM_CTRL_0 */
#define XPAR_AXI_BRAM_CTRL_0_DEVICE_ID 0
#define XPAR_AXI_BRAM_CTRL_0_DATA_WIDTH 32
#define XPAR_AXI_BRAM_CTRL_0_ECC 0
#define XPAR_AXI_BRAM_CTRL_0_FAULT_INJECT 0
#define XPAR_AXI_BRAM_CTRL_0_CE_FAILING_REGISTERS 0
#define XPAR_AXI_BRAM_CTRL_0_UE_FAILING_REGISTERS 0
#define XPAR_AXI_BRAM_CTRL_0_ECC_STATUS_REGISTERS 0
#define XPAR_AXI_BRAM_CTRL_0_CE_COUNTER_WIDTH 0
#define XPAR_AXI_BRAM_CTRL_0_ECC_ONOFF_REGISTER 0
#define XPAR_AXI_BRAM_CTRL_0_ECC_ONOFF_RESET_VALUE 0
#define XPAR_AXI_BRAM_CTRL_0_WRITE_ACCESS 0
#define XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR 0x40000000
#define XPAR_AXI_BRAM_CTRL_0_S_AXI_HIGHADDR 0x40001FFF
#define XPAR_AXI_BRAM_CTRL_0_S_AXI_CTRL_BASEADDR 0xFFFFFFFF
#define XPAR_AXI_BRAM_CTRL_0_S_AXI_CTRL_HIGHADDR 0xFFFFFFFF
/******************************************************************/
/* Canonical definitions for peripheral AXI_BRAM_CTRL_0 */
#define XPAR_BRAM_0_DEVICE_ID XPAR_AXI_BRAM_CTRL_0_DEVICE_ID
#define XPAR_BRAM_0_DATA_WIDTH 32
#define XPAR_BRAM_0_ECC 0
#define XPAR_BRAM_0_FAULT_INJECT 0
#define XPAR_BRAM_0_CE_FAILING_REGISTERS 0
#define XPAR_BRAM_0_UE_FAILING_REGISTERS 0
#define XPAR_BRAM_0_ECC_STATUS_REGISTERS 0
#define XPAR_BRAM_0_CE_COUNTER_WIDTH 0
#define XPAR_BRAM_0_ECC_ONOFF_REGISTER 0
#define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 0
#define XPAR_BRAM_0_WRITE_ACCESS 0
#define XPAR_BRAM_0_BASEADDR 0x40000000
#define XPAR_BRAM_0_HIGHADDR 0x40001FFF
/******************************************************************/
/* Definitions for peripheral PS7_DDR_0 */
#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
/******************************************************************/
/* Definitions for driver DEVCFG */
#define XPAR_XDCFG_NUM_INSTANCES 1
/* Definitions for peripheral PS7_DEV_CFG_0 */
#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0
#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000
#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FF
/******************************************************************/
/* Canonical definitions for peripheral PS7_DEV_CFG_0 */
#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
#define XPAR_XDCFG_0_BASEADDR 0xF8007000
#define XPAR_XDCFG_0_HIGHADDR 0xF80070FF
/******************************************************************/
/* Definitions for driver DMAPS */
#define XPAR_XDMAPS_NUM_INSTANCES 2
/* Definitions for peripheral PS7_DMA_NS */
#define XPAR_PS7_DMA_NS_DEVICE_ID 0
#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF
/* Definitions for peripheral PS7_DMA_S */
#define XPAR_PS7_DMA_S_DEVICE_ID 1
#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF
/******************************************************************/
/* Canonical definitions for peripheral PS7_DMA_NS */
#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
#define XPAR_XDMAPS_0_BASEADDR 0xF8004000
#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF
/* Canonical definitions for peripheral PS7_DMA_S */
#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
#define XPAR_XDMAPS_1_BASEADDR 0xF8003000
#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF
/******************************************************************/
/* Definitions for peripheral PS7_AFI_0 */
#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
/* Definitions for peripheral PS7_AFI_1 */
#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000
#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF
/* Definitions for peripheral PS7_AFI_2 */
#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000
#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF
/* Definitions for peripheral PS7_AFI_3 */
#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000
#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
/* Definitions for peripheral PS7_DDRC_0 */
#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
/* Definitions for peripheral PS7_GLOBALTIMER_0 */
#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200
#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF
/* Definitions for peripheral PS7_GPV_0 */
#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000
#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF
/* Definitions for peripheral PS7_INTC_DIST_0 */
#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000
#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF
/* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
/* Definitions for peripheral PS7_OCMC_0 */
#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000
#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF
/* Definitions for peripheral PS7_PL310_0 */
#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000
#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF
/* Definitions for peripheral PS7_PMU_0 */
#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000
#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF
#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000
#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF
/* Definitions for peripheral PS7_QSPI_LINEAR_0 */
#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFDFFFFFF
/* Definitions for peripheral PS7_RAM_0 */
#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
/* Definitions for peripheral PS7_RAM_1 */
#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000
#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
/* Definitions for peripheral PS7_SLCR_0 */
#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF
/******************************************************************/
/* Definitions for driver GPIO */
#define XPAR_XGPIO_NUM_INSTANCES 1
/* Definitions for peripheral AXI_GPIO_0 */
#define XPAR_AXI_GPIO_0_BASEADDR 0x41200000
#define XPAR_AXI_GPIO_0_HIGHADDR 0x4120FFFF
#define XPAR_AXI_GPIO_0_DEVICE_ID 0
#define XPAR_AXI_GPIO_0_INTERRUPT_PRESENT 0
#define XPAR_AXI_GPIO_0_IS_DUAL 0
/******************************************************************/
/* Canonical definitions for peripheral AXI_GPIO_0 */
#define XPAR_GPIO_0_BASEADDR 0x41200000
#define XPAR_GPIO_0_HIGHADDR 0x4120FFFF
#define XPAR_GPIO_0_DEVICE_ID XPAR_AXI_GPIO_0_DEVICE_ID
#define XPAR_GPIO_0_INTERRUPT_PRESENT 0
#define XPAR_GPIO_0_IS_DUAL 0
/******************************************************************/
/* Definitions for driver GPIOPS */
#define XPAR_XGPIOPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_GPIO_0 */
#define XPAR_PS7_GPIO_0_DEVICE_ID 0
#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
/******************************************************************/
/* Canonical definitions for peripheral PS7_GPIO_0 */
#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
/******************************************************************/
///* Definitions for driver IICPS */
//#define XPAR_XIICPS_NUM_INSTANCES 1
//
///* Definitions for peripheral PS7_I2C_0 */
//#define XPAR_PS7_I2C_0_DEVICE_ID 0
//#define XPAR_PS7_I2C_0_BASEADDR 0xE0004000
//#define XPAR_PS7_I2C_0_HIGHADDR 0xE0004FFF
//#define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 111111115
/******************************************************************/
/* Canonical definitions for peripheral PS7_I2C_0 */
#define XPAR_XIICPS_0_DEVICE_ID XPAR_PS7_I2C_0_DEVICE_ID
#define XPAR_XIICPS_0_BASEADDR 0xE0004000
#define XPAR_XIICPS_0_HIGHADDR 0xE0004FFF
#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 111111115
/******************************************************************/
/* Definitions for driver QSPIPS */
#define XPAR_XQSPIPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_QSPI_0 */
#define XPAR_PS7_QSPI_0_DEVICE_ID 0
#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000
#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000
#define XPAR_PS7_QSPI_0_QSPI_MODE 2
/******************************************************************/
/* Canonical definitions for peripheral PS7_QSPI_0 */
#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID
#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000
#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000
#define XPAR_XQSPIPS_0_QSPI_MODE 2
/******************************************************************/
/* Definitions for driver SCUWDT */
#define XPAR_XSCUWDT_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SCUWDT_0 */
#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF
/******************************************************************/
/* Canonical definitions for peripheral PS7_SCUWDT_0 */
#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
/******************************************************************/
/* Definitions for driver UCOS_EMACPS */
#define XPAR_UCOS_EMACPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_ETHERNET_0 */
#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0
#define XPAR_PS7_ETHERNET_0_BASEADDR 0x00000000
#define XPAR_PS7_ETHERNET_0_HIGHADDR 0x00000000
#define XPAR_PS7_ETHERNET_0_CLOCK_FREQ_HZ 0
/******************************************************************/
/* Canonical definitions for peripheral PS7_ETHERNET_0 */
#define XPAR_UCOS_EMACPS_0_NUM_INSTANCES 0
#define XPAR_UCOS_EMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID
#define XPAR_UCOS_EMACPS_0_BASEADDR 0x00000000
#define XPAR_UCOS_EMACPS_0_HIGHADDR 0x00000000
#define XPAR_UCOS_EMACPS_0_CLOCK_FREQ_HZ 0
/******************************************************************/
/* Definitions for driver UCOS_L2CACHEC */
#define XPAR_UCOS_L2CACHEC_NUM_INSTANCES 1
/* Definitions for peripheral PS7_L2CACHEC_0 */
#define XPAR_PS7_L2CACHEC_0_DEVICE_ID 0
#define XPAR_PS7_L2CACHEC_0_BASEADDR 0xF8F02000
#define XPAR_PS7_L2CACHEC_0_HIGHADDR 0xF8F02FFF
/******************************************************************/
/* Definitions for driver UCOS_SCUC */
#define XPAR_UCOS_L2CACHEC_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SCUC_0 */
#define XPAR_PS7_SCUC_0_DEVICE_ID 0
#define XPAR_PS7_SCUC_0_BASEADDR 0xF8F00000
#define XPAR_PS7_SCUC_0_HIGHADDR 0xF8F000FC
/******************************************************************/
/***Definitions for Core_nIRQ/nFIQ interrupts ****/
/* Definitions for driver UCOS_SCUGIC */
#define XPAR_XSCUGIC_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SCUGIC_0 */
#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0
#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100
#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FF
#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000
/******************************************************************/
/* Canonical definitions for peripheral PS7_SCUGIC_0 */
#define XPAR_SCUGIC_0_DEVICE_ID 0
#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100
#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FF
#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000
/******************************************************************/
/* Definitions for driver UCOS_SCUTIMER */
#define XPAR_UCOS_SCUC_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SCUTIMER_0 */
#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F
/******************************************************************/
/* Definitions for driver UCOS_SDPS */
#define XPAR_UCOS_SDPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SD_0 */
#define XPAR_PS7_SD_0_DEVICE_ID 0
#define XPAR_PS7_SD_0_BASEADDR 0xE0100000
#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
/******************************************************************/
/* Canonical definitions for peripheral PS7_SD_0 */
#define XPAR_UCOS_SDPS_0_NUM_INSTANCES 0
#define XPAR_UCOS_SDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID
#define XPAR_UCOS_SDPS_0_BASEADDR 0xE0100000
#define XPAR_UCOS_SDPS_0_HIGHADDR 0xE0100FFF
#define XPAR_UCOS_SDPS_0_SDIO_CLK_FREQ_HZ 50000000
/******************************************************************/
///* Definitions for driver UCOS_TTCPS */
//#define XPAR_UCOS_TTCPS_NUM_INSTANCES 3
//
///* Definitions for peripheral PS7_TTC_0 */
//#define XPAR_PS7_TTC_0_DEVICE_ID 0
//#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000
//#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115
//#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0
//#define XPAR_PS7_TTC_1_DEVICE_ID 1
//#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004
//#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115
//#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0
//#define XPAR_PS7_TTC_2_DEVICE_ID 2
//#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008
//#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115
//#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0
/******************************************************************/
/* Definitions for driver UCOS_UARTPS */
#define XPAR_UCOS_UARTPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_UART_1 */
#define XPAR_PS7_UART_1_DEVICE_ID 0
#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 50000000
#define XPAR_PS7_UART_1_HAS_MODEM 0
/******************************************************************/
/* Canonical definitions for peripheral PS7_UART_1 */
#define XPAR_UCOS_UARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
#define XPAR_UCOS_UARTPS_0_BASEADDR 0xE0001000
#define XPAR_UCOS_UARTPS_0_HIGHADDR 0xE0001FFF
#define XPAR_UCOS_UARTPS_0_UART_CLK_FREQ_HZ 50000000
#define XPAR_UCOS_UARTPS_0_HAS_MODEM 0
/******************************************************************/
/* Definitions for driver UCOS_USBPS */
#define XPAR_UCOS_USBPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_USB_0 */
#define XPAR_PS7_USB_0_DEVICE_ID 0
#define XPAR_PS7_USB_0_BASEADDR 0xE0002000
#define XPAR_PS7_USB_0_HIGHADDR 0xE0002FFF
/******************************************************************/
/* Canonical definitions for peripheral PS7_USB_0 */
#define XPAR_UCOS_USBPS_0_DEVICE_ID XPAR_PS7_USB_0_DEVICE_ID
#define XPAR_UCOS_USBPS_0_BASEADDR 0xE0002000
#define XPAR_UCOS_USBPS_0_HIGHADDR 0xE0002FFF
/******************************************************************/
/* Definitions for driver XADCPS */
#define XPAR_XADCPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_XADC_0 */
#define XPAR_PS7_XADC_0_DEVICE_ID 0
#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100
#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120
/******************************************************************/
/* Canonical definitions for peripheral PS7_XADC_0 */
#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
#define XPAR_XADCPS_0_BASEADDR 0xF8007100
#define XPAR_XADCPS_0_HIGHADDR 0xF8007120
/******************************************************************/
//UCOS STDOUT
#define UCOS_STDOUT_DRIVER UCOS_UART_PS7_UART
#define UCOS_STDOUT_DEVICE_ID 0
#define STDOUT_BASEADDRESS
//UCOS Ethernet
#define UCOS_ETHERNET_DRIVER UCOS_ETHERNET_EMACPS
//UCOS TASK PARAMETERS
#define UCOS_START_TASK_PRIO 5
#define UCOS_START_TASK_STACK_SIZE 784
#define UCOS_START_DEBUG_TRACE DEF_ENABLED
#define NET_TASK_CFG_RX_PRIO 30
#define NET_TASK_CFG_RX_STACK_SIZE 3072
#define NET_TASK_CFG_TXDEALLOC_PRIO 6
#define NET_TASK_CFG_TXDEALLOC_STACK_SIZE 2048
#define NET_TASK_CFG_TMR_PRIO 18
#define NET_TASK_CFG_TMR_STACK_SIZE 2048
#define HTTPc_OS_CFG_TASK_PRIO 20
#define HTTPc_OS_CFG_TASK_STK_SIZE 2048
#define UCOS_HTTPc_OS_CFG_TASK_DELAY 1
#define UCOS_HTTPc_OS_CFG_MSG_Q_SIZE 5
#define UCOS_HTTPc_OS_CFG_TIMEOUT 2000
#define UCOS_HTTPc_OS_CFG_INACTIVITY_TIMEOUT 30
#define UCOS_AMP_MASTER DEF_ENABLED
#define UCOS_CFG_INIT_CAN DEF_ENABLED
#define UCOS_CFG_INIT_NET DEF_ENABLED
#define UCOS_CFG_INIT_FS DEF_DISABLED
#define UCOS_CFG_INIT_OPENAMP DEF_DISABLED
#define UCOS_CFG_INIT_USBD DEF_DISABLED
#define UCOS_CFG_INIT_USBH DEF_DISABLED
#define UCOS_ETHERNET_ADDRESS "10.10.110.2"
#define UCOS_ETHERNET_GATEWAY "10.10.110.1"
#define UCOS_ETHERNET_SUBMASK "255.255.255.0"
#define UCOS_ETHERNET_DHCP DEF_ENABLED
#define UCOS_IF_RX_BUF_NBR 12
#define UCOS_IF_TX_LARGE_BUF_NBR 8
#define UCOS_IF_TX_SMALL_BUF_NBR 8
#define UCOS_IF_RX_DESC_NBR 0
#define UCOS_IF_TX_DESC_NBR 0
#define UCOS_IF_DEDIC_MEM_ADDR 0
#define UCOS_IF_DEDIC_MEM_SIZE 0
#define UCOS_IF_HW_ADDR "50:E5:49:E6:8D:28"
#define UCOS_PHY_BUS_ADDR 255
#define UCOS_PHY_BUS_MODE UCOS_NET_PHY_BUS_MODE_GMII
#define UCOS_PHY_TYPE UCOS_NET_PHY_TYPE_INT
#define UCOS_PHY_SPEED UCOS_NET_PHY_SPD_AUTO
#define UCOS_PHY_DUPLEX UCOS_NET_PHY_DUPLEX_AUTO
#define UCOS_USB_DRIVER UCOS_USB_NONE
#define UCOS_USB_DEVICE_ID 0
#define UCOS_USB_TYPE UCOS_USB_TYPE_DEVICE
#define UCOS_RAMDISK_EN DEF_DISABLED
#define UCOS_RAMDISK_SIZE 128
#define UCOS_RAMDISK_SECTOR_SIZE 512
#define UCOS_RAMDISK_BASE_ADDRESS 0
#define UCOS_SDCARD_EN DEF_DISABLED
#define XPAR_PS7_ETHERNET_0_INT_SOURCE 54
#define XPAR_PS7_SD_0_INT_SOURCE 56
#define XPAR_PS7_UART_1_INT_SOURCE 82
#define XPAR_PS7_USB_0_INT_SOURCE 53
#define UCOS_ZYNQ_CONFIG_MMU DEF_DISABLED
#define UCOS_ZYNQ_ENABLE_MMU DEF_DISABLED
#define UCOS_ZYNQ_CONFIG_CACHES DEF_DISABLED
#define UCOS_ZYNQ_ENABLE_CACHES DEF_DISABLED
#define UCOS_ZYNQ_ENABLE_OPTIMS DEF_DISABLED
#define ZYNQ_ENABLE_EARLY_L1_I_EN DEF_DISABLED
#define ZYNQ_ENABLE_EARLY_L1_D_EN DEF_DISABLED
#define UCOS_CPU_TYPE UCOS_CPU_TYPE_PS7
//Parameters added by Kai Gemlau
#define UCOS_SMP_ENABLE DEF_DISABLED
/******************************************************************/
/* Definitions for driver TTCPS */
#define XPAR_XTTCPS_NUM_INSTANCES 3U
/* Definitions for peripheral PS7_TTC_0 */
#define XPAR_PS7_TTC_0_DEVICE_ID 0U
#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000U
#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115U
#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0U
#define XPAR_PS7_TTC_1_DEVICE_ID 1U
#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004U
#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115U
#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0U
#define XPAR_PS7_TTC_2_DEVICE_ID 2U
#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008U
#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115U
#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0U
/******************************************************************/
/* Canonical definitions for peripheral PS7_TTC_0 */
#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PS7_TTC_0_DEVICE_ID
#define XPAR_XTTCPS_0_BASEADDR 0xF8001000U
#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 111111115U
#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0U
#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PS7_TTC_1_DEVICE_ID
#define XPAR_XTTCPS_1_BASEADDR 0xF8001004U
#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 111111115U
#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0U
#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PS7_TTC_2_DEVICE_ID
#define XPAR_XTTCPS_2_BASEADDR 0xF8001008U
#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 111111115U
#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0U
/******************************************************************/
/* Definitions for driver GPIOPS */
#define XPAR_XGPIOPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_GPIO_0 */
#define XPAR_PS7_GPIO_0_DEVICE_ID 0
#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
/******************************************************************/
/* Canonical definitions for peripheral PS7_GPIO_0 */
#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
/******************************************************************/
/* Definitions for driver IICPS */
#define XPAR_XIICPS_NUM_INSTANCES 2
/* Definitions for peripheral PS7_I2C_0 */
#define XPAR_PS7_I2C_0_DEVICE_ID 0
#define XPAR_PS7_I2C_0_BASEADDR 0xE0004000
#define XPAR_PS7_I2C_0_HIGHADDR 0xE0004FFF
#define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 111111115
/* Definitions for peripheral PS7_I2C_1 */
#define XPAR_PS7_I2C_1_DEVICE_ID 1
#define XPAR_PS7_I2C_1_BASEADDR 0xE0005000
#define XPAR_PS7_I2C_1_HIGHADDR 0xE0005FFF
#define XPAR_PS7_I2C_1_I2C_CLK_FREQ_HZ 111111115
/******************************************************************/
/* Canonical definitions for peripheral PS7_I2C_0 */
#define XPAR_XIICPS_0_DEVICE_ID XPAR_PS7_I2C_0_DEVICE_ID
#define XPAR_XIICPS_0_BASEADDR 0xE0004000
#define XPAR_XIICPS_0_HIGHADDR 0xE0004FFF
#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 111111115
/* Canonical definitions for peripheral PS7_I2C_1 */
#define XPAR_XIICPS_1_DEVICE_ID XPAR_PS7_I2C_1_DEVICE_ID
#define XPAR_XIICPS_1_BASEADDR 0xE0005000
#define XPAR_XIICPS_1_HIGHADDR 0xE0005FFF
#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 111111115
/******************************************************************/

1
src/APP/Aufgabe4/ps7/core0/cfg/xparameters.h Symbolic link
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../../../../Aufgabe1/ps7/core0/cfg/xparameters.h

325
src/APP/Aufgabe4/ps7/core0/cfg/xparameters_ps.h
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/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xparameters_ps.h
*
* This file contains the address definitions for the hard peripherals
* attached to the ARM Cortex A9 core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------- -------- ---------------------------------------------------
* 1.00a ecm/sdm 02/01/10 Initial version
* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
* driver tcl
* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#ifndef _XPARAMETERS_PS_H_
#define _XPARAMETERS_PS_H_
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions *****************************/
/*
* This block contains constant declarations for the peripherals
* within the hardblock
*/
/* Canonical definitions for DDR MEMORY */
#define XPAR_DDR_MEM_BASEADDR 0x00000000U
#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
/* Canonical definitions for Interrupts */
#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID
#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID
#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID
#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID
#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID
#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID
#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR
#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR
/* Canonical definitions for DMAC */
/* Canonical definitions for WDT */
/* Canonical definitions for SLCR */
#define XPAR_XSLCR_NUM_INSTANCES 1U
#define XPAR_XSLCR_0_DEVICE_ID 0U
#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR
/* Canonical definitions for SCU GIC */
#define XPAR_SCUGIC_NUM_INSTANCES 1U
#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000100U)
#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
#define XPAR_SCUGIC_ACK_BEFORE 0U
/* Canonical definitions for Global Timer */
#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U
#define XPAR_GLOBAL_TMR_DEVICE_ID 0U
#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U)
#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID
/* Xilinx Parallel Flash Library (XilFlash) User Settings */
#define XPAR_AXI_EMC
#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
/*
* This block contains constant declarations for the peripherals
* within the hardblock. These have been put for bacwards compatibilty
*/
#define XPS_PERIPHERAL_BASEADDR 0xE0000000U
#define XPS_UART0_BASEADDR 0xE0000000U
#define XPS_UART1_BASEADDR 0xE0001000U
#define XPS_USB0_BASEADDR 0xE0002000U
#define XPS_USB1_BASEADDR 0xE0003000U
#define XPS_I2C0_BASEADDR 0xE0004000U
#define XPS_I2C1_BASEADDR 0xE0005000U
#define XPS_SPI0_BASEADDR 0xE0006000U
#define XPS_SPI1_BASEADDR 0xE0007000U
#define XPS_CAN0_BASEADDR 0xE0008000U
#define XPS_CAN1_BASEADDR 0xE0009000U
#define XPS_GPIO_BASEADDR 0xE000A000U
#define XPS_GEM0_BASEADDR 0xE000B000U
#define XPS_GEM1_BASEADDR 0xE000C000U
#define XPS_QSPI_BASEADDR 0xE000D000U
#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000U
#define XPS_SDIO0_BASEADDR 0xE0100000U
#define XPS_SDIO1_BASEADDR 0xE0101000U
#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U
#define XPS_NAND_BASEADDR 0xE1000000U
#define XPS_PARPORT0_BASEADDR 0xE2000000U
#define XPS_PARPORT1_BASEADDR 0xE4000000U
#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000U
#define XPS_SYS_CTRL_BASEADDR 0xF8000000U /* AKA SLCR */
#define XPS_TTC0_BASEADDR 0xF8001000U
#define XPS_TTC1_BASEADDR 0xF8002000U
#define XPS_DMAC0_SEC_BASEADDR 0xF8003000U
#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000U
#define XPS_WDT_BASEADDR 0xF8005000U
#define XPS_DDR_CTRL_BASEADDR 0xF8006000U
#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U
#define XPS_AFI0_BASEADDR 0xF8008000U
#define XPS_AFI1_BASEADDR 0xF8009000U
#define XPS_AFI2_BASEADDR 0xF800A000U
#define XPS_AFI3_BASEADDR 0xF800B000U
#define XPS_OCM_BASEADDR 0xF800C000U
#define XPS_EFUSE_BASEADDR 0xF800D000U
#define XPS_CORESIGHT_BASEADDR 0xF8800000U
#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U
#define XPS_SCU_PERIPH_BASE 0xF8F00000U
#define XPS_L2CC_BASEADDR 0xF8F02000U
#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U
#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U
#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U
#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U
#define XPS_PERIPH_APB_BASEADDR 0xF8000000U
/* Shared Peripheral Interrupts (SPI) */
#define XPS_CORE_PARITY0_INT_ID 32U
#define XPS_CORE_PARITY1_INT_ID 33U
#define XPS_L2CC_INT_ID 34U
#define XPS_OCMINTR_INT_ID 35U
#define XPS_ECC_INT_ID 36U
#define XPS_PMU0_INT_ID 37U
#define XPS_PMU1_INT_ID 38U
#define XPS_SYSMON_INT_ID 39U
#define XPS_DVC_INT_ID 40U
#define XPS_WDT_INT_ID 41U
#define XPS_TTC0_0_INT_ID 42U
#define XPS_TTC0_1_INT_ID 43U
#define XPS_TTC0_2_INT_ID 44U
#define XPS_DMA0_ABORT_INT_ID 45U
#define XPS_DMA0_INT_ID 46U
#define XPS_DMA1_INT_ID 47U
#define XPS_DMA2_INT_ID 48U
#define XPS_DMA3_INT_ID 49U
#define XPS_SMC_INT_ID 50U
#define XPS_QSPI_INT_ID 51U
#define XPS_GPIO_INT_ID 52U
#define XPS_USB0_INT_ID 53U
#define XPS_GEM0_INT_ID 54U
#define XPS_GEM0_WAKE_INT_ID 55U
#define XPS_SDIO0_INT_ID 56U
#define XPS_I2C0_INT_ID 57U
#define XPS_SPI0_INT_ID 58U
#define XPS_UART0_INT_ID 59U
#define XPS_CAN0_INT_ID 60U
#define XPS_FPGA0_INT_ID 61U
#define XPS_FPGA1_INT_ID 62U
#define XPS_FPGA2_INT_ID 63U
#define XPS_FPGA3_INT_ID 64U
#define XPS_FPGA4_INT_ID 65U
#define XPS_FPGA5_INT_ID 66U
#define XPS_FPGA6_INT_ID 67U
#define XPS_FPGA7_INT_ID 68U
#define XPS_TTC1_0_INT_ID 69U
#define XPS_TTC1_1_INT_ID 70U
#define XPS_TTC1_2_INT_ID 71U
#define XPS_DMA4_INT_ID 72U
#define XPS_DMA5_INT_ID 73U
#define XPS_DMA6_INT_ID 74U
#define XPS_DMA7_INT_ID 75U
#define XPS_USB1_INT_ID 76U
#define XPS_GEM1_INT_ID 77U
#define XPS_GEM1_WAKE_INT_ID 78U
#define XPS_SDIO1_INT_ID 79U
#define XPS_I2C1_INT_ID 80U
#define XPS_SPI1_INT_ID 81U
#define XPS_UART1_INT_ID 82U
#define XPS_CAN1_INT_ID 83U
#define XPS_FPGA8_INT_ID 84U
#define XPS_FPGA9_INT_ID 85U
#define XPS_FPGA10_INT_ID 86U
#define XPS_FPGA11_INT_ID 87U
#define XPS_FPGA12_INT_ID 88U
#define XPS_FPGA13_INT_ID 89U
#define XPS_FPGA14_INT_ID 90U
#define XPS_FPGA15_INT_ID 91U
/* Private Peripheral Interrupts (PPI) */
#define XPS_GLOBAL_TMR_INT_ID 27U /* SCU Global Timer interrupt */
#define XPS_FIQ_INT_ID 28U /* FIQ from FPGA fabric */
#define XPS_SCU_TMR_INT_ID 29U /* SCU Private Timer interrupt */
#define XPS_SCU_WDT_INT_ID 30U /* SCU Private WDT interrupt */
#define XPS_IRQ_INT_ID 31U /* IRQ from FPGA fabric */
/* REDEFINES for TEST APP */
/* Definitions for UART */
#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID
#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID
#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID
#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID
#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID
#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID
#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID
#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID
#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID
#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID
#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID
#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID
#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID
#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID
#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID
#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
#define XPAR_PS7_TTC_0_INTR XPS_TTC0_0_INT_ID
#define XPAR_PS7_TTC_1_INTR XPS_TTC0_1_INT_ID
#define XPAR_PS7_TTC_2_INTR XPS_TTC0_2_INT_ID
#define XPAR_PS7_TTC_3_INTR XPS_TTC1_0_INT_ID
#define XPAR_PS7_TTC_4_INTR XPS_TTC1_1_INT_ID
#define XPAR_PS7_TTC_5_INTR XPS_TTC1_2_INT_ID
#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
/* For backwards compatibilty */
#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
#define XPAR_SCUTIMER_DEVICE_ID 0U
#define XPAR_SCUWDT_DEVICE_ID 0U
#ifdef __cplusplus
}
#endif
#endif /* protection macro */

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src/APP/Aufgabe4/ps7/core0/cfg/xparameters_ps.h Symbolic link
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../../../../Aufgabe1/ps7/core0/cfg/xparameters_ps.h

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src/APP/Aufgabe4/ps7/core0/linker/lscript.ld
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/*******************************************************************/
/* */
/* This file is automatically generated by linker script generator.*/
/* */
/* Version: */
/* */
/* Copyright (c) 2010-2016 Xilinx, Inc. All rights reserved. */
/* */
/* Description : Cortex-A9 Linker Script */
/* */
/*******************************************************************/
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
/* Define Memories in the system */
MEMORY
{
axi_bram_ctrl_0_Mem0 : ORIGIN = 0x40000000, LENGTH = 0x2000
ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x3FF00000
ps7_qspi_linear_0 : ORIGIN = 0xFC000000, LENGTH = 0x2000000
ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000
ps7_ram_1 : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00
ps7_ddr_core_0 : ORIGIN = 0x100000, LENGTH = 0x700000
ps7_ddr_core_1 : ORIGIN = 0x800000, LENGTH = 0x800000
}
/* Specify the default entry point to the program */
ENTRY(_vector_table)
/* Define the sections, and where they are mapped in memory */
SECTIONS
{
.text : {
KEEP (*(.vectors))
*(.boot)
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
*(.plt)
*(.gnu_warning)
*(.gcc_execpt_table)
*(.glue_7)
*(.glue_7t)
*(.vfp11_veneer)
*(.ARM.extab)
*(.gnu.linkonce.armextab.*)
} > ps7_ddr_core_0
.init : {
KEEP (*(.init))
} > ps7_ddr_core_0
.fini : {
KEEP (*(.fini))
} > ps7_ddr_core_0
.rodata : {
__rodata_start = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
__rodata_end = .;
} > ps7_ddr_core_0
.rodata1 : {
__rodata1_start = .;
*(.rodata1)
*(.rodata1.*)
__rodata1_end = .;
} > ps7_ddr_core_0
.sdata2 : {
__sdata2_start = .;
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
__sdata2_end = .;
} > ps7_ddr_core_0
.sbss2 : {
__sbss2_start = .;
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
__sbss2_end = .;
} > ps7_ddr_core_0
.data : {
__data_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.jcr)
*(.got)
*(.got.plt)
__data_end = .;
} > ps7_ddr_core_0
.data1 : {
__data1_start = .;
*(.data1)
*(.data1.*)
__data1_end = .;
} > ps7_ddr_core_0
.got : {
*(.got)
} > ps7_ddr_core_0
.ctors : {
__CTOR_LIST__ = .;
___CTORS_LIST___ = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
___CTORS_END___ = .;
} > ps7_ddr_core_0
.dtors : {
__DTOR_LIST__ = .;
___DTORS_LIST___ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
___DTORS_END___ = .;
} > ps7_ddr_core_0
.fixup : {
__fixup_start = .;
*(.fixup)
__fixup_end = .;
} > ps7_ddr_core_0
.eh_frame : {
*(.eh_frame)
} > ps7_ddr_core_0
.eh_framehdr : {
__eh_framehdr_start = .;
*(.eh_framehdr)
__eh_framehdr_end = .;
} > ps7_ddr_core_0
.gcc_except_table : {
*(.gcc_except_table)
} > ps7_ddr_core_0
.mmu_tbl (ALIGN(16384)) : {
__mmu_tbl_start = .;
*(.mmu_tbl)
__mmu_tbl_end = .;
} > ps7_ddr_core_0
.ARM.exidx : {
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidix.*.*)
__exidx_end = .;
} > ps7_ddr_core_0
.preinit_array : {
__preinit_array_start = .;
KEEP (*(SORT(.preinit_array.*)))
KEEP (*(.preinit_array))
__preinit_array_end = .;
} > ps7_ddr_core_0
.init_array : {
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
} > ps7_ddr_core_0
.fini_array : {
__fini_array_start = .;
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array))
__fini_array_end = .;
} > ps7_ddr_core_0
.ARM.attributes : {
__ARM.attributes_start = .;
*(.ARM.attributes)
__ARM.attributes_end = .;
} > ps7_ddr_core_0
.sdata : {
__sdata_start = .;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
__sdata_end = .;
} > ps7_ddr_core_0
.sbss (NOLOAD) : {
__sbss_start = .;
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
__sbss_end = .;
} > ps7_ddr_core_0
.tdata : {
__tdata_start = .;
*(.tdata)
*(.tdata.*)
*(.gnu.linkonce.td.*)
__tdata_end = .;
} > ps7_ddr_core_0
.tbss : {
__tbss_start = .;
*(.tbss)
*(.tbss.*)
*(.gnu.linkonce.tb.*)
__tbss_end = .;
} > ps7_ddr_core_0
.bss (NOLOAD) : {
__bss_start = .;
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
__bss_end = .;
} > ps7_ddr_core_0
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
/* Generate Stack and Heap definitions */
.heap (NOLOAD) : {
. = ALIGN(16);
_heap = .;
HeapBase = .;
_heap_start = .;
. += _HEAP_SIZE;
_heap_end = .;
HeapLimit = .;
} > ps7_ddr_core_0
.stack (NOLOAD) : {
. = ALIGN(16);
_stack_end = .;
. += _STACK_SIZE;
. = ALIGN(16);
_stack = .;
__stack = _stack;
. = ALIGN(16);
_irq_stack_end = .;
. += _IRQ_STACK_SIZE;
. = ALIGN(16);
__irq_stack = .;
_supervisor_stack_end = .;
. += _SUPERVISOR_STACK_SIZE;
. = ALIGN(16);
__supervisor_stack = .;
_abort_stack_end = .;
. += _ABORT_STACK_SIZE;
. = ALIGN(16);
__abort_stack = .;
_fiq_stack_end = .;
. += _FIQ_STACK_SIZE;
. = ALIGN(16);
__fiq_stack = .;
_undef_stack_end = .;
. += _UNDEF_STACK_SIZE;
. = ALIGN(16);
__undef_stack = .;
} > ps7_ddr_core_0
_end = .;
}

1
src/APP/Aufgabe4/ps7/core0/linker/lscript.ld Symbolic link
View File

@@ -0,0 +1 @@
../../../../Aufgabe1/ps7/core0/linker/lscript.ld

262
src/APP/Aufgabe4/ps7/core0/src/app_hooks.c
View File

@@ -1,262 +0,0 @@
/*
*********************************************************************************************************
* EXAMPLE CODE
*
* This file is provided as an example on how to use Micrium products.
*
* Please feel free to use any application code labeled as 'EXAMPLE CODE' in
* your application products. Example code may be used as is, in whole or in
* part, or may be used as a reference only. This file can be modified as
* required to meet the end-product requirements.
*
* Please help us continue to provide the Embedded community with the finest
* software available. Your honesty is greatly appreciated.
*
* You can find our product's user manual, API reference, release notes and
* more information at https://doc.micrium.com.
* You can contact us at www.micrium.com.
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* uC/OS-II
* Application Hooks
*
* Filename : app_hooks.c
* Version : V1.00
* Programmer(s) : FT
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* INCLUDE FILES
*********************************************************************************************************
*/
#include <ucos_ii.h>
/*
*********************************************************************************************************
* EXTERN GLOBAL VARIABLES
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* LOCAL CONSTANTS
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* LOCAL DATA TYPES
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* LOCAL TABLES
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* LOCAL GLOBAL VARIABLES
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* LOCAL FUNCTION PROTOTYPES
*********************************************************************************************************
*/
/*
**********************************************************************************************************
**********************************************************************************************************
** GLOBAL FUNCTIONS
**********************************************************************************************************
**********************************************************************************************************
*/
/*
*********************************************************************************************************
*********************************************************************************************************
** uC/OS-II APP HOOKS
*********************************************************************************************************
*********************************************************************************************************
*/
#if (OS_APP_HOOKS_EN > 0)
/*
*********************************************************************************************************
* TASK CREATION HOOK (APPLICATION)
*
* Description : This function is called when a task is created.
*
* Argument(s) : ptcb is a pointer to the task control block of the task being created.
*
* Note(s) : (1) Interrupts are disabled during this call.
*********************************************************************************************************
*/
void App_TaskCreateHook (OS_TCB *ptcb)
{
#if (APP_CFG_PROBE_OS_PLUGIN_EN == DEF_ENABLED) && (OS_PROBE_HOOKS_EN > 0)
OSProbe_TaskCreateHook(ptcb);
#endif
}
/*
*********************************************************************************************************
* TASK DELETION HOOK (APPLICATION)
*
* Description : This function is called when a task is deleted.
*
* Argument(s) : ptcb is a pointer to the task control block of the task being deleted.
*
* Note(s) : (1) Interrupts are disabled during this call.
*********************************************************************************************************
*/
void App_TaskDelHook (OS_TCB *ptcb)
{
(void)ptcb;
}
/*
*********************************************************************************************************
* IDLE TASK HOOK (APPLICATION)
*
* Description : This function is called by OSTaskIdleHook(), which is called by the idle task. This hook
* has been added to allow you to do such things as STOP the CPU to conserve power.
*
* Argument(s) : none.
*
* Note(s) : (1) Interrupts are enabled during this call.
*********************************************************************************************************
*/
#if OS_VERSION >= 251
void App_TaskIdleHook (void)
{
__asm volatile( "dsb" );
__asm volatile( "wfi" );
__asm volatile( "isb" );
}
#endif
/*
*********************************************************************************************************
* STATISTIC TASK HOOK (APPLICATION)
*
* Description : This function is called by OSTaskStatHook(), which is called every second by uC/OS-II's
* statistics task. This allows your application to add functionality to the statistics task.
*
* Argument(s) : none.
*********************************************************************************************************
*/
void App_TaskStatHook (void)
{
}
/*
*********************************************************************************************************
* TASK RETURN HOOK (APPLICATION)
*
* Description: This function is called if a task accidentally returns. In other words, a task should
* either be an infinite loop or delete itself when done.
*
* Arguments : ptcb is a pointer to the task control block of the task that is returning.
*
* Note(s) : none
*********************************************************************************************************
*/
#if OS_VERSION >= 289
void App_TaskReturnHook (OS_TCB *ptcb)
{
(void)ptcb;
}
#endif
/*
*********************************************************************************************************
* TASK SWITCH HOOK (APPLICATION)
*
* Description : This function is called when a task switch is performed. This allows you to perform other
* operations during a context switch.
*
* Argument(s) : none.
*
* Note(s) : (1) Interrupts are disabled during this call.
*
* (2) It is assumed that the global pointer 'OSTCBHighRdy' points to the TCB of the task that
* will be 'switched in' (i.e. the highest priority task) and, 'OSTCBCur' points to the
* task being switched out (i.e. the preempted task).
*********************************************************************************************************
*/
#if OS_TASK_SW_HOOK_EN > 0
void App_TaskSwHook (void)
{
#if (APP_CFG_PROBE_OS_PLUGIN_EN > 0) && (OS_PROBE_HOOKS_EN > 0)
OSProbe_TaskSwHook();
#endif
}
#endif
/*
*********************************************************************************************************
* OS_TCBInit() HOOK (APPLICATION)
*
* Description : This function is called by OSTCBInitHook(), which is called by OS_TCBInit() after setting
* up most of the TCB.
*
* Argument(s) : ptcb is a pointer to the TCB of the task being created.
*
* Note(s) : (1) Interrupts may or may not be ENABLED during this call.
*********************************************************************************************************
*/
#if OS_VERSION >= 204
void App_TCBInitHook (OS_TCB *ptcb)
{
(void)ptcb;
}
#endif
/*
*********************************************************************************************************
* TICK HOOK (APPLICATION)
*
* Description : This function is called every tick.
*
* Argument(s) : none.
*
* Note(s) : (1) Interrupts may or may not be ENABLED during this call.
*********************************************************************************************************
*/
#if OS_TIME_TICK_HOOK_EN > 0
void App_TimeTickHook (void)
{
#if (APP_CFG_PROBE_OS_PLUGIN_EN == DEF_ENABLED) && (OS_PROBE_HOOKS_EN > 0)
OSProbe_TickHook();
#endif
}
#endif
#endif

1
src/APP/Aufgabe4/ps7/core0/src/app_hooks.c Symbolic link
View File

@@ -0,0 +1 @@
../../../../Aufgabe2/ps7/core0/src/app_hooks.c

17
src/APP/Aufgabe4/ps7/core0/src/uartps_cfg.c
View File

@@ -1,17 +0,0 @@
#include "ucos_uartps.h"
#include "xparameters.h"
#include "xparameters_ps.h"
/*
* The uart configuration table for devices
*/
UCOS_UARTPS_Config UCOS_UARTPS_ConfigTable[] = {
{
XPAR_PS7_UART_1_DEVICE_ID,
XPAR_PS7_UART_1_BASEADDR,
XPAR_PS7_UART_1_UART_CLK_FREQ_HZ,
XPAR_PS7_UART_1_HAS_MODEM,
XPAR_PS7_UART_1_INT_SOURCE
}
};

1
src/APP/Aufgabe4/ps7/core0/src/uartps_cfg.c Symbolic link
View File

@@ -0,0 +1 @@
../../../../Aufgabe1/ps7/core0/src/uartps_cfg.c

56
src/APP/Aufgabe4/ps7/core0/src/xgpiops_g.c
View File

@@ -1,56 +0,0 @@
/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
*(a) running on a Xilinx device, or
*(b) that interact with a Xilinx device through a bus or interconnect.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Driver configuration
*
*******************************************************************/
#include "xparameters.h"
#include "xparameters_ps.h"
#include "xgpiops.h"
/*
* The configuration table for devices
*/
XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES] =
{
{
XPAR_PS7_GPIO_0_DEVICE_ID,
XPAR_PS7_GPIO_0_BASEADDR
}
};

111
src/APP/Aufgabe4/ps7/core0/src/xttcps_g.c
View File

@@ -1,111 +0,0 @@
/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
*(a) running on a Xilinx device, or
*(b) that interact with a Xilinx device through a bus or interconnect.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Driver configuration
*
*******************************************************************/
#include "xparameters_ps.h"
#include "xparameters.h"
#include "xttcps.h"
/*
* The configuration table for devices
*/
XTtcPs_Config XTtcPs_ConfigTable[] =
{
{
XPAR_PS7_TTC_0_DEVICE_ID,
XPAR_PS7_TTC_0_BASEADDR,
XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ
},
{
XPAR_PS7_TTC_1_DEVICE_ID,
XPAR_PS7_TTC_1_BASEADDR,
XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ
},
{
XPAR_PS7_TTC_2_DEVICE_ID,
XPAR_PS7_TTC_2_BASEADDR,
XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ
}//,
// {
// XPAR_PS7_TTC_3_DEVICE_ID,
// XPAR_PS7_TTC_3_BASEADDR,
// XPAR_PS7_TTC_3_TTC_CLK_FREQ_HZ
// },
// {
// XPAR_PS7_TTC_4_DEVICE_ID,
// XPAR_PS7_TTC_4_BASEADDR,
// XPAR_PS7_TTC_4_TTC_CLK_FREQ_HZ
// },
// {
// XPAR_PS7_TTC_5_DEVICE_ID,
// XPAR_PS7_TTC_5_BASEADDR,
// XPAR_PS7_TTC_5_TTC_CLK_FREQ_HZ
// },
// {
// XPAR_PS7_TTC_6_DEVICE_ID,
// XPAR_PS7_TTC_6_BASEADDR,
// XPAR_PS7_TTC_6_TTC_CLK_FREQ_HZ
// },
// {
// XPAR_PS7_TTC_7_DEVICE_ID,
// XPAR_PS7_TTC_7_BASEADDR,
// XPAR_PS7_TTC_7_TTC_CLK_FREQ_HZ
// },
// {
// XPAR_PS7_TTC_8_DEVICE_ID,
// XPAR_PS7_TTC_8_BASEADDR,
// XPAR_PS7_TTC_8_TTC_CLK_FREQ_HZ
// },
// {
// XPAR_PS7_TTC_9_DEVICE_ID,
// XPAR_PS7_TTC_9_BASEADDR,
// XPAR_PS7_TTC_9_TTC_CLK_FREQ_HZ
// },
// {
// XPAR_PS7_TTC_10_DEVICE_ID,
// XPAR_PS7_TTC_10_BASEADDR,
// XPAR_PS7_TTC_10_TTC_CLK_FREQ_HZ
// },
// {
// XPAR_PS7_TTC_11_DEVICE_ID,
// XPAR_PS7_TTC_11_BASEADDR,
// XPAR_PS7_TTC_11_TTC_CLK_FREQ_HZ
// }
};

1
src/APP/Aufgabe6/ps7/core0/build/config.mk
View File

@@ -1,6 +1,5 @@
#µController dependent flags
MCFLAGS =-mcpu=cortex-a9 -march=armv7-a -mthumb -mthumb-interwork -mfloat-abi=softfp -mfpu=neon
#Optimization
OPTIMIZE=-O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections

52
src/APP/Aufgabe6/ps7/core0/build/includes.mk
View File

@@ -1,52 +0,0 @@
INC += -I"$(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/cfg/"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Ports/ARM-Cortex-A/Generic/GNU/"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/ARM-Cortex-A/GNU/"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-Common"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Source"
INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-LIB"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/bsp/src/ipi"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/bsp/src/"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/bsp/src/$(ARCH)/"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_cpu_cortexa9/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_scugic/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_l2cachec/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_uartps/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_emacps/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_scuc/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_ttcps/src"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/cortexa9"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/cortexa9/gcc"
INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/common"
INC += -I"$(SRC_DIR)/Xilinx/libsrc/ipipsu_v2_3/src/"
INC += -I"$(SRC_DIR)/Modules/MMU"
INC += -I"$(SRC_DIR)/Xilinx/libsrc/ipipsu_v2_3/src/"
#scugic.h fix
INC += -I"$(SRC_DIR)/Xilinx/libsrc/scugic_v3_9/src/"
#uart includes
INC += -I"$(SRC_DIR)/Xilinx/libsrc/uartps_v3_6/src/"
#xttcps includes
INC += -I"$(SRC_DIR)/Xilinx/libsrc/ttcps_v3_5/src/"
#gpio includes
INC += -I"$(SRC_DIR)/Xilinx/libsrc/gpiops_v3_3/src/"
#I2C includes
INC += -I"$(SRC_DIR)/Xilinx/libsrc/iicps_v3_6/src/"
#task set includes
INC += -I"$(SRC_DIR)/Modules/genericTaskset/if"

1
src/APP/Aufgabe6/ps7/core0/build/includes.mk Symbolic link
View File

@@ -0,0 +1 @@
../../../../Aufgabe1/ps7/core0/build/includes.mk

7
src/APP/Aufgabe6/ps7/core0/build/sources.mk
View File

@@ -8,15 +8,13 @@ SRC += $(SRC_DIR)/ucos_v1_42/ucos/bsp/src/$(ARCH)/asm_vectors.S
SRC += $(SRC_DIR)/ucos_v1_42/ucos/components/ucos_osii/src/bsp/$(ARCH)/ucos_osii_bsp.c
SRC += $(SRC_DIR)/ucos_v1_42/ucos/components/ucos_common/src/$(ARCH)/cpu_bsp.c
SRC += $(SRC_DIR)/Modules/MMU/mmu.c
SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/main.c
SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/app_hooks.c
SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/uartps_cfg.c
SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/gt_tasks.c
SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/xttcps_g.c
SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/xgpiops_g.c
SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/xiicps_g.c
SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Ports/ARM-Cortex-A/Generic/GNU/os_cpu_a_vfp-d32.S
SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Ports/ARM-Cortex-A/Generic/GNU/os_cpu_c.c
@@ -43,9 +41,6 @@ SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-Common/Auth/auth.c
-include $(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Source/subdir.mk
#mmu
SRC += $(SRC_DIR)/Modules/MMU/mmu.c
#src for triple timer counter
SRC +=$(SRC_DIR)/Xilinx/libsrc/ttcps_v3_5/src/xttcps.c

216
src/APP/Aufgabe6/ps7/core0/cfg/cpu_cfg.h
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@@ -1,216 +0,0 @@
/*
*********************************************************************************************************
* uC/CPU
* CPU CONFIGURATION & PORT LAYER
*
* (c) Copyright 2004-2015; Micrium, Inc.; Weston, FL
*
* All rights reserved. Protected by international copyright laws.
*
* uC/CPU is provided in source form to registered licensees ONLY. It is
* illegal to distribute this source code to any third party unless you receive
* written permission by an authorized Micrium representative. Knowledge of
* the source code may NOT be used to develop a similar product.
*
* Please help us continue to provide the Embedded community with the finest
* software available. Your honesty is greatly appreciated.
*
* You can find our product's user manual, API reference, release notes and
* more information at https://doc.micrium.com.
* You can contact us at www.micrium.com.
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* CPU CONFIGURATION FILE
*
* TEMPLATE
*
* Filename : cpu_cfg.h
* Version : V1.30.02
* Programmer(s) : SR
* ITJ
* JBL
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* MODULE
*********************************************************************************************************
*/
#ifndef CPU_CFG_MODULE_PRESENT
#define CPU_CFG_MODULE_PRESENT
/*
*********************************************************************************************************
* CPU NAME CONFIGURATION
*
* Note(s) : (1) Configure CPU_CFG_NAME_EN to enable/disable CPU host name feature :
*
* (a) CPU host name storage
* (b) CPU host name API functions
*
* (2) Configure CPU_CFG_NAME_SIZE with the desired ASCII string size of the CPU host name,
* including the terminating NULL character.
*
* See also 'cpu_core.h GLOBAL VARIABLES Note #1'.
*********************************************************************************************************
*/
/* Configure CPU host name feature (see Note #1) : */
#define CPU_CFG_NAME_EN DEF_DISABLED
/* DEF_DISABLED CPU host name DISABLED */
/* DEF_ENABLED CPU host name ENABLED */
/* Configure CPU host name ASCII string size ... */
#define CPU_CFG_NAME_SIZE 16
/*
*********************************************************************************************************
* CPU TIMESTAMP CONFIGURATION
*
* Note(s) : (1) Configure CPU_CFG_TS_xx_EN to enable/disable CPU timestamp features :
*
* (a) CPU_CFG_TS_32_EN enable/disable 32-bit CPU timestamp feature
* (b) CPU_CFG_TS_64_EN enable/disable 64-bit CPU timestamp feature
*
* (2) (a) Configure CPU_CFG_TS_TMR_SIZE with the CPU timestamp timer's word size :
*
* CPU_WORD_SIZE_08 8-bit word size
* CPU_WORD_SIZE_16 16-bit word size
* CPU_WORD_SIZE_32 32-bit word size
* CPU_WORD_SIZE_64 64-bit word size
*
* (b) If the size of the CPU timestamp timer is not a binary multiple of 8-bit octets
* (e.g. 20-bits or even 24-bits), then the next lower, binary-multiple octet word
* size SHOULD be configured (e.g. to 16-bits). However, the minimum supported word
* size for CPU timestamp timers is 8-bits.
*
* See also 'cpu_core.h FUNCTION PROTOTYPES CPU_TS_TmrRd() Note #2a'.
*********************************************************************************************************
*/
/* Configure CPU timestamp features (see Note #1) : */
#define CPU_CFG_TS_32_EN DEF_ENABLED
#define CPU_CFG_TS_64_EN DEF_ENABLED
/* DEF_DISABLED CPU timestamps DISABLED */
/* DEF_ENABLED CPU timestamps ENABLED */
/* Configure CPU timestamp timer word size ... */
/* ... (see Note #2) : */
#define CPU_CFG_TS_TMR_SIZE CPU_WORD_SIZE_64
/*
*********************************************************************************************************
* CPU INTERRUPTS DISABLED TIME MEASUREMENT CONFIGURATION
*
* Note(s) : (1) (a) Configure CPU_CFG_INT_DIS_MEAS_EN to enable/disable measuring CPU's interrupts
* disabled time :
*
* (a) Enabled, if CPU_CFG_INT_DIS_MEAS_EN #define'd in 'cpu_cfg.h'
*
* (b) Disabled, if CPU_CFG_INT_DIS_MEAS_EN NOT #define'd in 'cpu_cfg.h'
*
* See also 'cpu_core.h FUNCTION PROTOTYPES Note #1'.
*
* (b) Configure CPU_CFG_INT_DIS_MEAS_OVRHD_NBR with the number of times to measure &
* average the interrupts disabled time measurements overhead.
*
* See also 'cpu_core.c CPU_IntDisMeasInit() Note #3a'.
*********************************************************************************************************
*/
#if 0 /* Configure CPU interrupts disabled time ... */
#define CPU_CFG_INT_DIS_MEAS_EN /* ... measurements feature (see Note #1a). */
#endif
/* Configure number of interrupts disabled overhead ... */
#define CPU_CFG_INT_DIS_MEAS_OVRHD_NBR 1u /* ... time measurements (see Note #1b). */
/*
*********************************************************************************************************
* CPU COUNT ZEROS CONFIGURATION
*
* Note(s) : (1) (a) Configure CPU_CFG_LEAD_ZEROS_ASM_PRESENT to define count leading zeros bits
* function(s) in :
*
* (1) 'cpu_a.asm', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable assembly-optimized function(s)
*
* (2) 'cpu_core.c', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT NOT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
*
* (b) Configure CPU_CFG_TRAIL_ZEROS_ASM_PRESENT to define count trailing zeros bits
* function(s) in :
*
* (1) 'cpu_a.asm', if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable assembly-optimized function(s)
*
* (2) 'cpu_core.c', if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT NOT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
*********************************************************************************************************
*/
#if 0 /* Configure CPU count leading zeros bits ... */
#define CPU_CFG_LEAD_ZEROS_ASM_PRESENT /* ... assembly-version (see Note #1a). */
#endif
#if 0 /* Configure CPU count trailing zeros bits ... */
#define CPU_CFG_TRAIL_ZEROS_ASM_PRESENT /* ... assembly-version (see Note #1b). */
#endif
/*
*********************************************************************************************************
* CPU ENDIAN TYPE OVERRIDE
*
* Note(s) : (1) Configure CPU_CFG_ENDIAN_TYPE to override the default CPU endian type defined in cpu.h.
*
* (a) CPU_ENDIAN_TYPE_BIG Big- endian word order (CPU words' most significant
* octet @ lowest memory address)
* (b) CPU_ENDIAN_TYPE_LITTLE Little-endian word order (CPU words' least significant
* octet @ lowest memory address)
*
* (2) Defining CPU_CFG_ENDIAN_TYPE here is only valid for supported bi-endian architectures.
* See 'cpu.h CPU WORD CONFIGURATION Note #3' for details
*********************************************************************************************************
*/
#if 0
#define CPU_CFG_ENDIAN_TYPE CPU_ENDIAN_TYPE_BIG /* Defines CPU data word-memory order (see Note #2). */
#endif
/*
*********************************************************************************************************
* CACHE MANAGEMENT
*
* Note(s) : (1) Configure CPU_CFG_CACHE_MGMT_EN to enable the cache managment API.
*
* (2) Defining CPU_CFG_CACHE_MGMT_EN to DEF_ENABLED only enable the cache management function.
* Cache are assumed to be configured and enabled by the time CPU_init() is called.
*********************************************************************************************************
*/
#define CPU_CFG_CACHE_MGMT_EN DEF_DISABLED
/*
*********************************************************************************************************
* MODULE END
*********************************************************************************************************
*/
#endif /* End of CPU cfg module include. */
#define CPU_CACHE_CFG_L2C310_BASE_ADDR 0xF8F02000

1
src/APP/Aufgabe6/ps7/core0/cfg/cpu_cfg.h Symbolic link
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@@ -0,0 +1 @@
../../../../Aufgabe1/ps7/core0/cfg/cpu_cfg.h

171
src/APP/Aufgabe6/ps7/core0/cfg/lib_cfg.h
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@@ -1,171 +0,0 @@
/*
*********************************************************************************************************
* EXAMPLE CODE
*
* This file is provided as an example on how to use Micrium products.
*
* Please feel free to use any application code labeled as 'EXAMPLE CODE' in
* your application products. Example code may be used as is, in whole or in
* part, or may be used as a reference only. This file can be modified as
* required to meet the end-product requirements.
*
* Please help us continue to provide the Embedded community with the finest
* software available. Your honesty is greatly appreciated.
*
* You can find information about uC/LIB by visiting doc.micrium.com.
* You can contact us at: http://www.micrium.com
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* CUSTOM LIBRARY CONFIGURATION FILE
*
* TEMPLATE
*
* Filename : lib_cfg.h
* Version : V1.38.01.00
* Programmer(s) : FBJ
* JFD
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* MODULE
*********************************************************************************************************
*/
#ifndef LIB_CFG_MODULE_PRESENT
#define LIB_CFG_MODULE_PRESENT
/*
*********************************************************************************************************
*********************************************************************************************************
* MEMORY LIBRARY CONFIGURATION
*********************************************************************************************************
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* MEMORY LIBRARY ARGUMENT CHECK CONFIGURATION
*
* Note(s) : (1) Configure LIB_MEM_CFG_ARG_CHK_EXT_EN to enable/disable the memory library suite external
* argument check feature :
*
* (a) When ENABLED, arguments received from any port interface provided by the developer
* or application are checked/validated.
*
* (b) When DISABLED, NO arguments received from any port interface provided by the developer
* or application are checked/validated.
*********************************************************************************************************
*/
/* External argument check. */
/* Indicates if arguments received from any port ... */
/* ... interface provided by the developer or ... */
/* ... application are checked/validated. */
#define LIB_MEM_CFG_ARG_CHK_EXT_EN DEF_DISABLED
/*
*********************************************************************************************************
* MEMORY LIBRARY ASSEMBLY OPTIMIZATION CONFIGURATION
*
* Note(s) : (1) Configure LIB_MEM_CFG_OPTIMIZE_ASM_EN to enable/disable assembly-optimized memory function(s).
*********************************************************************************************************
*/
/* Assembly-optimized function(s). */
/* Enable/disable assembly-optimized memory ... */
/* ... function(s). [see Note #1] */
#define LIB_MEM_CFG_OPTIMIZE_ASM_EN DEF_DISABLED
/*
*********************************************************************************************************
* MEMORY ALLOCATION CONFIGURATION
*
* Note(s) : (1) Configure LIB_MEM_CFG_DBG_INFO_EN to enable/disable memory allocation usage tracking
* that associates a name with each segment or dynamic pool allocated.
*
* (2) (a) Configure LIB_MEM_CFG_HEAP_SIZE with the desired size of heap memory (in octets).
*
* (b) Configure LIB_MEM_CFG_HEAP_BASE_ADDR to specify a base address for heap memory :
*
* (1) Heap initialized to specified application memory, if LIB_MEM_CFG_HEAP_BASE_ADDR
* #define'd in 'lib_cfg.h';
* CANNOT #define to address 0x0
*
* (2) Heap declared to Mem_Heap[] in 'lib_mem.c', if LIB_MEM_CFG_HEAP_BASE_ADDR
* NOT #define'd in 'lib_cfg.h'
*********************************************************************************************************
*/
/* Allocation debugging information. */
/* Enable/disable allocation of debug information ... */
/* ... associated to each memory allocation. */
#define LIB_MEM_CFG_DBG_INFO_EN DEF_DISABLED
/* Heap memory size (in bytes). */
/* Configure the desired size of the heap memory. ... */
/* ... Set to 0 to disable heap allocation features. */
#define LIB_MEM_CFG_HEAP_SIZE 64*1024
/* Heap memory padding alignment (in bytes). */
/* Configure the desired size of padding alignment ... */
/* ... of each buffer allocated from the heap. */
#define LIB_MEM_CFG_HEAP_PADDING_ALIGN LIB_MEM_PADDING_ALIGN_NONE
#if 0 /* Remove this to have heap alloc at specified addr. */
#define LIB_MEM_CFG_HEAP_BASE_ADDR 0
#endif
/*
*********************************************************************************************************
*********************************************************************************************************
* STRING LIBRARY CONFIGURATION
*********************************************************************************************************
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* STRING FLOATING POINT CONFIGURATION
*
* Note(s) : (1) Configure LIB_STR_CFG_FP_EN to enable/disable floating point string function(s).
*
* (2) Configure LIB_STR_CFG_FP_MAX_NBR_DIG_SIG to configure the maximum number of significant
* digits to calculate &/or display for floating point string function(s).
*
* See also 'lib_str.h STRING FLOATING POINT DEFINES Note #1'.
*********************************************************************************************************
*/
/* Floating point feature(s). */
/* Enable/disable floating point to string functions. */
#define LIB_STR_CFG_FP_EN DEF_DISABLED
/* Floating point number of significant digits. */
/* Configure the maximum number of significant ... */
/* ... digits to calculate &/or display for ... */
/* ... floating point string function(s). */
#define LIB_STR_CFG_FP_MAX_NBR_DIG_SIG LIB_STR_FP_MAX_NBR_DIG_SIG_DFLT
/*
*********************************************************************************************************
* MODULE END
*********************************************************************************************************
*/
#endif /* End of lib cfg module include. */

1
src/APP/Aufgabe6/ps7/core0/cfg/lib_cfg.h Symbolic link
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@@ -0,0 +1 @@
../../../../Aufgabe1/ps7/core0/cfg/lib_cfg.h

42
src/APP/Aufgabe6/ps7/core0/cfg/mmu_cfg.h
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@@ -1,42 +0,0 @@
/*
* mmu_cfg.h
*
* Created on: 25.04.2018
* Author: kaige
*/
#ifndef SRC_APP_LWIPREWORK_PS7_CORE0_CFG_MMU_CFG_H_
#define SRC_APP_LWIPREWORK_PS7_CORE0_CFG_MMU_CFG_H_
#include "mmu.h"
/*------------------------------------------------------------------------------------------------*/
/*!
* \brief FIRST LEVEL TRANSLATION TABLE (FTT)
*
* \ingroup PAR_CPU_MMU
*
* This variable represents the first level translation table. Each entry within
* the table represents the configuration of a 1MB memory segment. If a memory
* portion below 1MB must be accessed, the entry represents a pointer to the
* linked coarse page table, which contains the information of that 1MB in detail.
*
* \note This table MUST be aligned at 16kB boundary.
*/
/*------------------------------------------------------------------------------------------------*/
const PAR_MEM_REGION_T PARMemTbl_Core[] = {
/* +-------------------------------------------------------------------------------------------+
* | virtual | physical | size | owner | permissions | HID Field |
* +-----------+-----------+---------------+------------------+-----------------+--------------+*/
// First 1MB is marked as non-cacheable/non-bufferable (contains 3x 64KB SRAM @ address 0x00000000
{ 0x00000000, 0x00000000, MMU_SIZE_1MB, PAR_AP_PRW__URW_, PAR_HID_TEX_CB_CACHED_MEMORY | PAR_HID_CACHE_INNER_CB | PAR_HID_CACHE_OUTER_CB },
// DDR Memory is marked as normal (only 512MB for now)
{ 0x00100000, 0x00100000, MMU_SIZE_16MB, PAR_AP_PRW__URW_, PAR_HID_TEX_CB_CACHED_MEMORY | PAR_HID_CACHE_INNER___ | PAR_HID_CACHE_OUTER___ },
// Device section
{ 0xE0000000, 0xE0000000, MMU_SIZE_512MB-MMU_SIZE_1MB, PAR_AP_PRW__URW_, PAR_HID_EXCLUSIVE_SYS_DEVICE },
// Upper 1MB section contains 1x 64KB SRAM @ address 0xFFFF0000
{ 0xFFF00000, 0xFFF00000, MMU_SIZE_1MB, PAR_AP_PRW__URW_, PAR_HID_TEX_CB_OUT_IN_NON_CACHABLE }
};
#endif /* SRC_APP_LWIPREWORK_PS7_CORE0_CFG_MMU_CFG_H_ */

1
src/APP/Aufgabe6/ps7/core0/cfg/mmu_cfg.h Symbolic link
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@@ -0,0 +1 @@
../../../../Aufgabe1/ps7/core0/cfg/mmu_cfg.h

145
src/APP/Aufgabe6/ps7/core0/cfg/os_cfg.h
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@@ -1,145 +0,0 @@
/*
*********************************************************************************************************
* uC/OS-II
* The Real-Time Kernel
* uC/OS-II Configuration File for V2.9x
*
* (c) Copyright 2005-2014, Micrium, Weston, FL
* All Rights Reserved
*
*
* File : OS_CFG.H
* By : Jean J. Labrosse
* Version : V2.92.11
*
* LICENSING TERMS:
* ---------------
* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research.
* If you plan on using uC/OS-II in a commercial product you need to contact Micrium to properly license
* its use in your product. We provide ALL the source code for your convenience and to help you experience
* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a
* licensing fee.
*********************************************************************************************************
*/
#ifndef OS_CFG_H
#define OS_CFG_H
/* ---------------------- MISCELLANEOUS ----------------------- */
#define OS_APP_HOOKS_EN 1u /* Application-defined hooks are called from the uC/OS-II hooks */
#define OS_ARG_CHK_EN 0u /* Enable (1) or Disable (0) argument checking */
#define OS_CPU_HOOKS_EN 1u /* uC/OS-II hooks are found in the processor port files */
#define OS_DEBUG_EN 1u /* Enable(1) debug variables */
#define OS_EVENT_MULTI_EN 1u /* Include code for OSEventPendMulti() */
#define OS_EVENT_NAME_EN 1u /* Enable names for Sem, Mutex, Mbox and Q */
#define OS_LOWEST_PRIO 63u /* Defines the lowest priority that can be assigned ... */
/* ... MUST NEVER be higher than 254! */
#define OS_MAX_EVENTS 20u /* Max. number of event control blocks in your application */
#define OS_MAX_FLAGS 5u /* Max. number of Event Flag Groups in your application */
#define OS_MAX_MEM_PART 5u /* Max. number of memory partitions */
#define OS_MAX_QS 6u /* Max. number of queue control blocks in your application */
#define OS_MAX_TASKS 20u /* Max. number of tasks in your application, MUST be >= 2 */
#define OS_SCHED_LOCK_EN 1u /* Include code for OSSchedLock() and OSSchedUnlock() */
#define OS_TICK_STEP_EN 1u /* Enable tick stepping feature for uC/OS-View */
#define OS_TICKS_PER_SEC 1000u /* Set the number of ticks in one second */
#define OS_TLS_TBL_SIZE 0u /* Size of Thread-Local Storage Table */
/* --------------------- TASK STACK SIZE ---------------------- */
#define OS_TASK_TMR_STK_SIZE 128u /* Timer task stack size (# of OS_STK wide entries) */
#define OS_TASK_STAT_STK_SIZE 128u /* Statistics task stack size (# of OS_STK wide entries) */
#define OS_TASK_IDLE_STK_SIZE 128u /* Idle task stack size (# of OS_STK wide entries) */
/* --------------------- TASK MANAGEMENT ---------------------- */
#define OS_TASK_CHANGE_PRIO_EN 1u /* Include code for OSTaskChangePrio() */
#define OS_TASK_CREATE_EN 1u /* Include code for OSTaskCreate() */
#define OS_TASK_CREATE_EXT_EN 1u /* Include code for OSTaskCreateExt() */
#define OS_TASK_DEL_EN 1u /* Include code for OSTaskDel() */
#define OS_TASK_NAME_EN 1u /* Enable task names */
#define OS_TASK_PROFILE_EN 1u /* Include variables in OS_TCB for profiling */
#define OS_TASK_QUERY_EN 1u /* Include code for OSTaskQuery() */
#define OS_TASK_REG_TBL_SIZE 1u /* Size of task variables array (#of INT32U entries) */
#define OS_TASK_STAT_EN 1u /* Enable (1) or Disable(0) the statistics task */
#define OS_TASK_STAT_STK_CHK_EN 1u /* Check task stacks from statistic task */
#define OS_TASK_SUSPEND_EN 1u /* Include code for OSTaskSuspend() and OSTaskResume() */
#define OS_TASK_SW_HOOK_EN 1u /* Include code for OSTaskSwHook() */
/* ----------------------- EVENT FLAGS ------------------------ */
#define OS_FLAG_EN 1u /* Enable (1) or Disable (0) code generation for EVENT FLAGS */
#define OS_FLAG_ACCEPT_EN 1u /* Include code for OSFlagAccept() */
#define OS_FLAG_DEL_EN 1u /* Include code for OSFlagDel() */
#define OS_FLAG_NAME_EN 1u /* Enable names for event flag group */
#define OS_FLAG_QUERY_EN 1u /* Include code for OSFlagQuery() */
#define OS_FLAG_WAIT_CLR_EN 1u /* Include code for Wait on Clear EVENT FLAGS */
#define OS_FLAGS_NBITS 16u /* Size in #bits of OS_FLAGS data type (8, 16 or 32) */
/* -------------------- MESSAGE MAILBOXES --------------------- */
#define OS_MBOX_EN 1u /* Enable (1) or Disable (0) code generation for MAILBOXES */
#define OS_MBOX_ACCEPT_EN 1u /* Include code for OSMboxAccept() */
#define OS_MBOX_DEL_EN 1u /* Include code for OSMboxDel() */
#define OS_MBOX_PEND_ABORT_EN 1u /* Include code for OSMboxPendAbort() */
#define OS_MBOX_POST_EN 1u /* Include code for OSMboxPost() */
#define OS_MBOX_POST_OPT_EN 1u /* Include code for OSMboxPostOpt() */
#define OS_MBOX_QUERY_EN 1u /* Include code for OSMboxQuery() */
/* --------------------- MEMORY MANAGEMENT -------------------- */
#define OS_MEM_EN 1u /* Enable (1) or Disable (0) code generation for MEMORY MANAGER */
#define OS_MEM_NAME_EN 1u /* Enable memory partition names */
#define OS_MEM_QUERY_EN 1u /* Include code for OSMemQuery() */
/* ---------------- MUTUAL EXCLUSION SEMAPHORES --------------- */
#define OS_MUTEX_EN 1u /* Enable (1) or Disable (0) code generation for MUTEX */
#define OS_MUTEX_ACCEPT_EN 1u /* Include code for OSMutexAccept() */
#define OS_MUTEX_DEL_EN 1u /* Include code for OSMutexDel() */
#define OS_MUTEX_QUERY_EN 1u /* Include code for OSMutexQuery() */
/* ---------------------- MESSAGE QUEUES ---------------------- */
#define OS_Q_EN 1u /* Enable (1) or Disable (0) code generation for QUEUES */
#define OS_Q_ACCEPT_EN 1u /* Include code for OSQAccept() */
#define OS_Q_DEL_EN 1u /* Include code for OSQDel() */
#define OS_Q_FLUSH_EN 1u /* Include code for OSQFlush() */
#define OS_Q_PEND_ABORT_EN 1u /* Include code for OSQPendAbort() */
#define OS_Q_POST_EN 1u /* Include code for OSQPost() */
#define OS_Q_POST_FRONT_EN 1u /* Include code for OSQPostFront() */
#define OS_Q_POST_OPT_EN 1u /* Include code for OSQPostOpt() */
#define OS_Q_QUERY_EN 1u /* Include code for OSQQuery() */
/* ------------------------ SEMAPHORES ------------------------ */
#define OS_SEM_EN 1u /* Enable (1) or Disable (0) code generation for SEMAPHORES */
#define OS_SEM_ACCEPT_EN 1u /* Include code for OSSemAccept() */
#define OS_SEM_DEL_EN 1u /* Include code for OSSemDel() */
#define OS_SEM_PEND_ABORT_EN 1u /* Include code for OSSemPendAbort() */
#define OS_SEM_QUERY_EN 1u /* Include code for OSSemQuery() */
#define OS_SEM_SET_EN 1u /* Include code for OSSemSet() */
/* --------------------- TIME MANAGEMENT ---------------------- */
#define OS_TIME_DLY_HMSM_EN 1u /* Include code for OSTimeDlyHMSM() */
#define OS_TIME_DLY_RESUME_EN 1u /* Include code for OSTimeDlyResume() */
#define OS_TIME_GET_SET_EN 1u /* Include code for OSTimeGet() and OSTimeSet() */
#define OS_TIME_TICK_HOOK_EN 1u /* Include code for OSTimeTickHook() */
/* --------------------- TIMER MANAGEMENT --------------------- */
#define OS_TMR_EN 0u /* Enable (1) or Disable (0) code generation for TIMERS */
#define OS_TMR_CFG_MAX 16u /* Maximum number of timers */
#define OS_TMR_CFG_NAME_EN 1u /* Determine timer names */
#define OS_TMR_CFG_WHEEL_SIZE 7u /* Size of timer wheel (#Spokes) */
#define OS_TMR_CFG_TICKS_PER_SEC 10u /* Rate at which timer management task runs (Hz) */
#endif

1
src/APP/Aufgabe6/ps7/core0/cfg/os_cfg.h Symbolic link
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@@ -0,0 +1 @@
../../../../Aufgabe1/ps7/core0/cfg/os_cfg.h

681
src/APP/Aufgabe6/ps7/core0/cfg/xparameters.h
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@@ -1,681 +0,0 @@
/******************************************************************/
/* Definition for CPU ID */
#define XPAR_CPU_ID 0
/* Definitions for peripheral PS7_CORTEXA9_0 */
#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
#define XPAR_PS7_CORTEXA9_1_CPU_CLK_FREQ_HZ XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ
/******************************************************************/
/* Canonical definitions for peripheral PS7_CORTEXA9_0 */
#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
#define XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
/******************************************************************/
#undef DEF_DISABLED
#undef DEF_ENABLED
#define DEF_ENABLED 1
#define DEF_DISABLED 0
#include "xparameters_ps.h"
/******************************************************************/
/* Definitions for driver BRAM */
#define XPAR_XBRAM_NUM_INSTANCES 1
/* Definitions for peripheral AXI_BRAM_CTRL_0 */
#define XPAR_AXI_BRAM_CTRL_0_DEVICE_ID 0
#define XPAR_AXI_BRAM_CTRL_0_DATA_WIDTH 32
#define XPAR_AXI_BRAM_CTRL_0_ECC 0
#define XPAR_AXI_BRAM_CTRL_0_FAULT_INJECT 0
#define XPAR_AXI_BRAM_CTRL_0_CE_FAILING_REGISTERS 0
#define XPAR_AXI_BRAM_CTRL_0_UE_FAILING_REGISTERS 0
#define XPAR_AXI_BRAM_CTRL_0_ECC_STATUS_REGISTERS 0
#define XPAR_AXI_BRAM_CTRL_0_CE_COUNTER_WIDTH 0
#define XPAR_AXI_BRAM_CTRL_0_ECC_ONOFF_REGISTER 0
#define XPAR_AXI_BRAM_CTRL_0_ECC_ONOFF_RESET_VALUE 0
#define XPAR_AXI_BRAM_CTRL_0_WRITE_ACCESS 0
#define XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR 0x40000000
#define XPAR_AXI_BRAM_CTRL_0_S_AXI_HIGHADDR 0x40001FFF
#define XPAR_AXI_BRAM_CTRL_0_S_AXI_CTRL_BASEADDR 0xFFFFFFFF
#define XPAR_AXI_BRAM_CTRL_0_S_AXI_CTRL_HIGHADDR 0xFFFFFFFF
/******************************************************************/
/* Canonical definitions for peripheral AXI_BRAM_CTRL_0 */
#define XPAR_BRAM_0_DEVICE_ID XPAR_AXI_BRAM_CTRL_0_DEVICE_ID
#define XPAR_BRAM_0_DATA_WIDTH 32
#define XPAR_BRAM_0_ECC 0
#define XPAR_BRAM_0_FAULT_INJECT 0
#define XPAR_BRAM_0_CE_FAILING_REGISTERS 0
#define XPAR_BRAM_0_UE_FAILING_REGISTERS 0
#define XPAR_BRAM_0_ECC_STATUS_REGISTERS 0
#define XPAR_BRAM_0_CE_COUNTER_WIDTH 0
#define XPAR_BRAM_0_ECC_ONOFF_REGISTER 0
#define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 0
#define XPAR_BRAM_0_WRITE_ACCESS 0
#define XPAR_BRAM_0_BASEADDR 0x40000000
#define XPAR_BRAM_0_HIGHADDR 0x40001FFF
/******************************************************************/
/* Definitions for peripheral PS7_DDR_0 */
#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
/******************************************************************/
/* Definitions for driver DEVCFG */
#define XPAR_XDCFG_NUM_INSTANCES 1
/* Definitions for peripheral PS7_DEV_CFG_0 */
#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0
#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000
#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FF
/******************************************************************/
/* Canonical definitions for peripheral PS7_DEV_CFG_0 */
#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
#define XPAR_XDCFG_0_BASEADDR 0xF8007000
#define XPAR_XDCFG_0_HIGHADDR 0xF80070FF
/******************************************************************/
/* Definitions for driver DMAPS */
#define XPAR_XDMAPS_NUM_INSTANCES 2
/* Definitions for peripheral PS7_DMA_NS */
#define XPAR_PS7_DMA_NS_DEVICE_ID 0
#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF
/* Definitions for peripheral PS7_DMA_S */
#define XPAR_PS7_DMA_S_DEVICE_ID 1
#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF
/******************************************************************/
/* Canonical definitions for peripheral PS7_DMA_NS */
#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
#define XPAR_XDMAPS_0_BASEADDR 0xF8004000
#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF
/* Canonical definitions for peripheral PS7_DMA_S */
#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
#define XPAR_XDMAPS_1_BASEADDR 0xF8003000
#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF
/******************************************************************/
/* Definitions for peripheral PS7_AFI_0 */
#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
/* Definitions for peripheral PS7_AFI_1 */
#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000
#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF
/* Definitions for peripheral PS7_AFI_2 */
#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000
#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF
/* Definitions for peripheral PS7_AFI_3 */
#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000
#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
/* Definitions for peripheral PS7_DDRC_0 */
#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
/* Definitions for peripheral PS7_GLOBALTIMER_0 */
#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200
#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF
/* Definitions for peripheral PS7_GPV_0 */
#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000
#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF
/* Definitions for peripheral PS7_INTC_DIST_0 */
#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000
#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF
/* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
/* Definitions for peripheral PS7_OCMC_0 */
#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000
#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF
/* Definitions for peripheral PS7_PL310_0 */
#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000
#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF
/* Definitions for peripheral PS7_PMU_0 */
#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000
#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF
#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000
#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF
/* Definitions for peripheral PS7_QSPI_LINEAR_0 */
#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFDFFFFFF
/* Definitions for peripheral PS7_RAM_0 */
#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
/* Definitions for peripheral PS7_RAM_1 */
#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000
#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
/* Definitions for peripheral PS7_SLCR_0 */
#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF
/******************************************************************/
/* Definitions for driver GPIO */
#define XPAR_XGPIO_NUM_INSTANCES 1
/* Definitions for peripheral AXI_GPIO_0 */
#define XPAR_AXI_GPIO_0_BASEADDR 0x41200000
#define XPAR_AXI_GPIO_0_HIGHADDR 0x4120FFFF
#define XPAR_AXI_GPIO_0_DEVICE_ID 0
#define XPAR_AXI_GPIO_0_INTERRUPT_PRESENT 0
#define XPAR_AXI_GPIO_0_IS_DUAL 0
/******************************************************************/
/* Canonical definitions for peripheral AXI_GPIO_0 */
#define XPAR_GPIO_0_BASEADDR 0x41200000
#define XPAR_GPIO_0_HIGHADDR 0x4120FFFF
#define XPAR_GPIO_0_DEVICE_ID XPAR_AXI_GPIO_0_DEVICE_ID
#define XPAR_GPIO_0_INTERRUPT_PRESENT 0
#define XPAR_GPIO_0_IS_DUAL 0
/******************************************************************/
/* Definitions for driver GPIOPS */
#define XPAR_XGPIOPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_GPIO_0 */
#define XPAR_PS7_GPIO_0_DEVICE_ID 0
#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
/******************************************************************/
/* Canonical definitions for peripheral PS7_GPIO_0 */
#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
/******************************************************************/
///* Definitions for driver IICPS */
//#define XPAR_XIICPS_NUM_INSTANCES 1
//
///* Definitions for peripheral PS7_I2C_0 */
//#define XPAR_PS7_I2C_0_DEVICE_ID 0
//#define XPAR_PS7_I2C_0_BASEADDR 0xE0004000
//#define XPAR_PS7_I2C_0_HIGHADDR 0xE0004FFF
//#define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 111111115
/******************************************************************/
/* Canonical definitions for peripheral PS7_I2C_0 */
#define XPAR_XIICPS_0_DEVICE_ID XPAR_PS7_I2C_0_DEVICE_ID
#define XPAR_XIICPS_0_BASEADDR 0xE0004000
#define XPAR_XIICPS_0_HIGHADDR 0xE0004FFF
#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 111111115
/******************************************************************/
/* Definitions for driver QSPIPS */
#define XPAR_XQSPIPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_QSPI_0 */
#define XPAR_PS7_QSPI_0_DEVICE_ID 0
#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000
#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000
#define XPAR_PS7_QSPI_0_QSPI_MODE 2
/******************************************************************/
/* Canonical definitions for peripheral PS7_QSPI_0 */
#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID
#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000
#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000
#define XPAR_XQSPIPS_0_QSPI_MODE 2
/******************************************************************/
/* Definitions for driver SCUWDT */
#define XPAR_XSCUWDT_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SCUWDT_0 */
#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF
/******************************************************************/
/* Canonical definitions for peripheral PS7_SCUWDT_0 */
#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
/******************************************************************/
/* Definitions for driver UCOS_EMACPS */
#define XPAR_UCOS_EMACPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_ETHERNET_0 */
#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0
#define XPAR_PS7_ETHERNET_0_BASEADDR 0x00000000
#define XPAR_PS7_ETHERNET_0_HIGHADDR 0x00000000
#define XPAR_PS7_ETHERNET_0_CLOCK_FREQ_HZ 0
/******************************************************************/
/* Canonical definitions for peripheral PS7_ETHERNET_0 */
#define XPAR_UCOS_EMACPS_0_NUM_INSTANCES 0
#define XPAR_UCOS_EMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID
#define XPAR_UCOS_EMACPS_0_BASEADDR 0x00000000
#define XPAR_UCOS_EMACPS_0_HIGHADDR 0x00000000
#define XPAR_UCOS_EMACPS_0_CLOCK_FREQ_HZ 0
/******************************************************************/
/* Definitions for driver UCOS_L2CACHEC */
#define XPAR_UCOS_L2CACHEC_NUM_INSTANCES 1
/* Definitions for peripheral PS7_L2CACHEC_0 */
#define XPAR_PS7_L2CACHEC_0_DEVICE_ID 0
#define XPAR_PS7_L2CACHEC_0_BASEADDR 0xF8F02000
#define XPAR_PS7_L2CACHEC_0_HIGHADDR 0xF8F02FFF
/******************************************************************/
/* Definitions for driver UCOS_SCUC */
#define XPAR_UCOS_L2CACHEC_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SCUC_0 */
#define XPAR_PS7_SCUC_0_DEVICE_ID 0
#define XPAR_PS7_SCUC_0_BASEADDR 0xF8F00000
#define XPAR_PS7_SCUC_0_HIGHADDR 0xF8F000FC
/******************************************************************/
/***Definitions for Core_nIRQ/nFIQ interrupts ****/
/* Definitions for driver UCOS_SCUGIC */
#define XPAR_XSCUGIC_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SCUGIC_0 */
#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0
#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100
#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FF
#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000
/******************************************************************/
/* Canonical definitions for peripheral PS7_SCUGIC_0 */
#define XPAR_SCUGIC_0_DEVICE_ID 0
#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100
#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FF
#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000
/******************************************************************/
/* Definitions for driver UCOS_SCUTIMER */
#define XPAR_UCOS_SCUC_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SCUTIMER_0 */
#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F
/******************************************************************/
/* Definitions for driver UCOS_SDPS */
#define XPAR_UCOS_SDPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SD_0 */
#define XPAR_PS7_SD_0_DEVICE_ID 0
#define XPAR_PS7_SD_0_BASEADDR 0xE0100000
#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
/******************************************************************/
/* Canonical definitions for peripheral PS7_SD_0 */
#define XPAR_UCOS_SDPS_0_NUM_INSTANCES 0
#define XPAR_UCOS_SDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID
#define XPAR_UCOS_SDPS_0_BASEADDR 0xE0100000
#define XPAR_UCOS_SDPS_0_HIGHADDR 0xE0100FFF
#define XPAR_UCOS_SDPS_0_SDIO_CLK_FREQ_HZ 50000000
/******************************************************************/
///* Definitions for driver UCOS_TTCPS */
//#define XPAR_UCOS_TTCPS_NUM_INSTANCES 3
//
///* Definitions for peripheral PS7_TTC_0 */
//#define XPAR_PS7_TTC_0_DEVICE_ID 0
//#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000
//#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115
//#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0
//#define XPAR_PS7_TTC_1_DEVICE_ID 1
//#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004
//#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115
//#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0
//#define XPAR_PS7_TTC_2_DEVICE_ID 2
//#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008
//#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115
//#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0
/******************************************************************/
/* Definitions for driver UCOS_UARTPS */
#define XPAR_UCOS_UARTPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_UART_1 */
#define XPAR_PS7_UART_1_DEVICE_ID 0
#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 50000000
#define XPAR_PS7_UART_1_HAS_MODEM 0
/******************************************************************/
/* Canonical definitions for peripheral PS7_UART_1 */
#define XPAR_UCOS_UARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
#define XPAR_UCOS_UARTPS_0_BASEADDR 0xE0001000
#define XPAR_UCOS_UARTPS_0_HIGHADDR 0xE0001FFF
#define XPAR_UCOS_UARTPS_0_UART_CLK_FREQ_HZ 50000000
#define XPAR_UCOS_UARTPS_0_HAS_MODEM 0
/******************************************************************/
/* Definitions for driver UCOS_USBPS */
#define XPAR_UCOS_USBPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_USB_0 */
#define XPAR_PS7_USB_0_DEVICE_ID 0
#define XPAR_PS7_USB_0_BASEADDR 0xE0002000
#define XPAR_PS7_USB_0_HIGHADDR 0xE0002FFF
/******************************************************************/
/* Canonical definitions for peripheral PS7_USB_0 */
#define XPAR_UCOS_USBPS_0_DEVICE_ID XPAR_PS7_USB_0_DEVICE_ID
#define XPAR_UCOS_USBPS_0_BASEADDR 0xE0002000
#define XPAR_UCOS_USBPS_0_HIGHADDR 0xE0002FFF
/******************************************************************/
/* Definitions for driver XADCPS */
#define XPAR_XADCPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_XADC_0 */
#define XPAR_PS7_XADC_0_DEVICE_ID 0
#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100
#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120
/******************************************************************/
/* Canonical definitions for peripheral PS7_XADC_0 */
#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
#define XPAR_XADCPS_0_BASEADDR 0xF8007100
#define XPAR_XADCPS_0_HIGHADDR 0xF8007120
/******************************************************************/
//UCOS STDOUT
#define UCOS_STDOUT_DRIVER UCOS_UART_PS7_UART
#define UCOS_STDOUT_DEVICE_ID 0
#define STDOUT_BASEADDRESS
//UCOS Ethernet
#define UCOS_ETHERNET_DRIVER UCOS_ETHERNET_EMACPS
//UCOS TASK PARAMETERS
#define UCOS_START_TASK_PRIO 5
#define UCOS_START_TASK_STACK_SIZE 784
#define UCOS_START_DEBUG_TRACE DEF_ENABLED
#define NET_TASK_CFG_RX_PRIO 30
#define NET_TASK_CFG_RX_STACK_SIZE 3072
#define NET_TASK_CFG_TXDEALLOC_PRIO 6
#define NET_TASK_CFG_TXDEALLOC_STACK_SIZE 2048
#define NET_TASK_CFG_TMR_PRIO 18
#define NET_TASK_CFG_TMR_STACK_SIZE 2048
#define HTTPc_OS_CFG_TASK_PRIO 20
#define HTTPc_OS_CFG_TASK_STK_SIZE 2048
#define UCOS_HTTPc_OS_CFG_TASK_DELAY 1
#define UCOS_HTTPc_OS_CFG_MSG_Q_SIZE 5
#define UCOS_HTTPc_OS_CFG_TIMEOUT 2000
#define UCOS_HTTPc_OS_CFG_INACTIVITY_TIMEOUT 30
#define UCOS_AMP_MASTER DEF_ENABLED
#define UCOS_CFG_INIT_CAN DEF_ENABLED
#define UCOS_CFG_INIT_NET DEF_ENABLED
#define UCOS_CFG_INIT_FS DEF_DISABLED
#define UCOS_CFG_INIT_OPENAMP DEF_DISABLED
#define UCOS_CFG_INIT_USBD DEF_DISABLED
#define UCOS_CFG_INIT_USBH DEF_DISABLED
#define UCOS_ETHERNET_ADDRESS "10.10.110.2"
#define UCOS_ETHERNET_GATEWAY "10.10.110.1"
#define UCOS_ETHERNET_SUBMASK "255.255.255.0"
#define UCOS_ETHERNET_DHCP DEF_ENABLED
#define UCOS_IF_RX_BUF_NBR 12
#define UCOS_IF_TX_LARGE_BUF_NBR 8
#define UCOS_IF_TX_SMALL_BUF_NBR 8
#define UCOS_IF_RX_DESC_NBR 0
#define UCOS_IF_TX_DESC_NBR 0
#define UCOS_IF_DEDIC_MEM_ADDR 0
#define UCOS_IF_DEDIC_MEM_SIZE 0
#define UCOS_IF_HW_ADDR "50:E5:49:E6:8D:28"
#define UCOS_PHY_BUS_ADDR 255
#define UCOS_PHY_BUS_MODE UCOS_NET_PHY_BUS_MODE_GMII
#define UCOS_PHY_TYPE UCOS_NET_PHY_TYPE_INT
#define UCOS_PHY_SPEED UCOS_NET_PHY_SPD_AUTO
#define UCOS_PHY_DUPLEX UCOS_NET_PHY_DUPLEX_AUTO
#define UCOS_USB_DRIVER UCOS_USB_NONE
#define UCOS_USB_DEVICE_ID 0
#define UCOS_USB_TYPE UCOS_USB_TYPE_DEVICE
#define UCOS_RAMDISK_EN DEF_DISABLED
#define UCOS_RAMDISK_SIZE 128
#define UCOS_RAMDISK_SECTOR_SIZE 512
#define UCOS_RAMDISK_BASE_ADDRESS 0
#define UCOS_SDCARD_EN DEF_DISABLED
#define XPAR_PS7_ETHERNET_0_INT_SOURCE 54
#define XPAR_PS7_SD_0_INT_SOURCE 56
#define XPAR_PS7_UART_1_INT_SOURCE 82
#define XPAR_PS7_USB_0_INT_SOURCE 53
#define UCOS_ZYNQ_CONFIG_MMU DEF_DISABLED
#define UCOS_ZYNQ_ENABLE_MMU DEF_DISABLED
#define UCOS_ZYNQ_CONFIG_CACHES DEF_DISABLED
#define UCOS_ZYNQ_ENABLE_CACHES DEF_DISABLED
#define UCOS_ZYNQ_ENABLE_OPTIMS DEF_DISABLED
#define ZYNQ_ENABLE_EARLY_L1_I_EN DEF_DISABLED
#define ZYNQ_ENABLE_EARLY_L1_D_EN DEF_DISABLED
#define UCOS_CPU_TYPE UCOS_CPU_TYPE_PS7
//Parameters added by Kai Gemlau
#define UCOS_SMP_ENABLE DEF_DISABLED
/******************************************************************/
/* Definitions for driver TTCPS */
#define XPAR_XTTCPS_NUM_INSTANCES 3U
/* Definitions for peripheral PS7_TTC_0 */
#define XPAR_PS7_TTC_0_DEVICE_ID 0U
#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000U
#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115U
#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0U
#define XPAR_PS7_TTC_1_DEVICE_ID 1U
#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004U
#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115U
#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0U
#define XPAR_PS7_TTC_2_DEVICE_ID 2U
#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008U
#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115U
#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0U
/******************************************************************/
/* Canonical definitions for peripheral PS7_TTC_0 */
#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PS7_TTC_0_DEVICE_ID
#define XPAR_XTTCPS_0_BASEADDR 0xF8001000U
#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 111111115U
#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0U
#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PS7_TTC_1_DEVICE_ID
#define XPAR_XTTCPS_1_BASEADDR 0xF8001004U
#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 111111115U
#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0U
#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PS7_TTC_2_DEVICE_ID
#define XPAR_XTTCPS_2_BASEADDR 0xF8001008U
#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 111111115U
#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0U
/******************************************************************/
/* Definitions for driver GPIOPS */
#define XPAR_XGPIOPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_GPIO_0 */
#define XPAR_PS7_GPIO_0_DEVICE_ID 0
#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
/******************************************************************/
/* Canonical definitions for peripheral PS7_GPIO_0 */
#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
/******************************************************************/
/* Definitions for driver IICPS */
#define XPAR_XIICPS_NUM_INSTANCES 2
/* Definitions for peripheral PS7_I2C_0 */
#define XPAR_PS7_I2C_0_DEVICE_ID 0
#define XPAR_PS7_I2C_0_BASEADDR 0xE0004000
#define XPAR_PS7_I2C_0_HIGHADDR 0xE0004FFF
#define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 111111115
/* Definitions for peripheral PS7_I2C_1 */
#define XPAR_PS7_I2C_1_DEVICE_ID 1
#define XPAR_PS7_I2C_1_BASEADDR 0xE0005000
#define XPAR_PS7_I2C_1_HIGHADDR 0xE0005FFF
#define XPAR_PS7_I2C_1_I2C_CLK_FREQ_HZ 111111115
/******************************************************************/
/* Canonical definitions for peripheral PS7_I2C_0 */
#define XPAR_XIICPS_0_DEVICE_ID XPAR_PS7_I2C_0_DEVICE_ID
#define XPAR_XIICPS_0_BASEADDR 0xE0004000
#define XPAR_XIICPS_0_HIGHADDR 0xE0004FFF
#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 111111115
/* Canonical definitions for peripheral PS7_I2C_1 */
#define XPAR_XIICPS_1_DEVICE_ID XPAR_PS7_I2C_1_DEVICE_ID
#define XPAR_XIICPS_1_BASEADDR 0xE0005000
#define XPAR_XIICPS_1_HIGHADDR 0xE0005FFF
#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 111111115
/******************************************************************/

1
src/APP/Aufgabe6/ps7/core0/cfg/xparameters.h Symbolic link
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../../../../Aufgabe1/ps7/core0/cfg/xparameters.h

325
src/APP/Aufgabe6/ps7/core0/cfg/xparameters_ps.h
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@@ -1,325 +0,0 @@
/******************************************************************************
*
* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
* @file xparameters_ps.h
*
* This file contains the address definitions for the hard peripherals
* attached to the ARM Cortex A9 core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------- -------- ---------------------------------------------------
* 1.00a ecm/sdm 02/01/10 Initial version
* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
* driver tcl
* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#ifndef _XPARAMETERS_PS_H_
#define _XPARAMETERS_PS_H_
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions *****************************/
/*
* This block contains constant declarations for the peripherals
* within the hardblock
*/
/* Canonical definitions for DDR MEMORY */
#define XPAR_DDR_MEM_BASEADDR 0x00000000U
#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
/* Canonical definitions for Interrupts */
#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID
#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID
#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID
#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID
#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID
#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID
#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR
#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR
/* Canonical definitions for DMAC */
/* Canonical definitions for WDT */
/* Canonical definitions for SLCR */
#define XPAR_XSLCR_NUM_INSTANCES 1U
#define XPAR_XSLCR_0_DEVICE_ID 0U
#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR
/* Canonical definitions for SCU GIC */
#define XPAR_SCUGIC_NUM_INSTANCES 1U
#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000100U)
#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
#define XPAR_SCUGIC_ACK_BEFORE 0U
/* Canonical definitions for Global Timer */
#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U
#define XPAR_GLOBAL_TMR_DEVICE_ID 0U
#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U)
#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID
/* Xilinx Parallel Flash Library (XilFlash) User Settings */
#define XPAR_AXI_EMC
#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
/*
* This block contains constant declarations for the peripherals
* within the hardblock. These have been put for bacwards compatibilty
*/
#define XPS_PERIPHERAL_BASEADDR 0xE0000000U
#define XPS_UART0_BASEADDR 0xE0000000U
#define XPS_UART1_BASEADDR 0xE0001000U
#define XPS_USB0_BASEADDR 0xE0002000U
#define XPS_USB1_BASEADDR 0xE0003000U
#define XPS_I2C0_BASEADDR 0xE0004000U
#define XPS_I2C1_BASEADDR 0xE0005000U
#define XPS_SPI0_BASEADDR 0xE0006000U
#define XPS_SPI1_BASEADDR 0xE0007000U
#define XPS_CAN0_BASEADDR 0xE0008000U
#define XPS_CAN1_BASEADDR 0xE0009000U
#define XPS_GPIO_BASEADDR 0xE000A000U
#define XPS_GEM0_BASEADDR 0xE000B000U
#define XPS_GEM1_BASEADDR 0xE000C000U
#define XPS_QSPI_BASEADDR 0xE000D000U
#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000U
#define XPS_SDIO0_BASEADDR 0xE0100000U
#define XPS_SDIO1_BASEADDR 0xE0101000U
#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U
#define XPS_NAND_BASEADDR 0xE1000000U
#define XPS_PARPORT0_BASEADDR 0xE2000000U
#define XPS_PARPORT1_BASEADDR 0xE4000000U
#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000U
#define XPS_SYS_CTRL_BASEADDR 0xF8000000U /* AKA SLCR */
#define XPS_TTC0_BASEADDR 0xF8001000U
#define XPS_TTC1_BASEADDR 0xF8002000U
#define XPS_DMAC0_SEC_BASEADDR 0xF8003000U
#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000U
#define XPS_WDT_BASEADDR 0xF8005000U
#define XPS_DDR_CTRL_BASEADDR 0xF8006000U
#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U
#define XPS_AFI0_BASEADDR 0xF8008000U
#define XPS_AFI1_BASEADDR 0xF8009000U
#define XPS_AFI2_BASEADDR 0xF800A000U
#define XPS_AFI3_BASEADDR 0xF800B000U
#define XPS_OCM_BASEADDR 0xF800C000U
#define XPS_EFUSE_BASEADDR 0xF800D000U
#define XPS_CORESIGHT_BASEADDR 0xF8800000U
#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U
#define XPS_SCU_PERIPH_BASE 0xF8F00000U
#define XPS_L2CC_BASEADDR 0xF8F02000U
#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U
#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U
#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U
#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U
#define XPS_PERIPH_APB_BASEADDR 0xF8000000U
/* Shared Peripheral Interrupts (SPI) */
#define XPS_CORE_PARITY0_INT_ID 32U
#define XPS_CORE_PARITY1_INT_ID 33U
#define XPS_L2CC_INT_ID 34U
#define XPS_OCMINTR_INT_ID 35U
#define XPS_ECC_INT_ID 36U
#define XPS_PMU0_INT_ID 37U
#define XPS_PMU1_INT_ID 38U
#define XPS_SYSMON_INT_ID 39U
#define XPS_DVC_INT_ID 40U
#define XPS_WDT_INT_ID 41U
#define XPS_TTC0_0_INT_ID 42U
#define XPS_TTC0_1_INT_ID 43U
#define XPS_TTC0_2_INT_ID 44U
#define XPS_DMA0_ABORT_INT_ID 45U
#define XPS_DMA0_INT_ID 46U
#define XPS_DMA1_INT_ID 47U
#define XPS_DMA2_INT_ID 48U
#define XPS_DMA3_INT_ID 49U
#define XPS_SMC_INT_ID 50U
#define XPS_QSPI_INT_ID 51U
#define XPS_GPIO_INT_ID 52U
#define XPS_USB0_INT_ID 53U
#define XPS_GEM0_INT_ID 54U
#define XPS_GEM0_WAKE_INT_ID 55U
#define XPS_SDIO0_INT_ID 56U
#define XPS_I2C0_INT_ID 57U
#define XPS_SPI0_INT_ID 58U
#define XPS_UART0_INT_ID 59U
#define XPS_CAN0_INT_ID 60U
#define XPS_FPGA0_INT_ID 61U
#define XPS_FPGA1_INT_ID 62U
#define XPS_FPGA2_INT_ID 63U
#define XPS_FPGA3_INT_ID 64U
#define XPS_FPGA4_INT_ID 65U
#define XPS_FPGA5_INT_ID 66U
#define XPS_FPGA6_INT_ID 67U
#define XPS_FPGA7_INT_ID 68U
#define XPS_TTC1_0_INT_ID 69U
#define XPS_TTC1_1_INT_ID 70U
#define XPS_TTC1_2_INT_ID 71U
#define XPS_DMA4_INT_ID 72U
#define XPS_DMA5_INT_ID 73U
#define XPS_DMA6_INT_ID 74U
#define XPS_DMA7_INT_ID 75U
#define XPS_USB1_INT_ID 76U
#define XPS_GEM1_INT_ID 77U
#define XPS_GEM1_WAKE_INT_ID 78U
#define XPS_SDIO1_INT_ID 79U
#define XPS_I2C1_INT_ID 80U
#define XPS_SPI1_INT_ID 81U
#define XPS_UART1_INT_ID 82U
#define XPS_CAN1_INT_ID 83U
#define XPS_FPGA8_INT_ID 84U
#define XPS_FPGA9_INT_ID 85U
#define XPS_FPGA10_INT_ID 86U
#define XPS_FPGA11_INT_ID 87U
#define XPS_FPGA12_INT_ID 88U
#define XPS_FPGA13_INT_ID 89U
#define XPS_FPGA14_INT_ID 90U
#define XPS_FPGA15_INT_ID 91U
/* Private Peripheral Interrupts (PPI) */
#define XPS_GLOBAL_TMR_INT_ID 27U /* SCU Global Timer interrupt */
#define XPS_FIQ_INT_ID 28U /* FIQ from FPGA fabric */
#define XPS_SCU_TMR_INT_ID 29U /* SCU Private Timer interrupt */
#define XPS_SCU_WDT_INT_ID 30U /* SCU Private WDT interrupt */
#define XPS_IRQ_INT_ID 31U /* IRQ from FPGA fabric */
/* REDEFINES for TEST APP */
/* Definitions for UART */
#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID
#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID
#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID
#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID
#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID
#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID
#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID
#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID
#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID
#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID
#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID
#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID
#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID
#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID
#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID
#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
#define XPAR_PS7_TTC_0_INTR XPS_TTC0_0_INT_ID
#define XPAR_PS7_TTC_1_INTR XPS_TTC0_1_INT_ID
#define XPAR_PS7_TTC_2_INTR XPS_TTC0_2_INT_ID
#define XPAR_PS7_TTC_3_INTR XPS_TTC1_0_INT_ID
#define XPAR_PS7_TTC_4_INTR XPS_TTC1_1_INT_ID
#define XPAR_PS7_TTC_5_INTR XPS_TTC1_2_INT_ID
#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
/* For backwards compatibilty */
#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
#define XPAR_SCUTIMER_DEVICE_ID 0U
#define XPAR_SCUWDT_DEVICE_ID 0U
#ifdef __cplusplus
}
#endif
#endif /* protection macro */

1
src/APP/Aufgabe6/ps7/core0/cfg/xparameters_ps.h Symbolic link
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../../../../Aufgabe1/ps7/core0/cfg/xparameters_ps.h

291
src/APP/Aufgabe6/ps7/core0/linker/lscript.ld
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@@ -1,291 +0,0 @@
/*******************************************************************/
/* */
/* This file is automatically generated by linker script generator.*/
/* */
/* Version: */
/* */
/* Copyright (c) 2010-2016 Xilinx, Inc. All rights reserved. */
/* */
/* Description : Cortex-A9 Linker Script */
/* */
/*******************************************************************/
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
/* Define Memories in the system */
MEMORY
{
axi_bram_ctrl_0_Mem0 : ORIGIN = 0x40000000, LENGTH = 0x2000
ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x3FF00000
ps7_qspi_linear_0 : ORIGIN = 0xFC000000, LENGTH = 0x2000000
ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000
ps7_ram_1 : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00
ps7_ddr_core_0 : ORIGIN = 0x100000, LENGTH = 0x700000
ps7_ddr_core_1 : ORIGIN = 0x800000, LENGTH = 0x800000
}
/* Specify the default entry point to the program */
ENTRY(_vector_table)
/* Define the sections, and where they are mapped in memory */
SECTIONS
{
.text : {
KEEP (*(.vectors))
*(.boot)
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
*(.plt)
*(.gnu_warning)
*(.gcc_execpt_table)
*(.glue_7)
*(.glue_7t)
*(.vfp11_veneer)
*(.ARM.extab)
*(.gnu.linkonce.armextab.*)
} > ps7_ddr_core_0
.init : {
KEEP (*(.init))
} > ps7_ddr_core_0
.fini : {
KEEP (*(.fini))
} > ps7_ddr_core_0
.rodata : {
__rodata_start = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
__rodata_end = .;
} > ps7_ddr_core_0
.rodata1 : {
__rodata1_start = .;
*(.rodata1)
*(.rodata1.*)
__rodata1_end = .;
} > ps7_ddr_core_0
.sdata2 : {
__sdata2_start = .;
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
__sdata2_end = .;
} > ps7_ddr_core_0
.sbss2 : {
__sbss2_start = .;
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
__sbss2_end = .;
} > ps7_ddr_core_0
.data : {
__data_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.jcr)
*(.got)
*(.got.plt)
__data_end = .;
} > ps7_ddr_core_0
.data1 : {
__data1_start = .;
*(.data1)
*(.data1.*)
__data1_end = .;
} > ps7_ddr_core_0
.got : {
*(.got)
} > ps7_ddr_core_0
.ctors : {
__CTOR_LIST__ = .;
___CTORS_LIST___ = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
___CTORS_END___ = .;
} > ps7_ddr_core_0
.dtors : {
__DTOR_LIST__ = .;
___DTORS_LIST___ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
___DTORS_END___ = .;
} > ps7_ddr_core_0
.fixup : {
__fixup_start = .;
*(.fixup)
__fixup_end = .;
} > ps7_ddr_core_0
.eh_frame : {
*(.eh_frame)
} > ps7_ddr_core_0
.eh_framehdr : {
__eh_framehdr_start = .;
*(.eh_framehdr)
__eh_framehdr_end = .;
} > ps7_ddr_core_0
.gcc_except_table : {
*(.gcc_except_table)
} > ps7_ddr_core_0
.mmu_tbl (ALIGN(16384)) : {
__mmu_tbl_start = .;
*(.mmu_tbl)
__mmu_tbl_end = .;
} > ps7_ddr_core_0
.ARM.exidx : {
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidix.*.*)
__exidx_end = .;
} > ps7_ddr_core_0
.preinit_array : {
__preinit_array_start = .;
KEEP (*(SORT(.preinit_array.*)))
KEEP (*(.preinit_array))
__preinit_array_end = .;
} > ps7_ddr_core_0
.init_array : {
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
} > ps7_ddr_core_0
.fini_array : {
__fini_array_start = .;
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array))
__fini_array_end = .;
} > ps7_ddr_core_0
.ARM.attributes : {
__ARM.attributes_start = .;
*(.ARM.attributes)
__ARM.attributes_end = .;
} > ps7_ddr_core_0
.sdata : {
__sdata_start = .;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
__sdata_end = .;
} > ps7_ddr_core_0
.sbss (NOLOAD) : {
__sbss_start = .;
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
__sbss_end = .;
} > ps7_ddr_core_0
.tdata : {
__tdata_start = .;
*(.tdata)
*(.tdata.*)
*(.gnu.linkonce.td.*)
__tdata_end = .;
} > ps7_ddr_core_0
.tbss : {
__tbss_start = .;
*(.tbss)
*(.tbss.*)
*(.gnu.linkonce.tb.*)
__tbss_end = .;
} > ps7_ddr_core_0
.bss (NOLOAD) : {
__bss_start = .;
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
__bss_end = .;
} > ps7_ddr_core_0
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
/* Generate Stack and Heap definitions */
.heap (NOLOAD) : {
. = ALIGN(16);
_heap = .;
HeapBase = .;
_heap_start = .;
. += _HEAP_SIZE;
_heap_end = .;
HeapLimit = .;
} > ps7_ddr_core_0
.stack (NOLOAD) : {
. = ALIGN(16);
_stack_end = .;
. += _STACK_SIZE;
. = ALIGN(16);
_stack = .;
__stack = _stack;
. = ALIGN(16);
_irq_stack_end = .;
. += _IRQ_STACK_SIZE;
. = ALIGN(16);
__irq_stack = .;
_supervisor_stack_end = .;
. += _SUPERVISOR_STACK_SIZE;
. = ALIGN(16);
__supervisor_stack = .;
_abort_stack_end = .;
. += _ABORT_STACK_SIZE;
. = ALIGN(16);
__abort_stack = .;
_fiq_stack_end = .;
. += _FIQ_STACK_SIZE;
. = ALIGN(16);
__fiq_stack = .;
_undef_stack_end = .;
. += _UNDEF_STACK_SIZE;
. = ALIGN(16);
__undef_stack = .;
} > ps7_ddr_core_0
_end = .;
}

1
src/APP/Aufgabe6/ps7/core0/linker/lscript.ld Symbolic link
View File

@@ -0,0 +1 @@
../../../../Aufgabe1/ps7/core0/linker/lscript.ld

17
src/APP/Aufgabe6/ps7/core0/src/uartps_cfg.c
View File

@@ -1,17 +0,0 @@
#include "ucos_uartps.h"
#include "xparameters.h"
#include "xparameters_ps.h"
/*
* The uart configuration table for devices
*/
UCOS_UARTPS_Config UCOS_UARTPS_ConfigTable[] = {
{
XPAR_PS7_UART_1_DEVICE_ID,
XPAR_PS7_UART_1_BASEADDR,
XPAR_PS7_UART_1_UART_CLK_FREQ_HZ,
XPAR_PS7_UART_1_HAS_MODEM,
XPAR_PS7_UART_1_INT_SOURCE
}
};

1
src/APP/Aufgabe6/ps7/core0/src/uartps_cfg.c Symbolic link
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@@ -0,0 +1 @@
../../../../Aufgabe1/ps7/core0/src/uartps_cfg.c

111
src/APP/Aufgabe6/ps7/core0/src/xttcps_g.c
View File

@@ -1,111 +0,0 @@
/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
*(a) running on a Xilinx device, or
*(b) that interact with a Xilinx device through a bus or interconnect.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Driver configuration
*
*******************************************************************/
#include "xparameters_ps.h"
#include "xparameters.h"
#include "xttcps.h"
/*
* The configuration table for devices
*/
XTtcPs_Config XTtcPs_ConfigTable[] =
{
{
XPAR_PS7_TTC_0_DEVICE_ID,
XPAR_PS7_TTC_0_BASEADDR,
XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ
},
{
XPAR_PS7_TTC_1_DEVICE_ID,
XPAR_PS7_TTC_1_BASEADDR,
XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ
},
{
XPAR_PS7_TTC_2_DEVICE_ID,
XPAR_PS7_TTC_2_BASEADDR,
XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ
}//,
// {
// XPAR_PS7_TTC_3_DEVICE_ID,
// XPAR_PS7_TTC_3_BASEADDR,
// XPAR_PS7_TTC_3_TTC_CLK_FREQ_HZ
// },
// {
// XPAR_PS7_TTC_4_DEVICE_ID,
// XPAR_PS7_TTC_4_BASEADDR,
// XPAR_PS7_TTC_4_TTC_CLK_FREQ_HZ
// },
// {
// XPAR_PS7_TTC_5_DEVICE_ID,
// XPAR_PS7_TTC_5_BASEADDR,
// XPAR_PS7_TTC_5_TTC_CLK_FREQ_HZ
// },
// {
// XPAR_PS7_TTC_6_DEVICE_ID,
// XPAR_PS7_TTC_6_BASEADDR,
// XPAR_PS7_TTC_6_TTC_CLK_FREQ_HZ
// },
// {
// XPAR_PS7_TTC_7_DEVICE_ID,
// XPAR_PS7_TTC_7_BASEADDR,
// XPAR_PS7_TTC_7_TTC_CLK_FREQ_HZ
// },
// {
// XPAR_PS7_TTC_8_DEVICE_ID,
// XPAR_PS7_TTC_8_BASEADDR,
// XPAR_PS7_TTC_8_TTC_CLK_FREQ_HZ
// },
// {
// XPAR_PS7_TTC_9_DEVICE_ID,
// XPAR_PS7_TTC_9_BASEADDR,
// XPAR_PS7_TTC_9_TTC_CLK_FREQ_HZ
// },
// {
// XPAR_PS7_TTC_10_DEVICE_ID,
// XPAR_PS7_TTC_10_BASEADDR,
// XPAR_PS7_TTC_10_TTC_CLK_FREQ_HZ
// },
// {
// XPAR_PS7_TTC_11_DEVICE_ID,
// XPAR_PS7_TTC_11_BASEADDR,
// XPAR_PS7_TTC_11_TTC_CLK_FREQ_HZ
// }
};

1
src/APP/Aufgabe6/ps7/core0/src/xttcps_g.c Symbolic link
View File

@@ -0,0 +1 @@
../../../../Aufgabe3/ps7/core0/src/xttcps_g.c

1
src/APP/Aufgabe7/ps7/core0/build/config.mk
View File

@@ -1,6 +1,5 @@
#µController dependent flags
MCFLAGS =-mcpu=cortex-a9 -march=armv7-a -mthumb -mthumb-interwork -mfloat-abi=softfp -mfpu=neon
#Optimization
OPTIMIZE=-O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections

5
src/APP/Aufgabe7/ps7/core0/build/sources.mk
View File

@@ -8,7 +8,7 @@ SRC += $(SRC_DIR)/ucos_v1_42/ucos/bsp/src/$(ARCH)/asm_vectors.S
SRC += $(SRC_DIR)/ucos_v1_42/ucos/components/ucos_osii/src/bsp/$(ARCH)/ucos_osii_bsp.c
SRC += $(SRC_DIR)/ucos_v1_42/ucos/components/ucos_common/src/$(ARCH)/cpu_bsp.c
SRC += $(SRC_DIR)/Modules/MMU/mmu.c
SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/main.c
SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/app_hooks.c
@@ -46,9 +46,6 @@ SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-Common/Auth/auth.c
-include $(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Source/subdir.mk
#mmu
SRC += $(SRC_DIR)/Modules/MMU/mmu.c
#src for triple timer counter
SRC +=$(SRC_DIR)/Xilinx/libsrc/ttcps_v3_5/src/xttcps.c

216
src/APP/Aufgabe7/ps7/core0/cfg/cpu_cfg.h
View File

@@ -1,216 +0,0 @@
/*
*********************************************************************************************************
* uC/CPU
* CPU CONFIGURATION & PORT LAYER
*
* (c) Copyright 2004-2015; Micrium, Inc.; Weston, FL
*
* All rights reserved. Protected by international copyright laws.
*
* uC/CPU is provided in source form to registered licensees ONLY. It is
* illegal to distribute this source code to any third party unless you receive
* written permission by an authorized Micrium representative. Knowledge of
* the source code may NOT be used to develop a similar product.
*
* Please help us continue to provide the Embedded community with the finest
* software available. Your honesty is greatly appreciated.
*
* You can find our product's user manual, API reference, release notes and
* more information at https://doc.micrium.com.
* You can contact us at www.micrium.com.
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* CPU CONFIGURATION FILE
*
* TEMPLATE
*
* Filename : cpu_cfg.h
* Version : V1.30.02
* Programmer(s) : SR
* ITJ
* JBL
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* MODULE
*********************************************************************************************************
*/
#ifndef CPU_CFG_MODULE_PRESENT
#define CPU_CFG_MODULE_PRESENT
/*
*********************************************************************************************************
* CPU NAME CONFIGURATION
*
* Note(s) : (1) Configure CPU_CFG_NAME_EN to enable/disable CPU host name feature :
*
* (a) CPU host name storage
* (b) CPU host name API functions
*
* (2) Configure CPU_CFG_NAME_SIZE with the desired ASCII string size of the CPU host name,
* including the terminating NULL character.
*
* See also 'cpu_core.h GLOBAL VARIABLES Note #1'.
*********************************************************************************************************
*/
/* Configure CPU host name feature (see Note #1) : */
#define CPU_CFG_NAME_EN DEF_DISABLED
/* DEF_DISABLED CPU host name DISABLED */
/* DEF_ENABLED CPU host name ENABLED */
/* Configure CPU host name ASCII string size ... */
#define CPU_CFG_NAME_SIZE 16
/*
*********************************************************************************************************
* CPU TIMESTAMP CONFIGURATION
*
* Note(s) : (1) Configure CPU_CFG_TS_xx_EN to enable/disable CPU timestamp features :
*
* (a) CPU_CFG_TS_32_EN enable/disable 32-bit CPU timestamp feature
* (b) CPU_CFG_TS_64_EN enable/disable 64-bit CPU timestamp feature
*
* (2) (a) Configure CPU_CFG_TS_TMR_SIZE with the CPU timestamp timer's word size :
*
* CPU_WORD_SIZE_08 8-bit word size
* CPU_WORD_SIZE_16 16-bit word size
* CPU_WORD_SIZE_32 32-bit word size
* CPU_WORD_SIZE_64 64-bit word size
*
* (b) If the size of the CPU timestamp timer is not a binary multiple of 8-bit octets
* (e.g. 20-bits or even 24-bits), then the next lower, binary-multiple octet word
* size SHOULD be configured (e.g. to 16-bits). However, the minimum supported word
* size for CPU timestamp timers is 8-bits.
*
* See also 'cpu_core.h FUNCTION PROTOTYPES CPU_TS_TmrRd() Note #2a'.
*********************************************************************************************************
*/
/* Configure CPU timestamp features (see Note #1) : */
#define CPU_CFG_TS_32_EN DEF_ENABLED
#define CPU_CFG_TS_64_EN DEF_ENABLED
/* DEF_DISABLED CPU timestamps DISABLED */
/* DEF_ENABLED CPU timestamps ENABLED */
/* Configure CPU timestamp timer word size ... */
/* ... (see Note #2) : */
#define CPU_CFG_TS_TMR_SIZE CPU_WORD_SIZE_64
/*
*********************************************************************************************************
* CPU INTERRUPTS DISABLED TIME MEASUREMENT CONFIGURATION
*
* Note(s) : (1) (a) Configure CPU_CFG_INT_DIS_MEAS_EN to enable/disable measuring CPU's interrupts
* disabled time :
*
* (a) Enabled, if CPU_CFG_INT_DIS_MEAS_EN #define'd in 'cpu_cfg.h'
*
* (b) Disabled, if CPU_CFG_INT_DIS_MEAS_EN NOT #define'd in 'cpu_cfg.h'
*
* See also 'cpu_core.h FUNCTION PROTOTYPES Note #1'.
*
* (b) Configure CPU_CFG_INT_DIS_MEAS_OVRHD_NBR with the number of times to measure &
* average the interrupts disabled time measurements overhead.
*
* See also 'cpu_core.c CPU_IntDisMeasInit() Note #3a'.
*********************************************************************************************************
*/
#if 0 /* Configure CPU interrupts disabled time ... */
#define CPU_CFG_INT_DIS_MEAS_EN /* ... measurements feature (see Note #1a). */
#endif
/* Configure number of interrupts disabled overhead ... */
#define CPU_CFG_INT_DIS_MEAS_OVRHD_NBR 1u /* ... time measurements (see Note #1b). */
/*
*********************************************************************************************************
* CPU COUNT ZEROS CONFIGURATION
*
* Note(s) : (1) (a) Configure CPU_CFG_LEAD_ZEROS_ASM_PRESENT to define count leading zeros bits
* function(s) in :
*
* (1) 'cpu_a.asm', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable assembly-optimized function(s)
*
* (2) 'cpu_core.c', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT NOT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
*
* (b) Configure CPU_CFG_TRAIL_ZEROS_ASM_PRESENT to define count trailing zeros bits
* function(s) in :
*
* (1) 'cpu_a.asm', if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable assembly-optimized function(s)
*
* (2) 'cpu_core.c', if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT NOT #define'd in 'cpu.h'/
* 'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
*********************************************************************************************************
*/
#if 0 /* Configure CPU count leading zeros bits ... */
#define CPU_CFG_LEAD_ZEROS_ASM_PRESENT /* ... assembly-version (see Note #1a). */
#endif
#if 0 /* Configure CPU count trailing zeros bits ... */
#define CPU_CFG_TRAIL_ZEROS_ASM_PRESENT /* ... assembly-version (see Note #1b). */
#endif
/*
*********************************************************************************************************
* CPU ENDIAN TYPE OVERRIDE
*
* Note(s) : (1) Configure CPU_CFG_ENDIAN_TYPE to override the default CPU endian type defined in cpu.h.
*
* (a) CPU_ENDIAN_TYPE_BIG Big- endian word order (CPU words' most significant
* octet @ lowest memory address)
* (b) CPU_ENDIAN_TYPE_LITTLE Little-endian word order (CPU words' least significant
* octet @ lowest memory address)
*
* (2) Defining CPU_CFG_ENDIAN_TYPE here is only valid for supported bi-endian architectures.
* See 'cpu.h CPU WORD CONFIGURATION Note #3' for details
*********************************************************************************************************
*/
#if 0
#define CPU_CFG_ENDIAN_TYPE CPU_ENDIAN_TYPE_BIG /* Defines CPU data word-memory order (see Note #2). */
#endif
/*
*********************************************************************************************************
* CACHE MANAGEMENT
*
* Note(s) : (1) Configure CPU_CFG_CACHE_MGMT_EN to enable the cache managment API.
*
* (2) Defining CPU_CFG_CACHE_MGMT_EN to DEF_ENABLED only enable the cache management function.
* Cache are assumed to be configured and enabled by the time CPU_init() is called.
*********************************************************************************************************
*/
#define CPU_CFG_CACHE_MGMT_EN DEF_DISABLED
/*
*********************************************************************************************************
* MODULE END
*********************************************************************************************************
*/
#endif /* End of CPU cfg module include. */
#define CPU_CACHE_CFG_L2C310_BASE_ADDR 0xF8F02000

1
src/APP/Aufgabe7/ps7/core0/cfg/cpu_cfg.h Symbolic link
View File

@@ -0,0 +1 @@
../../../../Aufgabe1/ps7/core0/cfg/cpu_cfg.h

24
src/APP/Aufgabe7/ps7/core0/cfg/gt_core_cfg.h
View File

@@ -1,24 +0,0 @@
/*
* gt_core_cfg.h
*
* Created on: Aug 19, 2014
* Author: matthiasb
*/
#ifndef GT_CORE_CFG_H_
#define GT_CORE_CFG_H_
#define GT_USE_CPU_ARM9 0
#define GT_USE_CPU_CM3 0
#define GT_USE_CPU_CM7 0
#define GT_USE_CPU_ARM_V7_A 1
#define GT_STACKSIZE 256
#define GT_MAXTASKS 10
#define GT_MAXQACT 5
#if ( GT_NUM_OF_TASKS > GT_MAXTASKS )
#error "Too many tasks, increase GT_MAXTASKS or decrease GT_NUM_OF_TASKS"
#endif
#endif /* GT_CORE_CFG_H_ */

1
src/APP/Aufgabe7/ps7/core0/cfg/gt_core_cfg.h Symbolic link
View File

@@ -0,0 +1 @@
../../../../Aufgabe6/ps7/core0/cfg/gt_core_cfg.h

19
src/APP/Aufgabe7/ps7/core0/cfg/imu.h
View File

@@ -1,19 +0,0 @@
/*
* imu.h
*
* Created on: Nov 6, 2018
* Author: laurenzb
*/
#ifndef SRC_APP_AUFGABE7_PS7_CORE0_CFG_IMU_H_
#define SRC_APP_AUFGABE7_PS7_CORE0_CFG_IMU_H_
#include <stdio.h>
#include "xiicps.h"
#include "xparameters.h"
//insert your imu-code from task 4
#endif /* SRC_APP_AUFGABE7_PS7_CORE0_CFG_IMU_H_ */

1
src/APP/Aufgabe7/ps7/core0/cfg/imu.h Symbolic link
View File

@@ -0,0 +1 @@
../../../../Aufgabe4/ps7/core0/cfg/imu.h

171
src/APP/Aufgabe7/ps7/core0/cfg/lib_cfg.h
View File

@@ -1,171 +0,0 @@
/*
*********************************************************************************************************
* EXAMPLE CODE
*
* This file is provided as an example on how to use Micrium products.
*
* Please feel free to use any application code labeled as 'EXAMPLE CODE' in
* your application products. Example code may be used as is, in whole or in
* part, or may be used as a reference only. This file can be modified as
* required to meet the end-product requirements.
*
* Please help us continue to provide the Embedded community with the finest
* software available. Your honesty is greatly appreciated.
*
* You can find information about uC/LIB by visiting doc.micrium.com.
* You can contact us at: http://www.micrium.com
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* CUSTOM LIBRARY CONFIGURATION FILE
*
* TEMPLATE
*
* Filename : lib_cfg.h
* Version : V1.38.01.00
* Programmer(s) : FBJ
* JFD
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* MODULE
*********************************************************************************************************
*/
#ifndef LIB_CFG_MODULE_PRESENT
#define LIB_CFG_MODULE_PRESENT
/*
*********************************************************************************************************
*********************************************************************************************************
* MEMORY LIBRARY CONFIGURATION
*********************************************************************************************************
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* MEMORY LIBRARY ARGUMENT CHECK CONFIGURATION
*
* Note(s) : (1) Configure LIB_MEM_CFG_ARG_CHK_EXT_EN to enable/disable the memory library suite external
* argument check feature :
*
* (a) When ENABLED, arguments received from any port interface provided by the developer
* or application are checked/validated.
*
* (b) When DISABLED, NO arguments received from any port interface provided by the developer
* or application are checked/validated.
*********************************************************************************************************
*/
/* External argument check. */
/* Indicates if arguments received from any port ... */
/* ... interface provided by the developer or ... */
/* ... application are checked/validated. */
#define LIB_MEM_CFG_ARG_CHK_EXT_EN DEF_DISABLED
/*
*********************************************************************************************************
* MEMORY LIBRARY ASSEMBLY OPTIMIZATION CONFIGURATION
*
* Note(s) : (1) Configure LIB_MEM_CFG_OPTIMIZE_ASM_EN to enable/disable assembly-optimized memory function(s).
*********************************************************************************************************
*/
/* Assembly-optimized function(s). */
/* Enable/disable assembly-optimized memory ... */
/* ... function(s). [see Note #1] */
#define LIB_MEM_CFG_OPTIMIZE_ASM_EN DEF_DISABLED
/*
*********************************************************************************************************
* MEMORY ALLOCATION CONFIGURATION
*
* Note(s) : (1) Configure LIB_MEM_CFG_DBG_INFO_EN to enable/disable memory allocation usage tracking
* that associates a name with each segment or dynamic pool allocated.
*
* (2) (a) Configure LIB_MEM_CFG_HEAP_SIZE with the desired size of heap memory (in octets).
*
* (b) Configure LIB_MEM_CFG_HEAP_BASE_ADDR to specify a base address for heap memory :
*
* (1) Heap initialized to specified application memory, if LIB_MEM_CFG_HEAP_BASE_ADDR
* #define'd in 'lib_cfg.h';
* CANNOT #define to address 0x0
*
* (2) Heap declared to Mem_Heap[] in 'lib_mem.c', if LIB_MEM_CFG_HEAP_BASE_ADDR
* NOT #define'd in 'lib_cfg.h'
*********************************************************************************************************
*/
/* Allocation debugging information. */
/* Enable/disable allocation of debug information ... */
/* ... associated to each memory allocation. */
#define LIB_MEM_CFG_DBG_INFO_EN DEF_DISABLED
/* Heap memory size (in bytes). */
/* Configure the desired size of the heap memory. ... */
/* ... Set to 0 to disable heap allocation features. */
#define LIB_MEM_CFG_HEAP_SIZE 64*1024
/* Heap memory padding alignment (in bytes). */
/* Configure the desired size of padding alignment ... */
/* ... of each buffer allocated from the heap. */
#define LIB_MEM_CFG_HEAP_PADDING_ALIGN LIB_MEM_PADDING_ALIGN_NONE
#if 0 /* Remove this to have heap alloc at specified addr. */
#define LIB_MEM_CFG_HEAP_BASE_ADDR 0
#endif
/*
*********************************************************************************************************
*********************************************************************************************************
* STRING LIBRARY CONFIGURATION
*********************************************************************************************************
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* STRING FLOATING POINT CONFIGURATION
*
* Note(s) : (1) Configure LIB_STR_CFG_FP_EN to enable/disable floating point string function(s).
*
* (2) Configure LIB_STR_CFG_FP_MAX_NBR_DIG_SIG to configure the maximum number of significant
* digits to calculate &/or display for floating point string function(s).
*
* See also 'lib_str.h STRING FLOATING POINT DEFINES Note #1'.
*********************************************************************************************************
*/
/* Floating point feature(s). */
/* Enable/disable floating point to string functions. */
#define LIB_STR_CFG_FP_EN DEF_DISABLED
/* Floating point number of significant digits. */
/* Configure the maximum number of significant ... */
/* ... digits to calculate &/or display for ... */
/* ... floating point string function(s). */
#define LIB_STR_CFG_FP_MAX_NBR_DIG_SIG LIB_STR_FP_MAX_NBR_DIG_SIG_DFLT
/*
*********************************************************************************************************
* MODULE END
*********************************************************************************************************
*/
#endif /* End of lib cfg module include. */

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