From 6999fa3f2de093835794a5f163139e1c1c0ccc81 Mon Sep 17 00:00:00 2001
From: Eggert Jung <eggert.s.jung@wischhof13.de>
Date: Mon, 31 Aug 2020 03:47:09 +0200
Subject: [PATCH] Freerunning ADC with DMA; 1024 averaging

---
 newcode/main.c | 50 +++++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 45 insertions(+), 5 deletions(-)

diff --git a/newcode/main.c b/newcode/main.c
index 2bb3b91..dc00df8 100644
--- a/newcode/main.c
+++ b/newcode/main.c
@@ -6,7 +6,9 @@
 #include <stddef.h>
 #include "yaMBSiavr.h"
 
-uint16_t inputStatus[9];
+#define AVRG 1024
+
+uint16_t adc_values[AVRG];
 
 void init_clk(void)
 {
@@ -34,12 +36,12 @@ void init_clk(void)
 
 void init_timer_100us(){
     TCC0.CTRLA |= TC_CLKSEL_DIV256_gc;
-    TCC0.PER = 13; // ==> 9615us
+    TCC0.PER = 13; // ==> 9615Hz
     TCC0.INTCTRLA |= TC_OVFINTLVL_MED_gc;
 }
 
 void adc_init(void){
-    ADCA.CTRLB = 0x00;
+    ADCA.CTRLB = ADC_FREERUN_bm;
     ADCA.REFCTRL = ADC_REFSEL_VCC_gc;
     ADCA.PRESCALER = ADC_PRESCALER_DIV512_gc;
 
@@ -65,15 +67,49 @@ uint16_t adc_read(void){
     return ADCA.CH0.RES;
 }
 
+float avrg(uint16_t * values, uint16_t length){
+    uint64_t res = 0;
+    for(uint16_t i=0; i < length; i++){
+        res += values[i];
+    }
+    return (float)(res)/length;
+}
+
+void dma_init(void){
+    DMA.CTRL = DMA_ENABLE_bm;
+
+    //DMA.CH0.CTRLB = DMA_CH_TRNINTLVL_LO_gc;
+
+    DMA.CH0.TRFCNT = AVRG * 2;
+    DMA.CH0.CTRLA = DMA_CH_BURSTLEN_2BYTE_gc | DMA_CH_SINGLE_bm;
+    DMA.CH0.TRIGSRC = DMA_CH_TRIGSRC_ADCA_CH0_gc;
+
+    //repeat endless
+    DMA.CH0.CTRLA |= DMA_CH_REPEAT_bm;
+    DMA.CH0.REPCNT = 0;
+
+    DMA.CH0.SRCADDR0 = ((uintptr_t)&ADCA.CH0.RES) & 0xFF;
+    DMA.CH0.SRCADDR1 = (((uintptr_t)&ADCA.CH0.RES) >> 0x08) & 0xFF;
+    DMA.CH0.SRCADDR2 = (((uintptr_t)&ADCA.CH0.RES) >> 0x0F) & 0xFF;
+
+    DMA.CH0.DESTADDR0 = ((uintptr_t)adc_values) & 0xFF;
+    DMA.CH0.DESTADDR1 = ((uintptr_t)adc_values >> 0x08) & 0xFF;
+    DMA.CH0.DESTADDR2 = ((uintptr_t)adc_values >> 0x0F) & 0xFF;
+
+    DMA.CH0.ADDRCTRL = DMA_CH_SRCRELOAD_BURST_gc | DMA_CH_DESTRELOAD_TRANSACTION_gc | DMA_CH_SRCDIR_INC_gc | DMA_CH_DESTDIR_INC_gc;
+
+    DMA.CH0.CTRLA |= DMA_CH_ENABLE_bm;
+}
+
 void modbusGet(void) {
 	if (modbusGetBusState() & (1<<ReceiveCompleted))
     {
         switch(rxbuffer[1]) {
             case fcReadHoldingRegisters: ;
                 float tmp[4];
-                tmp[0] = adc_read() - 170;
+                tmp[0] = avrg(adc_values, AVRG) - 170;
                 tmp[1] = (tmp[0])/ 3926 * 1.95;
-                tmp[2] = (tmp[1]*993)/(3.3-tmp[1]);
+                tmp[2] = (tmp[1]*980)/(3.3-tmp[1]);
                 tmp[3] = (tmp[2]-100)/0.3927;
                 modbusExchangeRegisters(tmp, 0, 8);
                 break;
@@ -87,8 +123,12 @@ void modbusGet(void) {
 int main(void){
     init_clk();
     PORTD.DIRSET = 1 << 5;
+    PORTD.OUTTGL = 1 << 5;
+    _delay_ms(500);
+    PORTD.OUTTGL = 1 << 5;
 
     adc_init();
+    dma_init();
 
     PORTCFG.MPCMASK = 0xFF;
     PORTC.PIN1CTRL = PORT_OPC_PULLUP_gc;