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@ -6,9 +6,11 @@
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#include <stddef.h>
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#include <stddef.h>
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#include "yaMBSiavr.h"
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#include "yaMBSiavr.h"
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#define AVRG 1024
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#define AVRG 512
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volatile uint16_t adc_buffer[AVRG];
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volatile float ch_values[9];
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uint16_t adc_values[AVRG];
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void init_clk(void)
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void init_clk(void)
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{
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{
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@ -37,7 +39,7 @@ void init_clk(void)
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void init_timer_100us(){
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void init_timer_100us(){
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TCC0.CTRLA |= TC_CLKSEL_DIV256_gc;
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TCC0.CTRLA |= TC_CLKSEL_DIV256_gc;
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TCC0.PER = 13; // ==> 9615Hz
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TCC0.PER = 13; // ==> 9615Hz
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TCC0.INTCTRLA |= TC_OVFINTLVL_MED_gc;
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TCC0.INTCTRLA |= TC_OVFINTLVL_HI_gc;
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}
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}
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void adc_init(void){
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void adc_init(void){
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@ -69,16 +71,17 @@ uint16_t adc_read(void){
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float avrg(uint16_t * values, uint16_t length){
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float avrg(uint16_t * values, uint16_t length){
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uint64_t res = 0;
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uint64_t res = 0;
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for(uint16_t i=0; i < length; i++){
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//ommit first and last sample
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for(uint16_t i=1; i < length-1; i++){
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res += values[i];
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res += values[i];
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}
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}
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return (float)(res)/length;
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return (float)(res)/(length-2);
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}
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}
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void dma_init(void){
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void dma_init(void){
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DMA.CTRL = DMA_ENABLE_bm;
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DMA.CTRL = DMA_ENABLE_bm;
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//DMA.CH0.CTRLB = DMA_CH_TRNINTLVL_LO_gc;
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DMA.CH0.CTRLB = DMA_CH_TRNINTLVL_LO_gc;
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DMA.CH0.TRFCNT = AVRG * 2;
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DMA.CH0.TRFCNT = AVRG * 2;
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DMA.CH0.CTRLA = DMA_CH_BURSTLEN_2BYTE_gc | DMA_CH_SINGLE_bm;
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DMA.CH0.CTRLA = DMA_CH_BURSTLEN_2BYTE_gc | DMA_CH_SINGLE_bm;
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@ -92,9 +95,9 @@ void dma_init(void){
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DMA.CH0.SRCADDR1 = (((uintptr_t)&ADCA.CH0.RES) >> 0x08) & 0xFF;
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DMA.CH0.SRCADDR1 = (((uintptr_t)&ADCA.CH0.RES) >> 0x08) & 0xFF;
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DMA.CH0.SRCADDR2 = (((uintptr_t)&ADCA.CH0.RES) >> 0x0F) & 0xFF;
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DMA.CH0.SRCADDR2 = (((uintptr_t)&ADCA.CH0.RES) >> 0x0F) & 0xFF;
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DMA.CH0.DESTADDR0 = ((uintptr_t)adc_values) & 0xFF;
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DMA.CH0.DESTADDR0 = ((uintptr_t)adc_buffer) & 0xFF;
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DMA.CH0.DESTADDR1 = ((uintptr_t)adc_values >> 0x08) & 0xFF;
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DMA.CH0.DESTADDR1 = ((uintptr_t)adc_buffer >> 0x08) & 0xFF;
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DMA.CH0.DESTADDR2 = ((uintptr_t)adc_values >> 0x0F) & 0xFF;
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DMA.CH0.DESTADDR2 = ((uintptr_t)adc_buffer >> 0x0F) & 0xFF;
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DMA.CH0.ADDRCTRL = DMA_CH_SRCRELOAD_BURST_gc | DMA_CH_DESTRELOAD_TRANSACTION_gc | DMA_CH_SRCDIR_INC_gc | DMA_CH_DESTDIR_INC_gc;
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DMA.CH0.ADDRCTRL = DMA_CH_SRCRELOAD_BURST_gc | DMA_CH_DESTRELOAD_TRANSACTION_gc | DMA_CH_SRCDIR_INC_gc | DMA_CH_DESTDIR_INC_gc;
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@ -106,12 +109,7 @@ void modbusGet(void) {
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{
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{
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switch(rxbuffer[1]) {
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switch(rxbuffer[1]) {
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case fcReadHoldingRegisters: ;
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case fcReadHoldingRegisters: ;
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float tmp[4];
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modbusExchangeRegisters(ch_values, 0, 18);
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tmp[0] = avrg(adc_values, AVRG) - 170;
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tmp[1] = (tmp[0])/ 3926 * 1.95;
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tmp[2] = (tmp[1]*980)/(3.3-tmp[1]);
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tmp[3] = (tmp[2]-100)/0.3927;
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modbusExchangeRegisters(tmp, 0, 8);
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break;
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break;
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default:
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default:
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modbusSendException(ecIllegalFunction);
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modbusSendException(ecIllegalFunction);
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@ -149,3 +147,25 @@ int main(void){
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ISR(TCC0_OVF_vect){
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ISR(TCC0_OVF_vect){
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modbusTickTimer();
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modbusTickTimer();
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}
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}
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ISR(DMA_CH0_vect){
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static uint8_t pin = 0;
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DMA.INTFLAGS |= DMA_CH0TRNIF_bm; // clear flag
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DMA.CH0.TRIGSRC = DMA_CH_TRIGSRC_OFF_gc;
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ADCA.CTRLB = 0; // stop ADC
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uint8_t old_pin = pin;
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pin=(pin+1)%1;
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ADCA.CH0.MUXCTRL = pin << ADC_CH_MUXPOS_gp; // give MUX time to switch during averaging
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float temp = avrg(adc_buffer, AVRG);
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temp = temp - 170;
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temp = (temp)/ 3926 * 1.95;
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temp = (temp*993.5)/(3.3-temp);
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temp = (temp-100)/0.3927;
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ch_values[old_pin] = temp;
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DMA.CH0.TRIGSRC = DMA_CH_TRIGSRC_ADCA_CH0_gc;
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ADCA.CTRLB = ADC_FREERUN_bm; // start ADC again
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}
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