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152 lines
4.2 KiB
C
152 lines
4.2 KiB
C
#include <avr/io.h>
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#include <util/delay.h>
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#include <avr/interrupt.h>
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#include <avr/pgmspace.h>
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#include <stdlib.h>
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#include <stddef.h>
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#include "yaMBSiavr.h"
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#define AVRG 1024
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uint16_t adc_values[AVRG];
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void init_clk(void)
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{
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// ========= System Clock configuration =========
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// Set to external 16Mhz crystal, using the PLL at *2
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// set it to be a 12-16Mhz crystal with a slow start-up time.
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OSC.XOSCCTRL = OSC_FRQRANGE_2TO9_gc | OSC_XOSCSEL_XTAL_16KCLK_gc ;
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OSC.CTRL |= OSC_XOSCEN_bm ; // enable it
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while( (OSC.STATUS & OSC_XOSCRDY_bm) == 0 ){} // wait until it's stable
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// The external crystal is now running and stable.
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// (Note that it's not yet selected as the clock source)
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// Now configure the PLL to be eXternal oscillator * 2
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OSC.PLLCTRL = OSC_PLLSRC_XOSC_gc | 2;
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// now enable the PLL...
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OSC.CTRL |= OSC_PLLEN_bm ; // enable the PLL...
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while( (OSC.STATUS & OSC_PLLRDY_bm) == 0 ){} // wait until it's stable
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// And now, *finally*, we can switch from the internal 2Mhz clock to the PLL
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CCP = CCP_IOREG_gc; // protected write follows
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CLK.CTRL = CLK_SCLKSEL_PLL_gc; // The System clock is now PLL (16Mhz * 2)
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// ==============================================
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}
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void init_timer_100us(){
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TCC0.CTRLA |= TC_CLKSEL_DIV256_gc;
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TCC0.PER = 13; // ==> 9615Hz
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TCC0.INTCTRLA |= TC_OVFINTLVL_MED_gc;
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}
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void adc_init(void){
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ADCA.CTRLB = ADC_FREERUN_bm;
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ADCA.REFCTRL = ADC_REFSEL_VCC_gc;
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ADCA.PRESCALER = ADC_PRESCALER_DIV512_gc;
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uint8_t CalibrationByteL;
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uint8_t CalibrationByteH;
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NVM_CMD = NVM_CMD_READ_CALIB_ROW_gc;
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CalibrationByteL = pgm_read_byte(offsetof(NVM_PROD_SIGNATURES_t, ADCACAL0));
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CalibrationByteH = pgm_read_byte(offsetof(NVM_PROD_SIGNATURES_t, ADCACAL1));
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NVM_CMD = NVM_CMD_NO_OPERATION_gc;
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ADCA.CALL = CalibrationByteL;
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ADCA.CALH = CalibrationByteH;
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ADCA.CTRLA = ADC_ENABLE_bm;
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ADCA.CH0.CTRL = ADC_CH_INPUTMODE_SINGLEENDED_gc;
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ADCA.CH0.MUXCTRL = ADC_CH_MUXPOS_PIN0_gc;
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}
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uint16_t adc_read(void){
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ADCA.CH0.CTRL |= ADC_CH_START_bm;
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while(!(ADCA.CH0.INTFLAGS & ADC_CH_CHIF_bm));
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ADCA.CH0.INTFLAGS = ADC_CH_CHIF_bm;
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return ADCA.CH0.RES;
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}
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float avrg(uint16_t * values, uint16_t length){
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uint64_t res = 0;
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for(uint16_t i=0; i < length; i++){
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res += values[i];
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}
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return (float)(res)/length;
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}
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void dma_init(void){
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DMA.CTRL = DMA_ENABLE_bm;
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//DMA.CH0.CTRLB = DMA_CH_TRNINTLVL_LO_gc;
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DMA.CH0.TRFCNT = AVRG * 2;
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DMA.CH0.CTRLA = DMA_CH_BURSTLEN_2BYTE_gc | DMA_CH_SINGLE_bm;
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DMA.CH0.TRIGSRC = DMA_CH_TRIGSRC_ADCA_CH0_gc;
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//repeat endless
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DMA.CH0.CTRLA |= DMA_CH_REPEAT_bm;
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DMA.CH0.REPCNT = 0;
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DMA.CH0.SRCADDR0 = ((uintptr_t)&ADCA.CH0.RES) & 0xFF;
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DMA.CH0.SRCADDR1 = (((uintptr_t)&ADCA.CH0.RES) >> 0x08) & 0xFF;
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DMA.CH0.SRCADDR2 = (((uintptr_t)&ADCA.CH0.RES) >> 0x0F) & 0xFF;
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DMA.CH0.DESTADDR0 = ((uintptr_t)adc_values) & 0xFF;
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DMA.CH0.DESTADDR1 = ((uintptr_t)adc_values >> 0x08) & 0xFF;
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DMA.CH0.DESTADDR2 = ((uintptr_t)adc_values >> 0x0F) & 0xFF;
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DMA.CH0.ADDRCTRL = DMA_CH_SRCRELOAD_BURST_gc | DMA_CH_DESTRELOAD_TRANSACTION_gc | DMA_CH_SRCDIR_INC_gc | DMA_CH_DESTDIR_INC_gc;
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DMA.CH0.CTRLA |= DMA_CH_ENABLE_bm;
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}
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void modbusGet(void) {
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if (modbusGetBusState() & (1<<ReceiveCompleted))
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{
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switch(rxbuffer[1]) {
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case fcReadHoldingRegisters: ;
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float tmp[4];
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tmp[0] = avrg(adc_values, AVRG) - 170;
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tmp[1] = (tmp[0])/ 3926 * 1.95;
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tmp[2] = (tmp[1]*980)/(3.3-tmp[1]);
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tmp[3] = (tmp[2]-100)/0.3927;
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modbusExchangeRegisters(tmp, 0, 8);
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break;
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default:
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modbusSendException(ecIllegalFunction);
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break;
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}
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}
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}
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int main(void){
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init_clk();
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PORTD.DIRSET = 1 << 5;
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PORTD.OUTTGL = 1 << 5;
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_delay_ms(500);
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PORTD.OUTTGL = 1 << 5;
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adc_init();
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dma_init();
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PORTCFG.MPCMASK = 0xFF;
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PORTC.PIN1CTRL = PORT_OPC_PULLUP_gc;
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init_timer_100us();
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PMIC.CTRL |= PMIC_LOLVLEN_bm | PMIC_MEDLVLEN_bm | PMIC_HILVLEN_bm;
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sei();
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modbusSetAddress(1);
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modbusInit();
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for(;;){
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modbusGet();
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}
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}
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ISR(TCC0_OVF_vect){
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modbusTickTimer();
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}
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