/*! \file
 *  \brief Access to \ref Core::CR "Control Register" of a \ref Core "CPU core"
 */

#pragma once
#include "../types.h"

namespace Core {
/*! \brief Control Register 0
 *
 * \see [ISDMv3, 2.5 Control Registers](intel_manual_vol3.pdf#page=74)
 */
enum class CR0 : uint32_t {
	PE = 1U << 0,	///< Protected Mode enabled
	MP = 1U << 1,	///< Monitor co-processor
	EM = 1U << 2,	///< Emulation (no x87 floating-point unit present)
	TS = 1U << 3,	///< Task switched
	ET = 1U << 4,	///< Extension type
	NE = 1U << 15,	///< Numeric error
	WP = 1U << 16,	///< Write protect
	AM = 1U << 18,	///< Alignment mask
	NW = 1U << 29,	///< Not-write through caching
	CD = 1U << 30,	///< Cache disable
	PG = 1U << 31,	///< Paging
};

/*! \brief Control Register 4
 *
 * \see [ISDMv3, 2.5 Control Registers](intel_manual_vol3.pdf#page=77)
 */
enum class CR4 : uint32_t {
	VME = 1U << 0,	///< Virtual 8086 Mode Extensions
	PVI = 1U << 1,	///< Protected-mode Virtual Interrupts
	TSD = 1U << 2,	///< Time Stamp Disable
	DE = 1U << 3,	///< Debugging Extensions
	PSE = 1U << 4,	///< Page Size Extension
	PAE = 1U << 5,	///< Physical Address Extension
	MCE = 1U << 6,	///< Machine Check Exception
	PGE = 1U << 7,	///< Page Global Enabled
	PCE = 1U << 8,	///< Performance-Monitoring Counter enable
	/// Operating system support for FXSAVE and FXRSTOR instructions
	OSFXSR = 1U << 9,
	OSXMMEXCPT = 1U << 10,	///< Operating System Support for Unmasked SIMD
	///< Floating-Point Exceptions
	UMIP = 1U << 11,	  ///< User-Mode Instruction Prevention
	VMXE = 1U << 13,	  ///< Virtual Machine Extensions Enable
	SMXE = 1U << 14,	  ///< Safer Mode Extensions Enable
	FSGSBASE = 1U << 16,  ///< Enables the instructions RDFSBASE, RDGSBASE,
	///< WRFSBASE, and WRGSBASE.
	PCIDE = 1U << 17,	 ///< PCID Enable
	OSXSAVE = 1U << 18,	 ///< XSAVE and Processor Extended States Enable
	SMEP = 1U << 20,	 ///< Supervisor Mode Execution Protection Enable
	SMAP = 1U << 21,	 ///< Supervisor Mode Access Prevention Enable
	PKE = 1U << 22,		 ///< Protection Key Enable
};

/*! \brief Access to the Control Register
 *
 * \see [ISDMv3, 2.5 Control Registers](intel_manual_vol3.pdf#page=73)
 * \tparam id Control Register to access
 */
template <uint8_t id>
class CR {
   public:
	/*! \brief Read the value of the current Control Register
	 *
	 * \return Value stored in the CR
	 */
	static uintptr_t read(void) {
		uintptr_t val;
		asm volatile("mov %%cr%c1, %0" : "=r"(val) : "n"(id));
		return val;
	}

	/*! \brief Write a value into the current Control Register
	 *
	 * \param value Value to write into the CR
	 */
	static void write(uintptr_t value) {
		asm volatile("mov %0, %%cr%c1" : : "r"(value), "n"(id));
	}
};
}  // namespace Core