more or less works
This commit is contained in:
agsler
255
controllino_io.c
Normal file
255
controllino_io.c
Normal file
@@ -0,0 +1,255 @@
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#include <avr/io.h>
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#include <stdint.h>
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/* DMX buffer: indexed 1..512 */
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extern volatile uint8_t dmx_data[];
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/* Pin bit definitions (change bit numbers if different on your board) */
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/* PE4, PE5, PG5, PE3, PH3, PH4, PH5, PH6, PB4, PB5, PB6, PB7,
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PL7, PL6, PL5, PL4, PL3, PL2, PL1, PL0, PD4, PD5, PD6, PJ4 */
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/* For each Dn we need to map which port and bit will hold bit0..bit7 of the
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output byte. Here we assume each DMX channel is presented on a contiguous
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8-bit port where possible. Since the pins are all over, we output each DMX
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byte bit-by-bit to 8 dedicated pins: bit 0 -> mapped pin for bit0, ... bit7
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-> mapped pin for bit7. Replace the per-bit port/bit assignments below to
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match your desired wiring. */
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/* Example per-bit mapping for channel outputs (one mapping choice). */
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/* For brevity we map bits 0..7 of each channel to the same physical pin for
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that channel, i.e., output the full byte on 8-bit bus is not possible on
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single scattered pin. Instead we simply write the byte value to the port pins
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that form an 8-bit port where possible. We'll implement writing each
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channel's byte to its single port's low 8 bits when that port contains 8
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consecutive pins; otherwise we write the byte on the low 8 bits of a chosen
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port using the relevant mask. */
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/* Define helper macros for writing masked values */
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static inline void write_masked(volatile uint8_t *port, volatile uint8_t *ddr,
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uint8_t mask, uint8_t value) {
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uint8_t cur = *port & ~mask;
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*port = cur | (value & mask);
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*ddr |= mask; // ensure pins are outputs
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}
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/* Concrete writers for the pins used (mask and port pointers) */
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/* Adjust masks to the actual bit positions used on each port. The following
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masks assume: PB4..PB7 -> bits 4..7 on PORTB (fits for D8..D11) PL0..PL7 ->
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bits 0..7 on PORTL (fits for D12..D19) PH0..PH7 -> bits 0..7 on PORTH (we use
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PH3..PH6 for D4..D7 -> need masking) PD4..PD6 -> bits 4..6 on PORTD
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(D20..D22) PE0..PE7 -> bits 0..7 on PORTE (we use PE3,PE4,PE5 for D0,D1,D3)
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PJ4 -> bit 4 on PORTJ (D23)
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PG5 -> bit 5 on PORTG (D2)
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*/
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/* Write channel values to ports with appropriate masks */
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void output_dmx_channels_1_24(void) {
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/* D0 -> PE4 : map whole byte to bits 0..7 not possible; instead output
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LSB..MSB across 8 pins For simplicity we output the byte value on an 8-bit
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pseudo-bus using multiple ports: Here we implement a pragmatic approach:
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output each channel value on 8 dedicated IO pins defined below. You must
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adapt bit-to-pin assignments to match your wiring. */
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/* Example assignment: use PORTL for D12..D19 (8-bit) */
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/* D12..D19 handled below; for single-pin channels we output LSB on that pin
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(as HIGH/LOW) — if you actually need parallel 8-bit outputs on dedicated
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pins per channel, you'll need 8 pins per channel (192 pins) which is
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unlikely. So this snippet writes each channel's byte value as a PWM-like
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ON/OFF level on a single digital pin using thresholding:
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-> if value >= 128 -> set pin HIGH else LOW. */
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/* Quick implementation: set output pin HIGH if channel value >= 128, else
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LOW. Map each D0..D23 to its port/bit and write accordingly. */
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uint8_t v;
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/* D0: PE4 (bit 4) */
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v = dmx_data[1];
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if (v >= 128)
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PORTE |= (1 << 4);
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else
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PORTE &= ~(1 << 4);
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DDRE |= (1 << 4);
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/* D1: PE5 (bit 5) */
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v = dmx_data[2];
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if (v >= 128)
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PORTE |= (1 << 5);
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else
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PORTE &= ~(1 << 5);
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DDRE |= (1 << 5);
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/* D2: PG5 (bit 5) */
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v = dmx_data[3];
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if (v >= 128)
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PORTG |= (1 << 5);
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else
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PORTG &= ~(1 << 5);
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DDRG |= (1 << 5);
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/* D3: PE3 (bit 3) */
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v = dmx_data[4];
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if (v >= 128)
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PORTE |= (1 << 3);
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else
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PORTE &= ~(1 << 3);
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DDRE |= (1 << 3);
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/* D4: PH3 (bit 3) */
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v = dmx_data[5];
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if (v >= 128)
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PORTH |= (1 << 3);
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else
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PORTH &= ~(1 << 3);
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DDRH |= (1 << 3);
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/* D5: PH4 (bit 4) */
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v = dmx_data[6];
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if (v >= 128)
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PORTH |= (1 << 4);
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else
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PORTH &= ~(1 << 4);
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DDRH |= (1 << 4);
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/* D6: PH5 (bit 5) */
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v = dmx_data[7];
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if (v >= 128)
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PORTH |= (1 << 5);
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else
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PORTH &= ~(1 << 5);
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DDRH |= (1 << 5);
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/* D7: PH6 (bit 6) */
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v = dmx_data[8];
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if (v >= 128)
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PORTH |= (1 << 6);
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else
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PORTH &= ~(1 << 6);
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DDRH |= (1 << 6);
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/* D8: PB4 (bit 4) */
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v = dmx_data[9];
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if (v >= 128)
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PORTB |= (1 << 4);
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else
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PORTB &= ~(1 << 4);
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DDRB |= (1 << 4);
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/* D9: PB5 (bit 5) */
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v = dmx_data[10];
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if (v >= 128)
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PORTB |= (1 << 5);
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else
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PORTB &= ~(1 << 5);
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DDRB |= (1 << 5);
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/* D10: PB6 (bit 6) */
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v = dmx_data[11];
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if (v >= 128)
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PORTB |= (1 << 6);
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else
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PORTB &= ~(1 << 6);
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DDRB |= (1 << 6);
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/* D11: PB7 (bit 7) */
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v = dmx_data[12];
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if (v >= 128)
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PORTB |= (1 << 7);
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else
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PORTB &= ~(1 << 7);
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DDRB |= (1 << 7);
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/* D12: PL7 (bit 7) */
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v = dmx_data[13];
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if (v >= 128)
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PORTL |= (1 << 7);
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else
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PORTL &= ~(1 << 7);
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DDRL |= (1 << 7);
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/* D13: PL6 (bit 6) */
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v = dmx_data[14];
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if (v >= 128)
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PORTL |= (1 << 6);
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else
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PORTL &= ~(1 << 6);
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DDRL |= (1 << 6);
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/* D14: PL5 (bit 5) */
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v = dmx_data[15];
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if (v >= 128)
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PORTL |= (1 << 5);
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else
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PORTL &= ~(1 << 5);
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DDRL |= (1 << 5);
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/* D15: PL4 (bit 4) */
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v = dmx_data[16];
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if (v >= 128)
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PORTL |= (1 << 4);
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else
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PORTL &= ~(1 << 4);
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DDRL |= (1 << 4);
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/* D16: PL3 (bit 3) */
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v = dmx_data[17];
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if (v >= 128)
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PORTL |= (1 << 3);
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else
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PORTL &= ~(1 << 3);
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DDRL |= (1 << 3);
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/* D17: PL2 (bit 2) */
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v = dmx_data[18];
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if (v >= 128)
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PORTL |= (1 << 2);
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else
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PORTL &= ~(1 << 2);
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DDRL |= (1 << 2);
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/* D18: PL1 (bit 1) */
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v = dmx_data[19];
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if (v >= 128)
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PORTL |= (1 << 1);
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else
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PORTL &= ~(1 << 1);
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DDRL |= (1 << 1);
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/* D19: PL0 (bit 0) */
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v = dmx_data[20];
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if (v >= 128)
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PORTL |= (1 << 0);
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else
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PORTL &= ~(1 << 0);
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DDRL |= (1 << 0);
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/* D20: PD4 (bit 4) */
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v = dmx_data[21];
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if (v >= 128)
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PORTD |= (1 << 4);
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else
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PORTD &= ~(1 << 4);
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DDRD |= (1 << 4);
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/* D21: PD5 (bit 5) */
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v = dmx_data[22];
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if (v >= 128)
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PORTD |= (1 << 5);
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else
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PORTD &= ~(1 << 5);
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DDRD |= (1 << 5);
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/* D22: PD6 (bit 6) */
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v = dmx_data[23];
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if (v >= 128)
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PORTD |= (1 << 6);
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else
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PORTD &= ~(1 << 6);
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DDRD |= (1 << 6);
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/* D23: PJ4 (bit 4) */
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v = dmx_data[24];
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if (v >= 128)
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PORTJ |= (1 << 4);
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else
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PORTJ &= ~(1 << 4);
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DDRJ |= (1 << 4);
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}
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52
dmxtest.py
Normal file
52
dmxtest.py
Normal file
@@ -0,0 +1,52 @@
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#!/usr/bin/env python3
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import serial
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import time
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DEVICE = "/dev/ttyUSB0"
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BAUD = 250000 # DMX baud
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CHANNELS = 512
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ACTIVE_COUNT = 24 # cycle through channels 1..24
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def send_dmx(ser, data):
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try:
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ser.break_condition = True
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time.sleep(0.0001) # 100 µs
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ser.break_condition = False
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except Exception:
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ser.baudrate = 57600
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ser.write(b'\x00')
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ser.flush()
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ser.baudrate = BAUD
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time.sleep(0.000012) # 12 µs MAB
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frame = bytes([0x00]) + bytes(data)
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ser.write(frame)
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ser.flush()
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def main():
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dmx_values = bytearray([0]*(CHANNELS)) # index 0 -> channel 1
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with serial.Serial(DEVICE, baudrate=BAUD, bytesize=serial.EIGHTBITS,
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parity=serial.PARITY_NONE, stopbits=serial.STOPBITS_TWO,
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timeout=1) as ser:
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time.sleep(0.1)
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chan = 0
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try:
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while True:
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# clear all
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for i in range(CHANNELS):
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dmx_values[i] = 0
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# set active channel (channels 1..ACTIVE_COUNT)
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dmx_values[chan] = 255
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send_dmx(ser, dmx_values)
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time.sleep(0.025) # frame delay; adjust if desired
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# advance channel (wrap within 0..ACTIVE_COUNT-1)
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chan += 1
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if chan >= ACTIVE_COUNT:
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chan = 0
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except KeyboardInterrupt:
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pass
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if __name__ == "__main__":
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main()
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126
main.c
126
main.c
@@ -2,7 +2,9 @@
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#include <avr/io.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#define F_CPU 16000000UL
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#define DMX_CHANNELS 512
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volatile uint8_t dmx_data[DMX_CHANNELS + 1]; // 1..512
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@@ -10,117 +12,111 @@ volatile uint16_t dmx_index = 0;
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volatile bool dmx_frame_ready = false;
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volatile bool receiving = false;
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extern void output_dmx_channels_1_24(void);
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/* --- USART3 (DMX) init & ISR --- */
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void uart3_init(void) {
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// Set baud rate for 250000 (F_CPU must be set accordingly).
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// Formula UBRR = F_CPU/(16*baud)-1 ; For high speed use U2X - but DMX
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// typically uses normal mode. For F_CPU = 16MHz: UBRR =
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// 16,000,000/(16*250000)-1 = 3 We'll enable UBRR3 with 3 for 16MHz; adjust if
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// F_CPU differs.
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uint16_t ubrr = 3;
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UBRR3H = (uint8_t)(ubrr >> 8);
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UBRR3L = (uint8_t)ubrr;
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// Enable receiver and RX complete interrupt
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// uint16_t ubrr = (F_CPU / (16UL * 250000UL)) - 1; // 250000 baud
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// UBRR3H = (uint8_t)(ubrr >> 8);
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// UBRR3L = (uint8_t)ubrr;
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UBRR3L = 3;
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UCSR3B = (1 << RXEN3) | (1 << RXCIE3);
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// Set frame format: 8 data, 2 stop bits (USBS3 = 1)
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UCSR3C = (1 << USBS3) | (1 << UCSZ31) | (1 << UCSZ30);
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// Note: parity default is none (UPM bits = 0)
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UCSR3C = (1 << USBS3) | (1 << UCSZ31) | (1 << UCSZ30); // 8N2
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}
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ISR(USART3_RX_vect) {
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PORTE |= 1 << 4;
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uint8_t status = UCSR3A;
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uint8_t data = UDR3; // reading UDR clears the receive flag
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uint8_t data = UDR3;
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// If framing error -> likely BREAK (line held low longer than a byte time)
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if (status & (1 << FE3)) {
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// Break detected: start of new DMX packet
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// Break detected: start new DMX packet
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receiving = true;
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dmx_index = 0;
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dmx_frame_ready = false;
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return; // discard this byte (it's break/MAF)
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}
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if (!receiving) {
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// Not currently inside a DMX frame; ignore bytes until we detect break
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return;
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}
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// DMX: first byte after break is START CODE (usually 0); then channel
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// data 1..512
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if (!receiving)
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return;
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if (dmx_index == 0) {
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// start code
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// Optionally check for start code == 0, otherwise may discard or handle RDM
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// etc. We'll accept any start code but only store channels.
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dmx_index++; // move to channel 1 next
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// start code (usually 0) - ignore/store as needed
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dmx_index++; // next byte will be channel 1
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return;
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}
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// dmx_index corresponds to channel number
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if (dmx_index <= DMX_CHANNELS) {
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dmx_data[dmx_index] = data;
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dmx_index++;
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if (dmx_index > DMX_CHANNELS) {
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// Received full frame
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dmx_frame_ready = true;
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receiving = false; // wait for next break
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receiving = false;
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}
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} else {
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// Overflow (more bytes than expected) — treat as end and wait for next
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// break
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dmx_frame_ready = true;
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receiving = false;
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}
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}
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/* --- USART0 (printf/debug) init & putchar --- */
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void uart0_init(uint32_t baud) {
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// uint16_t ubrr = (uint16_t)((F_CPU / (16UL * baud)) - 1UL);
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// UBRR0H = (uint8_t)(ubrr >> 8);
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// UBRR0L = (uint8_t)ubrr;
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UBRR0L = 8;
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UCSR0B = (1 << TXEN0); // enable transmitter
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UCSR0C = (1 << UCSZ01) | (1 << UCSZ00); // 8 data, 1 stop, no parity
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}
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int uart0_putchar(char c, FILE *stream) {
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if (c == '\n')
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uart0_putchar('\r', stream); // CRLF
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while (!(UCSR0A & (1 << UDRE0)))
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; // wait until buffer empty
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UDR0 = (uint8_t)c;
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return 0;
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}
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/* Create a FILE stream for stdout */
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static FILE uart0_stdout =
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FDEV_SETUP_STREAM(uart0_putchar, NULL, _FDEV_SETUP_WRITE);
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int main(void) {
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// Example CPU freq assumption: 16 MHz. If different, adjust UBRR in
|
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// uart3_init.
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DDRE |= 1 << 4;
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cli();
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uart3_init();
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// Optional: initialize array
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DDRJ |= 1 << 5; // enable rs485 receiver
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uart3_init();
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uart0_init(115200); // debug baud
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// Hook stdout to UART0
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stdout = &uart0_stdout;
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// init DMX buffer
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for (uint16_t i = 1; i <= DMX_CHANNELS; ++i)
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dmx_data[i] = 0;
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sei();
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// Main loop: react to finished frames
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// Example usage
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printf("DMX receiver started\r\n");
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||||
|
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while (1) {
|
||||
if (dmx_frame_ready) {
|
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// Example: use channel 1..512 from dmx_data
|
||||
// Process dmx_data here. This is a single buffer; if processing takes
|
||||
// long, consider double-buffering to avoid race with ISR.
|
||||
// Example debug: print first 8 channels
|
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printf("DMX frame received. Ch1..8: ");
|
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for (uint8_t i = 1; i <= 8; ++i) {
|
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printf("%u ", dmx_data[i]);
|
||||
}
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printf("\r\n");
|
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||||
// After consuming, clear flag
|
||||
dmx_frame_ready = false;
|
||||
}
|
||||
|
||||
// if (dmx_data[1])
|
||||
// PORTE |= 1 << 4;
|
||||
// else
|
||||
// PORTE &= ~(1 << 4);
|
||||
output_dmx_channels_1_24();
|
||||
|
||||
// Other application code...
|
||||
// other app code...
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
// #include <avr/io.h>
|
||||
// #include <util/delay.h>
|
||||
//
|
||||
// int main(void) {
|
||||
// DDRE = 1 << 4;
|
||||
//
|
||||
// while (1) {
|
||||
// PORTE ^= 1 << 4;
|
||||
// _delay_ms(500);
|
||||
// }
|
||||
// }
|
||||
|
||||
Reference in New Issue
Block a user