more or less works
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agsler
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controllino_io.c
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255
controllino_io.c
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#include <avr/io.h>
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#include <stdint.h>
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/* DMX buffer: indexed 1..512 */
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extern volatile uint8_t dmx_data[];
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/* Pin bit definitions (change bit numbers if different on your board) */
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/* PE4, PE5, PG5, PE3, PH3, PH4, PH5, PH6, PB4, PB5, PB6, PB7,
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PL7, PL6, PL5, PL4, PL3, PL2, PL1, PL0, PD4, PD5, PD6, PJ4 */
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/* For each Dn we need to map which port and bit will hold bit0..bit7 of the
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output byte. Here we assume each DMX channel is presented on a contiguous
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8-bit port where possible. Since the pins are all over, we output each DMX
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byte bit-by-bit to 8 dedicated pins: bit 0 -> mapped pin for bit0, ... bit7
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-> mapped pin for bit7. Replace the per-bit port/bit assignments below to
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match your desired wiring. */
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/* Example per-bit mapping for channel outputs (one mapping choice). */
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/* For brevity we map bits 0..7 of each channel to the same physical pin for
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that channel, i.e., output the full byte on 8-bit bus is not possible on
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single scattered pin. Instead we simply write the byte value to the port pins
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that form an 8-bit port where possible. We'll implement writing each
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channel's byte to its single port's low 8 bits when that port contains 8
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consecutive pins; otherwise we write the byte on the low 8 bits of a chosen
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port using the relevant mask. */
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/* Define helper macros for writing masked values */
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static inline void write_masked(volatile uint8_t *port, volatile uint8_t *ddr,
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uint8_t mask, uint8_t value) {
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uint8_t cur = *port & ~mask;
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*port = cur | (value & mask);
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*ddr |= mask; // ensure pins are outputs
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}
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/* Concrete writers for the pins used (mask and port pointers) */
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/* Adjust masks to the actual bit positions used on each port. The following
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masks assume: PB4..PB7 -> bits 4..7 on PORTB (fits for D8..D11) PL0..PL7 ->
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bits 0..7 on PORTL (fits for D12..D19) PH0..PH7 -> bits 0..7 on PORTH (we use
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PH3..PH6 for D4..D7 -> need masking) PD4..PD6 -> bits 4..6 on PORTD
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(D20..D22) PE0..PE7 -> bits 0..7 on PORTE (we use PE3,PE4,PE5 for D0,D1,D3)
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PJ4 -> bit 4 on PORTJ (D23)
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PG5 -> bit 5 on PORTG (D2)
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*/
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/* Write channel values to ports with appropriate masks */
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void output_dmx_channels_1_24(void) {
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/* D0 -> PE4 : map whole byte to bits 0..7 not possible; instead output
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LSB..MSB across 8 pins For simplicity we output the byte value on an 8-bit
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pseudo-bus using multiple ports: Here we implement a pragmatic approach:
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output each channel value on 8 dedicated IO pins defined below. You must
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adapt bit-to-pin assignments to match your wiring. */
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/* Example assignment: use PORTL for D12..D19 (8-bit) */
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/* D12..D19 handled below; for single-pin channels we output LSB on that pin
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(as HIGH/LOW) — if you actually need parallel 8-bit outputs on dedicated
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pins per channel, you'll need 8 pins per channel (192 pins) which is
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unlikely. So this snippet writes each channel's byte value as a PWM-like
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ON/OFF level on a single digital pin using thresholding:
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-> if value >= 128 -> set pin HIGH else LOW. */
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/* Quick implementation: set output pin HIGH if channel value >= 128, else
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LOW. Map each D0..D23 to its port/bit and write accordingly. */
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uint8_t v;
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/* D0: PE4 (bit 4) */
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v = dmx_data[1];
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if (v >= 128)
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PORTE |= (1 << 4);
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else
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PORTE &= ~(1 << 4);
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DDRE |= (1 << 4);
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/* D1: PE5 (bit 5) */
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v = dmx_data[2];
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if (v >= 128)
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PORTE |= (1 << 5);
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else
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PORTE &= ~(1 << 5);
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DDRE |= (1 << 5);
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/* D2: PG5 (bit 5) */
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v = dmx_data[3];
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if (v >= 128)
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PORTG |= (1 << 5);
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else
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PORTG &= ~(1 << 5);
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DDRG |= (1 << 5);
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/* D3: PE3 (bit 3) */
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v = dmx_data[4];
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if (v >= 128)
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PORTE |= (1 << 3);
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else
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PORTE &= ~(1 << 3);
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DDRE |= (1 << 3);
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/* D4: PH3 (bit 3) */
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v = dmx_data[5];
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if (v >= 128)
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PORTH |= (1 << 3);
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else
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PORTH &= ~(1 << 3);
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DDRH |= (1 << 3);
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/* D5: PH4 (bit 4) */
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v = dmx_data[6];
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if (v >= 128)
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PORTH |= (1 << 4);
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else
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PORTH &= ~(1 << 4);
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DDRH |= (1 << 4);
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/* D6: PH5 (bit 5) */
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v = dmx_data[7];
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if (v >= 128)
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PORTH |= (1 << 5);
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else
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PORTH &= ~(1 << 5);
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DDRH |= (1 << 5);
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/* D7: PH6 (bit 6) */
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v = dmx_data[8];
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if (v >= 128)
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PORTH |= (1 << 6);
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else
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PORTH &= ~(1 << 6);
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DDRH |= (1 << 6);
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/* D8: PB4 (bit 4) */
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v = dmx_data[9];
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if (v >= 128)
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PORTB |= (1 << 4);
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else
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PORTB &= ~(1 << 4);
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DDRB |= (1 << 4);
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/* D9: PB5 (bit 5) */
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v = dmx_data[10];
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if (v >= 128)
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PORTB |= (1 << 5);
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else
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PORTB &= ~(1 << 5);
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DDRB |= (1 << 5);
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/* D10: PB6 (bit 6) */
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v = dmx_data[11];
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if (v >= 128)
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PORTB |= (1 << 6);
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else
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PORTB &= ~(1 << 6);
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DDRB |= (1 << 6);
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/* D11: PB7 (bit 7) */
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v = dmx_data[12];
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if (v >= 128)
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PORTB |= (1 << 7);
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else
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PORTB &= ~(1 << 7);
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DDRB |= (1 << 7);
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/* D12: PL7 (bit 7) */
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v = dmx_data[13];
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if (v >= 128)
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PORTL |= (1 << 7);
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else
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PORTL &= ~(1 << 7);
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DDRL |= (1 << 7);
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/* D13: PL6 (bit 6) */
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v = dmx_data[14];
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if (v >= 128)
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PORTL |= (1 << 6);
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else
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PORTL &= ~(1 << 6);
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DDRL |= (1 << 6);
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/* D14: PL5 (bit 5) */
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v = dmx_data[15];
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if (v >= 128)
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PORTL |= (1 << 5);
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else
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PORTL &= ~(1 << 5);
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DDRL |= (1 << 5);
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/* D15: PL4 (bit 4) */
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v = dmx_data[16];
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if (v >= 128)
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PORTL |= (1 << 4);
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else
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PORTL &= ~(1 << 4);
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DDRL |= (1 << 4);
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/* D16: PL3 (bit 3) */
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v = dmx_data[17];
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if (v >= 128)
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PORTL |= (1 << 3);
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else
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PORTL &= ~(1 << 3);
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DDRL |= (1 << 3);
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/* D17: PL2 (bit 2) */
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v = dmx_data[18];
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if (v >= 128)
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PORTL |= (1 << 2);
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else
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PORTL &= ~(1 << 2);
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DDRL |= (1 << 2);
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/* D18: PL1 (bit 1) */
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v = dmx_data[19];
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if (v >= 128)
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PORTL |= (1 << 1);
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else
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PORTL &= ~(1 << 1);
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DDRL |= (1 << 1);
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/* D19: PL0 (bit 0) */
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v = dmx_data[20];
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if (v >= 128)
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PORTL |= (1 << 0);
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else
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PORTL &= ~(1 << 0);
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DDRL |= (1 << 0);
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/* D20: PD4 (bit 4) */
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v = dmx_data[21];
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if (v >= 128)
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PORTD |= (1 << 4);
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else
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PORTD &= ~(1 << 4);
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DDRD |= (1 << 4);
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/* D21: PD5 (bit 5) */
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v = dmx_data[22];
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if (v >= 128)
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PORTD |= (1 << 5);
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else
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PORTD &= ~(1 << 5);
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DDRD |= (1 << 5);
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/* D22: PD6 (bit 6) */
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v = dmx_data[23];
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if (v >= 128)
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PORTD |= (1 << 6);
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else
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PORTD &= ~(1 << 6);
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DDRD |= (1 << 6);
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/* D23: PJ4 (bit 4) */
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v = dmx_data[24];
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if (v >= 128)
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PORTJ |= (1 << 4);
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else
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PORTJ &= ~(1 << 4);
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DDRJ |= (1 << 4);
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}
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