127 lines
3.1 KiB
C
127 lines
3.1 KiB
C
#include <avr/interrupt.h>
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#include <avr/io.h>
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#include <stdbool.h>
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#include <stdint.h>
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#define DMX_CHANNELS 512
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volatile uint8_t dmx_data[DMX_CHANNELS + 1]; // 1..512
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volatile uint16_t dmx_index = 0;
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volatile bool dmx_frame_ready = false;
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volatile bool receiving = false;
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void uart3_init(void) {
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// Set baud rate for 250000 (F_CPU must be set accordingly).
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// Formula UBRR = F_CPU/(16*baud)-1 ; For high speed use U2X - but DMX
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// typically uses normal mode. For F_CPU = 16MHz: UBRR =
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// 16,000,000/(16*250000)-1 = 3 We'll enable UBRR3 with 3 for 16MHz; adjust if
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// F_CPU differs.
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uint16_t ubrr = 3;
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UBRR3H = (uint8_t)(ubrr >> 8);
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UBRR3L = (uint8_t)ubrr;
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// Enable receiver and RX complete interrupt
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UCSR3B = (1 << RXEN3) | (1 << RXCIE3);
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// Set frame format: 8 data, 2 stop bits (USBS3 = 1)
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UCSR3C = (1 << USBS3) | (1 << UCSZ31) | (1 << UCSZ30);
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// Note: parity default is none (UPM bits = 0)
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}
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ISR(USART3_RX_vect) {
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PORTE |= 1 << 4;
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uint8_t status = UCSR3A;
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uint8_t data = UDR3; // reading UDR clears the receive flag
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// If framing error -> likely BREAK (line held low longer than a byte time)
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if (status & (1 << FE3)) {
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// Break detected: start of new DMX packet
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receiving = true;
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dmx_index = 0;
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dmx_frame_ready = false;
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return; // discard this byte (it's break/MAF)
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}
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if (!receiving) {
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// Not currently inside a DMX frame; ignore bytes until we detect break
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return;
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}
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// DMX: first byte after break is START CODE (usually 0); then channel
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// data 1..512
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if (dmx_index == 0) {
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// start code
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// Optionally check for start code == 0, otherwise may discard or handle RDM
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// etc. We'll accept any start code but only store channels.
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dmx_index++; // move to channel 1 next
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return;
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}
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// dmx_index corresponds to channel number
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if (dmx_index <= DMX_CHANNELS) {
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dmx_data[dmx_index] = data;
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dmx_index++;
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if (dmx_index > DMX_CHANNELS) {
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// Received full frame
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dmx_frame_ready = true;
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receiving = false; // wait for next break
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}
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} else {
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// Overflow (more bytes than expected) — treat as end and wait for next
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// break
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dmx_frame_ready = true;
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receiving = false;
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}
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}
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int main(void) {
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// Example CPU freq assumption: 16 MHz. If different, adjust UBRR in
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// uart3_init.
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DDRE |= 1 << 4;
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cli();
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uart3_init();
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// Optional: initialize array
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for (uint16_t i = 1; i <= DMX_CHANNELS; ++i)
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dmx_data[i] = 0;
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sei();
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// Main loop: react to finished frames
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while (1) {
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if (dmx_frame_ready) {
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// Example: use channel 1..512 from dmx_data
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// Process dmx_data here. This is a single buffer; if processing takes
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// long, consider double-buffering to avoid race with ISR.
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// After consuming, clear flag
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dmx_frame_ready = false;
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}
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// if (dmx_data[1])
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// PORTE |= 1 << 4;
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// else
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// PORTE &= ~(1 << 4);
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// Other application code...
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}
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return 0;
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}
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// #include <avr/io.h>
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// #include <util/delay.h>
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//
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// int main(void) {
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// DDRE = 1 << 4;
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//
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// while (1) {
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// PORTE ^= 1 << 4;
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// _delay_ms(500);
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// }
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// }
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