ejung/parafraktor-stm32
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bump freqency to 64MHz (max)

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had problems in cubeMX with that, but now it seems to work
This commit is contained in:
Eggert Jung
2025-05-02 01:56:18 +02:00
parent b85c8fc5f0
commit 096c40d216
3 changed files with 35 additions and 34 deletions
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6
Src/main.c
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@@ -94,7 +94,7 @@ void init_UART1_dma(){
GPIOC->AFR[0] &= GPIO_AFRL_AFSEL5;
GPIOC->AFR[0] |= 1 << GPIO_AFRL_AFSEL5_Pos; // AF1 -> USART1 RX
USART1->BRR = 128; // 32000000÷250000
USART1->BRR = 256; // 64000000÷250000
USART1->CR1 = USART_CR1_RE;
USART1->CR3 |= USART_CR3_EIE; // Interrupt on BREAK (and other errors)
@@ -258,7 +258,7 @@ void SystemClock_Config(void)
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
RCC_OscInitStruct.PLL.PLLN = 8;
RCC_OscInitStruct.PLL.PLLN = 16;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
@@ -275,7 +275,7 @@ void SystemClock_Config(void)
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
{
Error_Handler();
}