ejung/parafraktor-stm32
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dma works

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This commit is contained in:
Eggert Jung
2025-04-28 23:42:51 +02:00
parent 19a85baf33
commit b85c8fc5f0
1 changed files with 25 additions and 7 deletions
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32
Src/main.c
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@@ -100,7 +100,7 @@ void init_UART1_dma(){
USART1->CR3 |= USART_CR3_EIE; // Interrupt on BREAK (and other errors)
USART1->CR3 |= USART_CR3_DMAR; // DMA Receiver mode
DMA1_Channel1->CCR = (0x02 << DMA_CCR_PL_Pos) | DMA_CCR_MINC | DMA_CCR_TCIE;
DMA1_Channel1->CCR = (0x02 << DMA_CCR_PL_Pos) | DMA_CCR_MINC | DMA_CCR_TCIE;
DMA1_Channel1->CMAR = ( uint32_t )&rxBuffer[0];
DMA1_Channel1->CPAR = ( uint32_t )&(USART1->RDR);
@@ -109,7 +109,6 @@ void init_UART1_dma(){
DMAMUX1_Channel0->CCR &= ~( DMAMUX_CxCR_DMAREQ_ID );
DMAMUX1_Channel0->CCR |= ( 50 << DMAMUX_CxCR_DMAREQ_ID_Pos ); // 50 -> USART1 RX
USART1->CR1 |= USART_CR1_UE;
HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
@@ -119,9 +118,25 @@ void init_UART1_dma(){
HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
}
void Reset_DMA(void) {
// Disable the DMA channel
DMA1_Channel1->CCR &= ~DMA_CCR_EN; // Disable DMA Channel 1
// Clear the transfer complete flag
DMA1->IFCR |= DMA_IFCR_CTCIF1; // Clear transfer complete flag for Channel 1
// Reconfigure the DMA
DMA1_Channel1->CMAR = (uint32_t)rxBuffer; // Set memory address to the start of the buffer
DMA1_Channel1->CNDTR = BUFFER_SIZE; // Set number of data items to transfer
// Enable the DMA channel again
DMA1_Channel1->CCR |= DMA_CCR_EN; // Enable DMA Channel 1
}
void USART1_IRQHandler(){
SEGGER_SYSVIEW_RecordEnterISR();
if(USART1->ISR & USART_ISR_RXNE_RXFNE){
//SEGGER_SYSVIEW_PrintfHost("RXNE");
//printf("%x ", USART1->RDR);
rxBuffer[rxBufferPos++] = USART1->RDR;
if(rxBufferPos >= BUFFER_SIZE){
@@ -134,15 +149,19 @@ void USART1_IRQHandler(){
//if(rxBufferPos != 514)
// printf("FE after %d\n",rxBufferPos);
//rxBufferPos = 0;
printf("FE\n");
//DMA1_Channel1->CNDTR = 1;
DMA1_Channel1->CNDTR = 5;
DMA1_Channel1->CCR |= ( DMA_CCR_EN );
SEGGER_SYSVIEW_PrintfHost("FE");
Reset_DMA();
//DMA1_Channel1->CCR &= ~( DMA_CCR_EN );
//DMA1_Channel1->CNDTR = 512;
//DMA1_Channel1->CMAR = ( uint32_t )&rxBuffer[0];
//DMA1_Channel1->CCR |= ( DMA_CCR_EN );
////DMA1_Channel1->CCR |= ( DMA_CCR_EN );
}
if(USART1->ISR & USART_ISR_ORE){
USART1->ICR = USART_ICR_ORECF;
//printf("ORE\n");
//SEGGER_SYSVIEW_PrintfHost("ORE");
}
if(USART1->ISR & USART_ISR_NE){
USART1->ICR = USART_ICR_NECF;
@@ -159,9 +178,8 @@ void DMA1_Channel1_IRQHandler(){
SEGGER_SYSVIEW_RecordEnterISR();
if(DMA1->ISR & DMA_ISR_TCIF1){
DMA1->IFCR = DMA_IFCR_CTCIF1;
DMA1_Channel1->CCR &= ~( DMA_CCR_EN );
DMA1_Channel1->CMAR = ( uint32_t )&rxBuffer[0];
}
SEGGER_SYSVIEW_PrintfHost("DMA");
SEGGER_SYSVIEW_RecordExitISR();
}
/* USER CODE END 0 */