ejung/parafraktor-stm32
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wip on stepper movement

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some bug occurs on reversiong direction when declining in position
This commit is contained in:
Eggert Jung
2025-05-03 01:52:29 +02:00
parent 05a9fafee4
commit 9852548a10
6 changed files with 313 additions and 156 deletions
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169
Src/main.c
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@@ -27,6 +27,9 @@
#include "stm32g0xx_hal_cortex.h"
#include <stdint.h>
#include <stdio.h>
#include "uart_dmx.h"
#include "stepper.h"
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
@@ -59,151 +62,7 @@ static void MX_GPIO_Init(void);
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
#define BUFFER_SIZE 515
uint8_t rxBuffer[BUFFER_SIZE];
uint16_t rxBufferPos = 0;
void init_UART1_it(){
RCC->APBENR2 |= RCC_APBENR2_USART1EN;
RCC->IOPENR |= RCC_IOPENR_GPIOCEN;
GPIOC->MODER &= ~GPIO_MODER_MODE5; // Alternate function mode on RX pin
GPIOC->MODER |= GPIO_MODER_MODE5_1;
GPIOC->AFR[0] &= GPIO_AFRL_AFSEL5;
GPIOC->AFR[0] |= 1 << GPIO_AFRL_AFSEL5_Pos; // AF1 -> USART1 RX
USART1->BRR = 128; // 32000000÷250000
USART1->CR1 = USART_CR1_RE;
USART1->CR3 |= USART_CR3_EIE; // Interrupt on BREAK (and other errors)
USART1->CR1 |= USART_CR1_RXNEIE_RXFNEIE; // RX Interrupt
USART1->CR1 |= USART_CR1_UE;
HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(USART1_IRQn);
}
void init_UART1_dma(){
RCC->IOPENR |= RCC_IOPENR_GPIOCEN;
RCC->APBENR2 |= RCC_APBENR2_USART1EN;
RCC->AHBENR |= RCC_AHBENR_DMA1EN;
GPIOC->MODER &= ~GPIO_MODER_MODE5; // Alternate function mode on RX pin
GPIOC->MODER |= GPIO_MODER_MODE5_1;
GPIOC->AFR[0] &= GPIO_AFRL_AFSEL5;
GPIOC->AFR[0] |= 1 << GPIO_AFRL_AFSEL5_Pos; // AF1 -> USART1 RX
USART1->BRR = 256; // 64000000÷250000
USART1->CR1 = USART_CR1_RE;
USART1->CR3 |= USART_CR3_EIE; // Interrupt on BREAK (and other errors)
USART1->CR3 |= USART_CR3_DMAR; // DMA Receiver mode
DMA1_Channel1->CCR = (0x02 << DMA_CCR_PL_Pos) | DMA_CCR_MINC | DMA_CCR_TCIE;
DMA1_Channel1->CMAR = ( uint32_t )&rxBuffer[0];
DMA1_Channel1->CPAR = ( uint32_t )&(USART1->RDR);
DMA1_Channel1->CNDTR = 5;
DMAMUX1_Channel0->CCR &= ~( DMAMUX_CxCR_DMAREQ_ID );
DMAMUX1_Channel0->CCR |= ( 50 << DMAMUX_CxCR_DMAREQ_ID_Pos ); // 50 -> USART1 RX
USART1->CR1 |= USART_CR1_UE;
HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(USART1_IRQn);
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
}
void Reset_DMA(void) {
// Disable the DMA channel
DMA1_Channel1->CCR &= ~DMA_CCR_EN; // Disable DMA Channel 1
// Clear the transfer complete flag
DMA1->IFCR |= DMA_IFCR_CTCIF1; // Clear transfer complete flag for Channel 1
// Reconfigure the DMA
DMA1_Channel1->CMAR = (uint32_t)rxBuffer; // Set memory address to the start of the buffer
DMA1_Channel1->CNDTR = BUFFER_SIZE; // Set number of data items to transfer
// Enable the DMA channel again
DMA1_Channel1->CCR |= DMA_CCR_EN; // Enable DMA Channel 1
}
void USART1_IRQHandler(){
SEGGER_SYSVIEW_RecordEnterISR();
if(USART1->ISR & USART_ISR_RXNE_RXFNE){
//SEGGER_SYSVIEW_PrintfHost("RXNE");
//printf("%x ", USART1->RDR);
rxBuffer[rxBufferPos++] = USART1->RDR;
if(rxBufferPos >= BUFFER_SIZE){
rxBufferPos = 0;
}
}
if(USART1->ISR & USART_ISR_FE){
//TODO read rx==0
USART1->ICR = USART_ICR_FECF;
//if(rxBufferPos != 514)
// printf("FE after %d\n",rxBufferPos);
//rxBufferPos = 0;
//DMA1_Channel1->CNDTR = 1;
SEGGER_SYSVIEW_PrintfHost("FE");
Reset_DMA();
//DMA1_Channel1->CCR &= ~( DMA_CCR_EN );
//DMA1_Channel1->CNDTR = 512;
//DMA1_Channel1->CMAR = ( uint32_t )&rxBuffer[0];
//DMA1_Channel1->CCR |= ( DMA_CCR_EN );
////DMA1_Channel1->CCR |= ( DMA_CCR_EN );
}
if(USART1->ISR & USART_ISR_ORE){
USART1->ICR = USART_ICR_ORECF;
//printf("ORE\n");
//SEGGER_SYSVIEW_PrintfHost("ORE");
}
if(USART1->ISR & USART_ISR_NE){
USART1->ICR = USART_ICR_NECF;
printf("NE\n");
}
if(USART1->ISR & USART_ISR_UDR){
USART1->ICR = USART_ICR_UDRCF;
printf("UDR\n");
}
SEGGER_SYSVIEW_RecordExitISR();
}
void DMA1_Channel1_IRQHandler(){
SEGGER_SYSVIEW_RecordEnterISR();
if(DMA1->ISR & DMA_ISR_TCIF1){
DMA1->IFCR = DMA_IFCR_CTCIF1;
}
SEGGER_SYSVIEW_PrintfHost("DMA");
SEGGER_SYSVIEW_RecordExitISR();
}
void init_stepper(){
RCC->IOPENR |= RCC_IOPENR_GPIOBEN;
RCC->IOPENR |= RCC_IOPENR_GPIOCEN;
RCC->IOPENR |= RCC_IOPENR_GPIOEEN;
// Set to output (00: Input, 01: Output, 10: Alternate function, 11: Analog)
// PB4 Direction
GPIOB->MODER &= ~(0x3 << (4 * 2)); // Clear mode bits for PB4
GPIOB->MODER |= (0x1 << (4 * 2)); // Set mode to output for PB4
// PC11 Enable
GPIOC->MODER &= ~(0x3 << (11 * 2)); // Clear mode bits for PC11
GPIOC->MODER |= (0x1 << (11 * 2)); // Set mode to output for PC11
// PE2 Step
GPIOE->MODER &= ~(0x3 << (2 * 2)); // Clear mode bits for PE2
GPIOE->MODER |= (0x1 << (2 * 2)); // Set mode to output for PE2
GPIOC->BSRR |= GPIO_BSRR_BS11;
}
/* USER CODE END 0 */
/**
@@ -239,24 +98,24 @@ int main(void)
MX_GPIO_Init();
/* USER CODE BEGIN 2 */
init_UART1_dma();
init_stepper();
stepper_gpio_init();
Timer1_Init();
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
//HAL_UART_Receive_DMA(&huart1, rxBuffer, BUFFER_SIZE);
uint16_t cnt = 0;
//uint16_t cnt = 0;
while (1)
{
printf("buf: ");
for(uint16_t i=0; i<10; i++)
printf("0x%02X ", rxBuffer[i]);
printf("\n");
//printf("buf: ");
//for(uint16_t i=0; i<10; i++)
// printf("0x%02X ", rxBuffer[i]);
//printf("\n");
SEGGER_SYSVIEW_OnIdle();
if(cnt++ >= 260-rxBuffer[1]){
cnt = 0;
GPIOE->ODR ^= GPIO_ODR_OD2;
}
//if(cnt++ >= 256-rxBuffer[1]){
// cnt = 0;
// GPIOE->ODR ^= GPIO_ODR_OD2;
//}
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */