wip on stepper movement
some bug occurs on reversiong direction when declining in positionfixturemapping
parent
05a9fafee4
commit
9852548a10
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#include "stm32g0b1xx.h"
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typedef struct {
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GPIO_TypeDef* en_port;
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uint8_t en_pin;
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GPIO_TypeDef* dir_port;
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uint8_t dir_pin;
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GPIO_TypeDef* step_port;
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uint8_t step_pin;
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GPIO_TypeDef* home_port;
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uint8_t home_pin;
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uint8_t homed:1;
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uint8_t moving:1;
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int16_t pos;
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int16_t speed;
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int16_t ramp_to_speed;
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uint32_t next_step;
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} stepper_T;
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void Timer1_Init(void);
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void stepper_gpio_init();
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void do_steps();
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#include "stm32g0b1xx.h"
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#define BUFFER_SIZE 515
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extern uint8_t rxBuffer[BUFFER_SIZE];
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extern uint16_t rxBufferPos;
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void init_UART1_it();
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void init_UART1_dma();
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#include "stm32g0b1xx.h"
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#include "stepper.h"
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include "SEGGER_SYSVIEW.h"
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#include "uart_dmx.h"
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stepper_T steppers[] = {
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{.en_port=GPIOC, .en_pin=11, .dir_port=GPIOB, .dir_pin=4, .step_port=GPIOE, .step_pin=2, .home_port=GPIOF, .home_pin=3}
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};
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void set_pins(stepper_T* stp){
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// Set direction (00: Input, 01: Output, 10: Alternate function, 11: Analog)
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// enable
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stp->en_port->MODER &= ~(0x3 << (stp->en_pin * 2));
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stp->en_port->MODER |= (0x1 << (stp->en_pin * 2));
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// direction
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stp->dir_port->MODER &= ~(0x3 << (stp->dir_pin * 2));
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stp->dir_port->MODER |= (0x1 << (stp->dir_pin * 2));
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// step
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stp->step_port->MODER &= ~(0x3 << (stp->step_pin * 2));
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stp->step_port->MODER |= (0x1 << (stp->step_pin * 2));
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// home switch
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stp->home_port->MODER &= ~(0x3 << (stp->home_pin * 2));
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// make shure stepper is enabled (active low)
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stp->en_port->BSRR |= (0x1 << (stp->en_pin + 16));
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}
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void stepper_gpio_init(){
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RCC->IOPENR |= RCC_IOPENR_GPIOBEN;
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RCC->IOPENR |= RCC_IOPENR_GPIOCEN;
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RCC->IOPENR |= RCC_IOPENR_GPIOEEN;
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RCC->IOPENR |= RCC_IOPENR_GPIOFEN;
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for(uint8_t i=0; i<(sizeof(steppers)/sizeof(stepper_T)); i++){
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set_pins(&steppers[i]);
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}
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}
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void Timer1_Init(void) {
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// Step 1: Enable the clock for Timer 1
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RCC->APBENR2 |= RCC_APBENR2_TIM1EN; // Enable TIM1 clock
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// Step 2: Configure Timer 1
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TIM1->PSC = 64;
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TIM1->ARR = 100;
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TIM1->DIER |= TIM_DIER_UIE; // Enable update interrupt
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// Step 3: Enable Timer 1
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TIM1->CR1 |= TIM_CR1_CEN; // Enable the timer
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// Step 4: Enable the interrupt in NVIC
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NVIC_EnableIRQ(TIM1_BRK_UP_TRG_COM_IRQn); // Enable Timer 1 interrupt in NVIC
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}
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// Timer 1 Update Interrupt Handler
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void TIM1_BRK_UP_TRG_COM_IRQHandler(void) {
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SEGGER_SYSVIEW_RecordEnterISR();
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if (TIM1->SR & TIM_SR_UIF) { // Check if the update interrupt flag is set
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TIM1->SR &= ~TIM_SR_UIF; // Clear the update interrupt flag
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//SEGGER_SYSVIEW_PrintfHost("do step");
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do_steps();
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}
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SEGGER_SYSVIEW_RecordExitISR();
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}
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void do_steps(){
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static uint32_t timer = 0;
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timer++;
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for(uint8_t i=0; i<(sizeof(steppers)/sizeof(stepper_T)); i++){
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if(steppers[i].ramp_to_speed != 0 && steppers[i].next_step == timer){
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/* ramp speed */
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if(steppers[i].speed < steppers[i].ramp_to_speed)
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steppers[i].speed++;
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if(steppers[i].speed > steppers[i].ramp_to_speed)
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steppers[i].speed--;
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/* limit max speed */
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if(steppers[i].speed >= 100)
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steppers[i].speed=100;
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if(steppers[i].speed <= -100)
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steppers[i].speed=-100;
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/* get direction from sign */
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if(steppers[i].speed>0)
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steppers[i].dir_port->BSRR |= 1 << steppers[i].dir_pin;
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if(steppers[i].speed<0)
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steppers[i].dir_port->BSRR |= 1 << (steppers[i].dir_pin + 16);
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/* calculate next step time */
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steppers[i].next_step = timer + (1000/abs(steppers[i].speed)); // should be safe for 1 overflow
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/* step and count position */
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steppers[i].step_port->ODR ^= 1 << steppers[i].step_pin;
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if(steppers[i].speed>0)
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steppers[i].pos++;
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if(steppers[i].speed<0)
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steppers[i].pos--;
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printf("pos %d\tspeed %d\n", steppers[i].pos, steppers[i].speed);
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}
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if(steppers[i].homed){
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int16_t old_ramp_to_speed = steppers[i].ramp_to_speed;
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steppers[i].ramp_to_speed = rxBuffer[1] - steppers[i].pos;
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if(steppers[i].ramp_to_speed != 0 && old_ramp_to_speed == 0)
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steppers[i].next_step = timer+1;
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}
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else{
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if(~(steppers[i].home_port->IDR) & (1 << steppers[i].home_pin)){
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steppers[i].pos = 0;
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steppers[i].homed = 1;
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steppers[i].speed = 0;
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steppers[i].ramp_to_speed = 0;
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printf("homed %d\n", i);
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}
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else{
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if(steppers[i].ramp_to_speed == 0){
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steppers[i].ramp_to_speed=10;
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steppers[i].next_step = timer+1;
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}
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}
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}
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}
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}
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@ -0,0 +1,129 @@
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#include "uart_dmx.h"
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#include "SEGGER_SYSVIEW.h"
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#include "stdio.h"
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#include "stm32g0xx_hal.h"
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#include "system_stm32g0xx.h"
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uint8_t rxBuffer[BUFFER_SIZE];
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uint16_t rxBufferPos = 0;
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void init_UART1_it(){
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RCC->APBENR2 |= RCC_APBENR2_USART1EN;
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RCC->IOPENR |= RCC_IOPENR_GPIOCEN;
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GPIOC->MODER &= ~GPIO_MODER_MODE5; // Alternate function mode on RX pin
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GPIOC->MODER |= GPIO_MODER_MODE5_1;
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GPIOC->AFR[0] &= GPIO_AFRL_AFSEL5;
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GPIOC->AFR[0] |= 1 << GPIO_AFRL_AFSEL5_Pos; // AF1 -> USART1 RX
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USART1->BRR = 128; // 32000000÷250000
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USART1->CR1 = USART_CR1_RE;
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USART1->CR3 |= USART_CR3_EIE; // Interrupt on BREAK (and other errors)
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USART1->CR1 |= USART_CR1_RXNEIE_RXFNEIE; // RX Interrupt
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USART1->CR1 |= USART_CR1_UE;
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HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
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HAL_NVIC_EnableIRQ(USART1_IRQn);
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}
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void init_UART1_dma(){
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RCC->IOPENR |= RCC_IOPENR_GPIOCEN;
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RCC->APBENR2 |= RCC_APBENR2_USART1EN;
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RCC->AHBENR |= RCC_AHBENR_DMA1EN;
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GPIOC->MODER &= ~GPIO_MODER_MODE5; // Alternate function mode on RX pin
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GPIOC->MODER |= GPIO_MODER_MODE5_1;
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GPIOC->AFR[0] &= GPIO_AFRL_AFSEL5;
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GPIOC->AFR[0] |= 1 << GPIO_AFRL_AFSEL5_Pos; // AF1 -> USART1 RX
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USART1->BRR = SystemCoreClock / 250000; // 64000000÷250000
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USART1->CR1 = USART_CR1_RE;
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USART1->CR3 |= USART_CR3_EIE; // Interrupt on BREAK (and other errors)
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USART1->CR3 |= USART_CR3_DMAR; // DMA Receiver mode
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DMA1_Channel1->CCR = (0x02 << DMA_CCR_PL_Pos) | DMA_CCR_MINC | DMA_CCR_TCIE;
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DMA1_Channel1->CMAR = ( uint32_t )&rxBuffer[0];
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DMA1_Channel1->CPAR = ( uint32_t )&(USART1->RDR);
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DMA1_Channel1->CNDTR = 5;
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DMAMUX1_Channel0->CCR &= ~( DMAMUX_CxCR_DMAREQ_ID );
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DMAMUX1_Channel0->CCR |= ( 50 << DMAMUX_CxCR_DMAREQ_ID_Pos ); // 50 -> USART1 RX
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USART1->CR1 |= USART_CR1_UE;
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HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
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HAL_NVIC_EnableIRQ(USART1_IRQn);
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HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
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HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
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}
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void Reset_DMA(void) {
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// Disable the DMA channel
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DMA1_Channel1->CCR &= ~DMA_CCR_EN; // Disable DMA Channel 1
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// Clear the transfer complete flag
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DMA1->IFCR |= DMA_IFCR_CTCIF1; // Clear transfer complete flag for Channel 1
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// Reconfigure the DMA
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DMA1_Channel1->CMAR = (uint32_t)rxBuffer; // Set memory address to the start of the buffer
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DMA1_Channel1->CNDTR = BUFFER_SIZE; // Set number of data items to transfer
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// Enable the DMA channel again
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DMA1_Channel1->CCR |= DMA_CCR_EN; // Enable DMA Channel 1
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}
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void USART1_IRQHandler(){
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SEGGER_SYSVIEW_RecordEnterISR();
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if(USART1->ISR & USART_ISR_RXNE_RXFNE){
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//SEGGER_SYSVIEW_PrintfHost("RXNE");
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//printf("%x ", USART1->RDR);
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rxBuffer[rxBufferPos++] = USART1->RDR;
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if(rxBufferPos >= BUFFER_SIZE){
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rxBufferPos = 0;
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}
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}
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if(USART1->ISR & USART_ISR_FE){
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//TODO read rx==0
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USART1->ICR = USART_ICR_FECF;
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//if(rxBufferPos != 514)
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// printf("FE after %d\n",rxBufferPos);
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//rxBufferPos = 0;
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//DMA1_Channel1->CNDTR = 1;
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SEGGER_SYSVIEW_PrintfHost("FE");
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Reset_DMA();
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//DMA1_Channel1->CCR &= ~( DMA_CCR_EN );
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//DMA1_Channel1->CNDTR = 512;
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//DMA1_Channel1->CMAR = ( uint32_t )&rxBuffer[0];
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//DMA1_Channel1->CCR |= ( DMA_CCR_EN );
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////DMA1_Channel1->CCR |= ( DMA_CCR_EN );
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}
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if(USART1->ISR & USART_ISR_ORE){
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USART1->ICR = USART_ICR_ORECF;
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//printf("ORE\n");
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//SEGGER_SYSVIEW_PrintfHost("ORE");
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}
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if(USART1->ISR & USART_ISR_NE){
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USART1->ICR = USART_ICR_NECF;
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printf("NE\n");
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}
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if(USART1->ISR & USART_ISR_UDR){
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USART1->ICR = USART_ICR_UDRCF;
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printf("UDR\n");
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}
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SEGGER_SYSVIEW_RecordExitISR();
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}
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void DMA1_Channel1_IRQHandler(){
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SEGGER_SYSVIEW_RecordEnterISR();
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if(DMA1->ISR & DMA_ISR_TCIF1){
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DMA1->IFCR = DMA_IFCR_CTCIF1;
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}
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SEGGER_SYSVIEW_PrintfHost("DMA");
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SEGGER_SYSVIEW_RecordExitISR();
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}
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