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Kai-Bjoern
392
src/Modules/MMU/mmu.c
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392
src/Modules/MMU/mmu.c
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/*
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****************************************************************************************************
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*
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* uC/OS-MMU
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*
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* (c) Copyright 2012, Micrium, FL
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* All rights reserved.
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*
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* All rights reserved. Protected by international copyright laws.
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* Knowledge of the source code may not be used to write a similar
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* product. This file may only be used in accordance with a license
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* and should not be redistributed in any way.
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*
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*
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* Version : 3.1.2pp-35237
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* File : MMU.c (#1)
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* Programmer(s) : EO
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****************************************************************************************************
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*/
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/*!
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****************************************************************************************************
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* \defgroup PAR_CPU_MMU Target Specific MMU Implementation
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* \ingroup PAR_CORE
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*
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*
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* The memory management unit (MMU) for the ...
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*
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****************************************************************************************************
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*/
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/*
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****************************************************************************************************
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* INCLUDES
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****************************************************************************************************
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*/
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#include "mmu.h"
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#include "xpseudo_asm.h"
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#include "xil_cache.h"
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#include "lib_mem.h"
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#include "mmu_cfg.h"
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/*
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****************************************************************************************************
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* GOBAL DATA
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****************************************************************************************************
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*/
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extern INT32U MMUTable;
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/*
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****************************************************************************************************
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* PRIVATE FUNCTION PROTOTYPES
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****************************************************************************************************
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*/
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static MMU_ERR_T MMUTblAdd (PAR_MEM_REGION_REF_T mem, INT32U * pMMUTable);
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static MMU_ERR_T MMUTblAdd1M (PAR_MEM_REGION_REF_T mem, INT32U off, INT32U * pMMUTable);
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static void FTTSet (INT32U va, INT32U descr, INT32U * pMMUTable);
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static INT32U FTTGet (INT32U va, INT32U * pMMUTable);
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static INT32U FTTDescr (PAR_MEM_REGION_REF_T mem, INT32U offset, INT32U type, INT32U tbl);
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static void MMUEnable (INT32U * pMMUTable);
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static void MMUSwitchContext (INT32U id);
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/*
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****************************************************************************************************
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* FUNCTIONS
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****************************************************************************************************
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*/
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/*------------------------------------------------------------------------------------------------*/
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/*!
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* \brief INIT THE MMU
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*
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* \ingroup PAR_CPU_MMU
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*
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* This function initialize the target specific MMU
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*
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* \note The integrator must supply the contents of the PARErrLogging() function to handle
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* possible error conditions.
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*/
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/*------------------------------------------------------------------------------------------------*/
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MMU_ERR_T MMUInit (void)
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{
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INT32U n; /* Local: loop counter */
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MMU_ERR_T err = MMU_ERR_NONE;
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Mem_Clr(&MMUTable,FTT_SIZE * sizeof(CPU_WORD_SIZE_32));
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for(n = 0; n < sizeof(PARMemTbl_Core)/sizeof(PAR_MEM_REGION_T); n++){
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err = MMUTblAdd((PAR_MEM_REGION_REF_T)&PARMemTbl_Core[n], &MMUTable);
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if(err != MMU_ERR_NONE)
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return err;
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}
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MMUEnable(&MMUTable); /* Enable the MMU */
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return MMU_ERR_NONE;
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}
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/*
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****************************************************************************************************
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* LOCAL FUNCTIONS
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****************************************************************************************************
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*/
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/*------------------------------------------------------------------------------------------------*/
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/*!
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* \brief MMU TABLE CONSTRUCTION
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*
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* \ingroup PAR_CPU_MMU
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*
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* This function constructs the needed table entries for a single user defined memory
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* region with the following rules:
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*
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* - build user memory size with blocks of 4K, 64K and 1M portions
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*
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* - ensure that each block is aligned at size (4K Block is aligned at 4K boundary, etc.)
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*
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* \param mem Reference to memory region
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*
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* \note Memory portions below 1KB will be ignored, because the MMU granularity starts with 1kB
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*/
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/*------------------------------------------------------------------------------------------------*/
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static MMU_ERR_T MMUTblAdd(const PAR_MEM_REGION_REF_T mem, INT32U * pMMUTable)
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{
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INT32U vaddr; /* Local: virtual address */
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INT32U off; /* Local: offset in memory region */
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INT32U size; /* Local: remaining size of memory region */
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MMU_ERR_T err = MMU_ERR_NONE;
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/*------------------------------------------*/
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vaddr = mem->VA_Start; /* set virtual memory address */
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size = mem->Size; /* set size to memory region size */
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off = 0; /* set memory region offset to 0 */
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if ((vaddr & (MMU_SIZE_1MB - 1)) != 0) { /* see, if VA is not aligned at 4k */
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return MMU_ERR_ALIGN;
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}
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if ((size % MMU_SIZE_1MB) != 0) { /* see, if size is not multiple of 4k */
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return MMU_ERR_SIZE;
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}
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while(size >= MMU_SIZE_1MB) { /* create section for memory region */
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err = MMUTblAdd1M(mem, off, pMMUTable); /* add a 1M section */
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if(err != MMU_ERR_NONE)
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return err;
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vaddr += MMU_SIZE_1MB; /* update virtual address and */
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off += MMU_SIZE_1MB; /* offset and */
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size -= MMU_SIZE_1MB; /* remaining bytes in memory region */
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}
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return MMU_ERR_NONE;
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}
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/*------------------------------------------------------------------------------------------------*/
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/*!
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* \brief INSERT 1M SECTION IN MMU TABLE
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*
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* \ingroup PAR_CPU_MMU
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*
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* This function constructs the needed table entries for a single 1M memory block.
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*
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* \param mem Reference to memory region
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*
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* \param off Offset within the referenced memory region
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*/
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/*------------------------------------------------------------------------------------------------*/
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static MMU_ERR_T MMUTblAdd1M(PAR_MEM_REGION_REF_T mem, INT32U off, INT32U * pMMUTable)
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{
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INT32U vaddr; /* Local: virtual address */
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INT32U descr; /* Local: translation table descriptor */
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INT32U type; /* Local: descriptor type information */
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/*------------------------------------------*/
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vaddr = mem->VA_Start + off; /* calculate virtual address */
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type = FTTGet(vaddr, pMMUTable) & FTT_TYPE; /* get descriptor type */
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if (type != FTT_TYPE_FLT) { /* see, if section is already in use */
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return MMU_ERR_ENTRY_IN_USE;
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}
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descr = FTTDescr(mem, off, FTT_TYPE_SEC, 0); /* construct first level section descr. */
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FTTSet(vaddr, descr, pMMUTable); /* set section for virtual address */
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return MMU_ERR_NONE;
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}
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/*------------------------------------------------------------------------------------------------*/
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/*!
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* \brief SET FIRST LEVEL TRANSLATION TABLE DESCRIPTOR
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*
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* \ingroup PAR_CPU_MMU
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*
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* This function sets the given descriptor in the first level translation table
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* which corresponds to the given virtual address.
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*
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* \param va Virtual Address
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*
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* \param descr First level descriptor
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*/
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/*------------------------------------------------------------------------------------------------*/
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static void FTTSet(INT32U va, INT32U descr, INT32U * pMMUTable)
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{
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volatile INT32U *tbl; /* Local: ptr to first level table entry */
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INT32U tbl_idx; /* Local: first level table index */
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/*------------------------------------------*/
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tbl_idx = (va >> 20) & 0x00000FFF; /* get table index out of virtual address */
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tbl = pMMUTable + tbl_idx; /* set first level table base address */
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/*------------------------------------------*/
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*tbl = descr; /* set descriptor in first level table */
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dsb();
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isb();
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}
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/*------------------------------------------------------------------------------------------------*/
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/*!
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* \brief GET FIRST LEVEL TRANSLATION TABLE DESCRIPTOR
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*
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* \ingroup PAR_CPU_MMU
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*
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* This function returns the first level translation table descriptor of the given
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* virtual address.
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*
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* \param va Virtual Address
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*
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* \return The current active descriptor is returned.
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*/
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/*------------------------------------------------------------------------------------------------*/
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static INT32U FTTGet(INT32U va, INT32U * pMMUTable)
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{
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volatile INT32U *tbl; /* Local: ptr to first level table entry */
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INT32U tbl_idx; /* Local: first level table index */
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/*------------------------------------------*/
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tbl_idx = (va >> 20) & 0x00000FFF; /* get table index out of virtual address */
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tbl = pMMUTable + tbl_idx; /* set first level table base address */
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/*------------------------------------------*/
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return (*tbl); /* get descriptor in first level table */
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}
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/*------------------------------------------------------------------------------------------------*/
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/*!
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* \brief CONSTRUCT FIRST LEVEL TRANSLATION TABLE DESCRIPTOR
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*
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* \ingroup PAR_CPU_MMU
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*
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* This function constructs the first level translation table descriptor of the given
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* type for the offset within the memory region.
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*
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* \param mem Reference to memory region
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*
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* \param offset Offset within the referenced memory region
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*
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* \param type Type information (section / coarse page / fine page / fault)
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*
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* \param base Base address of page table
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*
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* \return For the types FTT_TYPE_SEC, FTT_TYPE_CPT and FTT_TYPE_FPT, the
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* corresponding table descriptor is returned. For any other type, the return value is
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* the table descriptor for FTT_TYPE_FLT.
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*
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* \see FTT_TYPE_FLT, FTT_TYPE_CPT, FTT_TYPE_SEC, FTT_TYPE_FPT
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*/
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/*------------------------------------------------------------------------------------------------*/
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static INT32U FTTDescr(PAR_MEM_REGION_REF_T mem, INT32U offset, INT32U type, INT32U base)
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{
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INT32U result = 0; /* Local: function result */
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INT32U pa; /* Local: physical address */
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switch(type){
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case FTT_TYPE_SEC:
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pa = mem->PA_Start + offset; /* yes: calculate physical address */
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result = FTT_TYPE_SEC | /* set descriptor type to section */
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((mem->HID & PAR_HID_CB_MASK) << 2u) | /* cachable & bufferable flag */
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((mem->HID & PAR_HID_F_XN) >> 6u) | /* Execute-Never Flag */
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((PAR_DOMAIN_MASTER) << 5) | /* owner = domain */
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((mem->AP & 0x3) << 10u) | /* access permissions AP0 and AP1 */
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((mem->AP & 0x4) << 13u) | /* access permissions AP2 */
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((mem->HID & PAR_HID_TEX_MASK) << 10u) | /* TEX attributes */
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((mem->HID & PAR_HID_F_S) << 8u) | /* shareable-flag */
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((mem->HID & PAR_HID_F_NG) << 8u) | /* Non-Global-Flag */
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((mem->HID & PAR_HID_F_NS) << 8u) | /* non-secure bit */
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(pa & 0xFFF00000); /* bits[31:20] of physical address */
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break;
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case FTT_TYPE_PT:
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case FTT_TYPE_FLT:
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case FTT_TYPE_RES:
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default:
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break;
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}
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return result;
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}
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/*------------------------------------------------------------------------------------------------*/
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/*!
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* \brief ENABLE MMU
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*
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* \ingroup PAR_CPU_MMU
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*
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* This function enables the MMU.
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*
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* \note The first level translation table and the page tables must be initialized before
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* calling this function.
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*/
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/*------------------------------------------------------------------------------------------------*/
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static void MMUEnable(INT32U * pMMUTable)
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{
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INT32U ctrl; /* Local: control register */
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//Invalidate data and instruction cache
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Xil_DCacheDisable();
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__set_mmu_table(((INT32U)pMMUTable & 0xFFFFC000) | PAR_TTBR0_FLAGS); /* Set first level transl. table base addr. */
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__set_domain_control(0x55555555u); /* set all domains to client */
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//eo verwenden noch PD1 = 1 für tlb miss in TTBR1 wird zu translation fault.
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__set_asid(0 & 0xFF);
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__set_mmu_control(0x00000000); /* Set TTBCR to 0 -> Use TTBR0 and 14Bit alignment */
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__clr_mmu_fault();
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__dsb();
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__invalidate_tlb();
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__invalidate_branchpred();
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__dsb();
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__isb();
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ctrl = __get_sys_control(); /* get current control register */
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ctrl |= MMU_SCTLR_FLAGS; /* set I,C,S and M to enable MMU */
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__set_sys_control(ctrl); /* write new control register */
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/*------------------------------------------*/
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__no_operation(); /* perform 2 flat fetches */
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__no_operation();
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#if (UCOS_AMP_MASTER == DEF_ENABLED)
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// /* Enable L2 Cache */
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// This is a "mandatory" step, don't now why, see Zynq Reference manual
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*((CPU_INT32U*)0xF8000A1C) = 0x020202;
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Xil_L2CacheEnable();
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/* set L2 Aux register */
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// CPU_INT32U dat = *((CPU_INT32U*)0xF8F02104);
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// dat = 0x72760000;
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// *((CPU_INT32U*)0xF8F02104) = dat;
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// // /* Set all latencies of tag-ram to 2 */
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// // *((CPU_INT32U*)0xF8F02108) = 0x00000111;
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// // /* set data ram write and setup latencies to 2, data ram read to 3 */
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// // *((CPU_INT32U*)0xF8F0210C) = 0x00000121;
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// // /* set prefetch conrtol register */
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// // *((CPU_INT32U*)0xF8F02F60) = 0x30000000;
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// /* enable L2 Cache */
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// *((CPU_INT32U*)0xF8F02100) = 0x1;
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#endif
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CPU_INT32U actlr = __get_actlr();
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actlr &= ~(0x00000040);
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__set_actlr(actlr);
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/*--- MMU/address translation is enabled ---*/
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}
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/*------------------------------------------------------------------------------------------------*/
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/*!
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* \brief Switch Address Space
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*
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* \ingroup PAR_CPU_MMU
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*
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* This function switches the address space and manipulates the virt->phys translation.
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*
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* \param id Partition ID
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*/
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/*------------------------------------------------------------------------------------------------*/
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static void MMUSwitchContext(INT32U id)
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{
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CPU_INT32U cpu_sr = 0;
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/*------------------------------------------*/
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OS_ENTER_CRITICAL(); /* Enter critical section */
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//We don't need to flush caches, when for all shared memory regions the L1 cache policy is correct write through or disabled
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// __flush_caches(); /* Flush caches */
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// MMU_DCacheClean();
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//We don't need to invalidate the tlb, beacuase we have the ASID value corresponding to a partition
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// __invalidate_tlb(); /* Invalidate TLB */
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__dsb();
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__set_asid(id & 0xFF);
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__set_mmu_table(((INT32U)MMUTable & 0xFFFFC000) | PAR_TTBR0_FLAGS); /* Set first level transl. table base addr. */
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__dsb();
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__isb();
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OS_EXIT_CRITICAL(); /* Exit critical section */
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/*------------------------------------------*/
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}
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