Squashed all commits

.gitignore

@@ -0,0 +1,24 @@
+out/
+*.o
+*.history*
+*.indexes*
+.metadata
+*.bin
+*.hex
+*.d
+*.map
+*.lst
+.cproject
+.project
+.settings
+*.log
+*~
+*.expand
+
+#Latex Krams
+*.aux
+*.log
+*.aux
+*.out
+*.pdf
+*.toc

Debug/ps7/Aufgabe1/windowSetting.cmm

@@ -0,0 +1,43 @@
+// T3210000 Wed Sep 27 07:34:53 2017
+
+ B::
+ 
+ TOOLBAR ON
+ STATUSBAR ON
+ FramePOS ,,,,Maximized
+ WinPAGE.RESet
+ 
+ WinPAGE.Create P000
+ WinCLEAR
+  
+ WinPOS 0% 0% 50% 78% ,,, W000
+ ;WinTABS 10. 10. 25. 62.
+ wm.List.auto
+ 
+ WinPOS 50% 0% 30% 28% ,,, W001
+ ;WinTABS 13. 0. 0. 0. 0. 0. 0.
+ wm.Break.List
+ 
+ WinPOS 50% 30% 30% 70% ,,, W002
+ wm.Var.Watch %Hex %Decimal
+ 
+ VAR.ADDWATCH OSPrioCur
+ 
+ WinPOS 80% 0% 20% 50% ,,, W003
+ wm.Register /SPOTLIGHT 
+ 
+ WinPOS 0% 80% 50% 20% ,,, W004
+ wm.Symbol.browse \\*\*\*
+ ;WinPAN 0. 239. 
+ 
+ ;WinPOS 50% 50% 30% 50% ,,, W005
+ ;wm.Perf.ListFunc
+ 
+ WinPos 80% 50% 20% 50% ,,, W006
+ wm.Frame /Locals
+ 
+
+ 
+ WinPAGE.select P000
+ 
+ ENDDO

Debug/ps7/Aufgabe1/zc706_onchip_trace.cmm

@@ -0,0 +1,78 @@
+LOCAL &ppd
+&ppd=OS.PPD()
+&tmpDir=OS.PTD()
+
+WinCLEAR
+
+; --------------------------------------------------------------------------------
+; common SYStem settings
+PRINT   "Assigning Cores"
+
+CD &ppd
+RESet
+System.RESet
+SYStem.CPU ZYNQ-7000
+SYStem.CONFIG CORE 1. 1.
+SYStem.CONFIG SLAVE OFF
+CORE.ASSIGN 1.
+
+; set DaisyChaining Parameters of the board
+; check e.g. SYStem.DETECT.ShowCHAIN
+PRINT   "Setting up DaisyChain Parameters"
+SYStem.CONFIG DAPIRPRE  6.
+SYStem.CONFIG DAPIRPOST 0.
+SYStem.CONFIG DAPDRPRE  1.
+SYStem.CONFIG DAPDRPOST 0.
+
+; trigger a soft-reset using the AHB Bus -> we loose the connection
+PRINT   "Trigger Soft-Reset"
+SYStem.Mode.Prepare
+ON ERROR CONTinue
+Data.Set EAHB:0xF8000008 %Long 0xDF0D
+Data.Set EAHB:0xF8000200 %Long 0x1
+WAIT 0.1s
+PRINT ""
+ON ERROR inherit
+
+PRINT   "Attach and initialize"
+SYStem.Mode.Attach
+Break
+
+PRINT "initializing the target"
+DO "~~/demo/arm/hardware/zynq-7000/scripts/trace/ps7_init.cmm" "&ppd/../ps7_init.tcl"
+
+PRINT "programming the FPGA design"
+LOCAL &bitfile
+&bitfile="&ppd/../base_zynq_wrapper.bit"
+DO "~~/demo/arm/hardware/zynq-7000/scripts/zynq_bitstream" "&bitfile" 0x00100000
+
+; --------------------------------------------------------------------------------
+; initialize ONCHIP trace (ETM)
+Trace.Method Onchip
+ETM.TraceID 1.
+ETM.Trace ON
+ETM.ON
+
+Trace.Clock 666MHz
+ETM.TimeMode CycleAccurate
+
+; Some optional settings
+SETUP.Var %SpotLight
+MAP.BOnchip 0x0--0xffffffff // force onchip-breakpoints
+MODE.HLL
+
+; load code
+Data.LOAD.Elf "&ppd/../../../out/Aufgabe1_ps7_core0.elf"
+
+; run to main
+Go main
+WAIT !STATE.RUN() 
+
+
+; initialize RTOS support
+PRINT "initializing uC/OS-II support..."
+TASK.CONFIG ../ucos    ; load uC/OS-II Awareness
+MENU.ReProgram ../ucos.men ; load uC/OS-II Menu
+HELP.FILTER.Add rtosucos   ; add ucos awareness manual to help filter
+
+ENDDO

Debug/ps7/Aufgabe2/windowSetting.cmm

@@ -0,0 +1,43 @@
+// T3210000 Wed Sep 27 07:34:53 2017
+
+ B::
+ 
+ TOOLBAR ON
+ STATUSBAR ON
+ FramePOS ,,,,Maximized
+ WinPAGE.RESet
+ 
+ WinPAGE.Create P000
+ WinCLEAR
+  
+ WinPOS 0% 0% 50% 78% ,,, W000
+ ;WinTABS 10. 10. 25. 62.
+ wm.List.auto
+ 
+ WinPOS 50% 0% 30% 28% ,,, W001
+ ;WinTABS 13. 0. 0. 0. 0. 0. 0.
+ wm.Break.List
+ 
+ WinPOS 50% 30% 30% 70% ,,, W002
+ wm.Var.Watch %Hex %Decimal
+ 
+ VAR.ADDWATCH OSPrioCur
+ 
+ WinPOS 80% 0% 20% 50% ,,, W003
+ wm.Register /SPOTLIGHT 
+ 
+ WinPOS 0% 80% 50% 20% ,,, W004
+ wm.Symbol.browse \\*\*\*
+ ;WinPAN 0. 239. 
+ 
+ ;WinPOS 50% 50% 30% 50% ,,, W005
+ ;wm.Perf.ListFunc
+ 
+ WinPos 80% 50% 20% 50% ,,, W006
+ wm.Frame /Locals
+ 
+
+ 
+ WinPAGE.select P000
+ 
+ ENDDO

Debug/ps7/Aufgabe2/zc706_onchip_trace.cmm

@@ -0,0 +1,80 @@
+LOCAL &ppd
+&ppd=OS.PPD()
+&tmpDir=OS.PTD()
+
+WinCLEAR
+
+; --------------------------------------------------------------------------------
+; common SYStem settings
+PRINT   "Assigning Cores"
+
+CD &ppd
+RESet
+System.RESet
+SYStem.CPU ZYNQ-7000
+SYStem.CONFIG CORE 1. 1.
+SYStem.CONFIG SLAVE OFF
+CORE.ASSIGN 1.
+
+; set DaisyChaining Parameters of the board
+; check e.g. SYStem.DETECT.ShowCHAIN
+PRINT   "Setting up DaisyChain Parameters"
+SYStem.CONFIG DAPIRPRE  6.
+SYStem.CONFIG DAPIRPOST 0.
+SYStem.CONFIG DAPDRPRE  1.
+SYStem.CONFIG DAPDRPOST 0.
+
+; trigger a soft-reset using the AHB Bus -> we loose the connection
+PRINT   "Trigger Soft-Reset"
+SYStem.Mode.Prepare
+ON ERROR CONTinue
+Data.Set EAHB:0xF8000008 %Long 0xDF0D
+Data.Set EAHB:0xF8000200 %Long 0x1
+WAIT 0.1s
+PRINT ""
+ON ERROR inherit
+
+PRINT   "Attach and initialize"
+SYStem.Mode.Attach
+Break
+
+PRINT "initializing the target"
+DO "~~/demo/arm/hardware/zynq-7000/scripts/trace/ps7_init.cmm" "&ppd/../ps7_init.tcl"
+
+PRINT "programming the FPGA design"
+LOCAL &bitfile
+&bitfile="&ppd/../base_zynq_wrapper.bit"
+DO "~~/demo/arm/hardware/zynq-7000/scripts/zynq_bitstream" "&bitfile" 0x00100000
+
+; --------------------------------------------------------------------------------
+; initialize ONCHIP trace (ETM)
+Trace.Method Onchip
+ETM.TraceID 1.
+ETM.Trace ON
+ETM.ON
+
+Trace.Clock 666MHz
+ETM.TimeMode CycleAccurate
+
+; Some optional settings
+SETUP.Var %SpotLight
+MAP.BOnchip 0x0--0xffffffff // force onchip-breakpoints
+MODE.HLL
+
+; load code
+Data.LOAD.Elf "&ppd/../../../out/Aufgabe2_ps7_core0.elf"
+
+; run to main
+Go main
+WAIT !STATE.RUN() 
+
+; open some windows
+DO windowSetting.cmm
+
+; initialize RTOS support
+PRINT "initializing uC/OS-II support..."
+TASK.CONFIG ../ucos    ; load uC/OS-II Awareness
+MENU.ReProgram ../ucos.men ; load uC/OS-II Menu
+HELP.FILTER.Add rtosucos   ; add ucos awareness manual to help filter
+
+ENDDO

Debug/ps7/Aufgabe3/windowSetting.cmm

@@ -0,0 +1,43 @@
+// T3210000 Wed Sep 27 07:34:53 2017
+
+ B::
+ 
+ TOOLBAR ON
+ STATUSBAR ON
+ FramePOS ,,,,Maximized
+ WinPAGE.RESet
+ 
+ WinPAGE.Create P000
+ WinCLEAR
+  
+ WinPOS 0% 0% 50% 78% ,,, W000
+ ;WinTABS 10. 10. 25. 62.
+ wm.List.auto
+ 
+ WinPOS 50% 0% 30% 28% ,,, W001
+ ;WinTABS 13. 0. 0. 0. 0. 0. 0.
+ wm.Break.List
+ 
+ WinPOS 50% 30% 30% 70% ,,, W002
+ wm.Var.Watch %Hex %Decimal
+ 
+ VAR.ADDWATCH OSPrioCur
+ 
+ WinPOS 80% 0% 20% 50% ,,, W003
+ wm.Register /SPOTLIGHT 
+ 
+ WinPOS 0% 80% 50% 20% ,,, W004
+ wm.Symbol.browse \\*\*\*
+ ;WinPAN 0. 239. 
+ 
+ ;WinPOS 50% 50% 30% 50% ,,, W005
+ ;wm.Perf.ListFunc
+ 
+ WinPos 80% 50% 20% 50% ,,, W006
+ wm.Frame /Locals
+ 
+
+ 
+ WinPAGE.select P000
+ 
+ ENDDO

Debug/ps7/Aufgabe3/zc706_onchip_trace.cmm

@@ -0,0 +1,80 @@
+LOCAL &ppd
+&ppd=OS.PPD()
+&tmpDir=OS.PTD()
+
+WinCLEAR
+
+; --------------------------------------------------------------------------------
+; common SYStem settings
+PRINT   "Assigning Cores"
+
+CD &ppd
+RESet
+System.RESet
+SYStem.CPU ZYNQ-7000
+SYStem.CONFIG CORE 1. 1.
+SYStem.CONFIG SLAVE OFF
+CORE.ASSIGN 1.
+
+; set DaisyChaining Parameters of the board
+; check e.g. SYStem.DETECT.ShowCHAIN
+PRINT   "Setting up DaisyChain Parameters"
+SYStem.CONFIG DAPIRPRE  6.
+SYStem.CONFIG DAPIRPOST 0.
+SYStem.CONFIG DAPDRPRE  1.
+SYStem.CONFIG DAPDRPOST 0.
+
+; trigger a soft-reset using the AHB Bus -> we loose the connection
+PRINT   "Trigger Soft-Reset"
+SYStem.Mode.Prepare
+ON ERROR CONTinue
+Data.Set EAHB:0xF8000008 %Long 0xDF0D
+Data.Set EAHB:0xF8000200 %Long 0x1
+WAIT 0.1s
+PRINT ""
+ON ERROR inherit
+
+PRINT   "Attach and initialize"
+SYStem.Mode.Attach
+Break
+
+PRINT "initializing the target"
+DO "~~/demo/arm/hardware/zynq-7000/scripts/trace/ps7_init.cmm" "&ppd/../ps7_init.tcl"
+
+PRINT "programming the FPGA design"
+LOCAL &bitfile
+&bitfile="&ppd/../base_zynq_wrapper.bit"
+DO "~~/demo/arm/hardware/zynq-7000/scripts/zynq_bitstream" "&bitfile" 0x00100000
+
+; --------------------------------------------------------------------------------
+; initialize ONCHIP trace (ETM)
+Trace.Method Onchip
+ETM.TraceID 1.
+ETM.Trace ON
+ETM.ON
+
+Trace.Clock 666MHz
+ETM.TimeMode CycleAccurate
+
+; Some optional settings
+SETUP.Var %SpotLight
+MAP.BOnchip 0x0--0xffffffff // force onchip-breakpoints
+MODE.HLL
+
+; load code
+Data.LOAD.Elf "&ppd/../../../out/Aufgabe3_ps7_core0.elf"
+
+; run to main
+Go main
+WAIT !STATE.RUN() 
+
+; open some windows
+DO windowSetting.cmm
+
+; initialize RTOS support
+PRINT "initializing uC/OS-II support..."
+TASK.CONFIG ../ucos    ; load uC/OS-II Awareness
+MENU.ReProgram ../ucos.men ; load uC/OS-II Menu
+HELP.FILTER.Add rtosucos   ; add ucos awareness manual to help filter
+
+ENDDO

Debug/ps7/Aufgabe4/windowSetting.cmm

@@ -0,0 +1,43 @@
+// T3210000 Wed Sep 27 07:34:53 2017
+
+ B::
+ 
+ TOOLBAR ON
+ STATUSBAR ON
+ FramePOS ,,,,Maximized
+ WinPAGE.RESet
+ 
+ WinPAGE.Create P000
+ WinCLEAR
+  
+ WinPOS 0% 0% 50% 78% ,,, W000
+ ;WinTABS 10. 10. 25. 62.
+ wm.List.auto
+ 
+ WinPOS 50% 0% 30% 28% ,,, W001
+ ;WinTABS 13. 0. 0. 0. 0. 0. 0.
+ wm.Break.List
+ 
+ WinPOS 50% 30% 30% 70% ,,, W002
+ wm.Var.Watch %Hex %Decimal
+ 
+ VAR.ADDWATCH OSPrioCur
+ 
+ WinPOS 80% 0% 20% 50% ,,, W003
+ wm.Register /SPOTLIGHT 
+ 
+ WinPOS 0% 80% 50% 20% ,,, W004
+ wm.Symbol.browse \\*\*\*
+ ;WinPAN 0. 239. 
+ 
+ ;WinPOS 50% 50% 30% 50% ,,, W005
+ ;wm.Perf.ListFunc
+ 
+ WinPos 80% 50% 20% 50% ,,, W006
+ wm.Frame /Locals
+ 
+
+ 
+ WinPAGE.select P000
+ 
+ ENDDO

Debug/ps7/Aufgabe4/zc706_onchip_trace.cmm

@@ -0,0 +1,80 @@
+LOCAL &ppd
+&ppd=OS.PPD()
+&tmpDir=OS.PTD()
+
+WinCLEAR
+
+; --------------------------------------------------------------------------------
+; common SYStem settings
+PRINT   "Assigning Cores"
+
+CD &ppd
+RESet
+System.RESet
+SYStem.CPU ZYNQ-7000
+SYStem.CONFIG CORE 1. 1.
+SYStem.CONFIG SLAVE OFF
+CORE.ASSIGN 1.
+
+; set DaisyChaining Parameters of the board
+; check e.g. SYStem.DETECT.ShowCHAIN
+PRINT   "Setting up DaisyChain Parameters"
+SYStem.CONFIG DAPIRPRE  6.
+SYStem.CONFIG DAPIRPOST 0.
+SYStem.CONFIG DAPDRPRE  1.
+SYStem.CONFIG DAPDRPOST 0.
+
+; trigger a soft-reset using the AHB Bus -> we loose the connection
+PRINT   "Trigger Soft-Reset"
+SYStem.Mode.Prepare
+ON ERROR CONTinue
+Data.Set EAHB:0xF8000008 %Long 0xDF0D
+Data.Set EAHB:0xF8000200 %Long 0x1
+WAIT 0.1s
+PRINT ""
+ON ERROR inherit
+
+PRINT   "Attach and initialize"
+SYStem.Mode.Attach
+Break
+
+PRINT "initializing the target"
+DO "~~/demo/arm/hardware/zynq-7000/scripts/trace/ps7_init.cmm" "&ppd/../ps7_init.tcl"
+
+PRINT "programming the FPGA design"
+LOCAL &bitfile
+&bitfile="&ppd/../base_zynq_wrapper.bit"
+DO "~~/demo/arm/hardware/zynq-7000/scripts/zynq_bitstream" "&bitfile" 0x00100000
+
+; --------------------------------------------------------------------------------
+; initialize ONCHIP trace (ETM)
+Trace.Method Onchip
+ETM.TraceID 1.
+ETM.Trace ON
+ETM.ON
+
+Trace.Clock 666MHz
+ETM.TimeMode CycleAccurate
+
+; Some optional settings
+SETUP.Var %SpotLight
+MAP.BOnchip 0x0--0xffffffff // force onchip-breakpoints
+MODE.HLL
+
+; load code
+Data.LOAD.Elf "&ppd/../../../out/Aufgabe4_ps7_core0.elf"
+
+; run to main
+Go main
+WAIT !STATE.RUN() 
+
+; open some windows
+DO windowSetting.cmm
+
+; initialize RTOS support
+PRINT "initializing uC/OS-II support..."
+TASK.CONFIG ../ucos    ; load uC/OS-II Awareness
+MENU.ReProgram ../ucos.men ; load uC/OS-II Menu
+HELP.FILTER.Add rtosucos   ; add ucos awareness manual to help filter
+
+ENDDO

Debug/ps7/Aufgabe5/windowSetting.cmm

@@ -0,0 +1,43 @@
+// T3210000 Wed Sep 27 07:34:53 2017
+
+ B::
+ 
+ TOOLBAR ON
+ STATUSBAR ON
+ FramePOS ,,,,Maximized
+ WinPAGE.RESet
+ 
+ WinPAGE.Create P000
+ WinCLEAR
+  
+ WinPOS 0% 0% 50% 78% ,,, W000
+ ;WinTABS 10. 10. 25. 62.
+ wm.List.auto
+ 
+ WinPOS 50% 0% 30% 28% ,,, W001
+ ;WinTABS 13. 0. 0. 0. 0. 0. 0.
+ wm.Break.List
+ 
+ WinPOS 50% 30% 30% 70% ,,, W002
+ wm.Var.Watch %Hex %Decimal
+ 
+ VAR.ADDWATCH OSPrioCur
+ 
+ WinPOS 80% 0% 20% 50% ,,, W003
+ wm.Register /SPOTLIGHT 
+ 
+ WinPOS 0% 80% 50% 20% ,,, W004
+ wm.Symbol.browse \\*\*\*
+ ;WinPAN 0. 239. 
+ 
+ ;WinPOS 50% 50% 30% 50% ,,, W005
+ ;wm.Perf.ListFunc
+ 
+ WinPos 80% 50% 20% 50% ,,, W006
+ wm.Frame /Locals
+ 
+
+ 
+ WinPAGE.select P000
+ 
+ ENDDO

Debug/ps7/Aufgabe5/zc706_onchip_trace.cmm

@@ -0,0 +1,80 @@
+LOCAL &ppd
+&ppd=OS.PPD()
+&tmpDir=OS.PTD()
+
+WinCLEAR
+
+; --------------------------------------------------------------------------------
+; common SYStem settings
+PRINT   "Assigning Cores"
+
+CD &ppd
+RESet
+System.RESet
+SYStem.CPU ZYNQ-7000
+SYStem.CONFIG CORE 1. 1.
+SYStem.CONFIG SLAVE OFF
+CORE.ASSIGN 1.
+
+; set DaisyChaining Parameters of the board
+; check e.g. SYStem.DETECT.ShowCHAIN
+PRINT   "Setting up DaisyChain Parameters"
+SYStem.CONFIG DAPIRPRE  6.
+SYStem.CONFIG DAPIRPOST 0.
+SYStem.CONFIG DAPDRPRE  1.
+SYStem.CONFIG DAPDRPOST 0.
+
+; trigger a soft-reset using the AHB Bus -> we loose the connection
+PRINT   "Trigger Soft-Reset"
+SYStem.Mode.Prepare
+ON ERROR CONTinue
+Data.Set EAHB:0xF8000008 %Long 0xDF0D
+Data.Set EAHB:0xF8000200 %Long 0x1
+WAIT 0.1s
+PRINT ""
+ON ERROR inherit
+
+PRINT   "Attach and initialize"
+SYStem.Mode.Attach
+Break
+
+PRINT "initializing the target"
+DO "~~/demo/arm/hardware/zynq-7000/scripts/trace/ps7_init.cmm" "&ppd/../ps7_init.tcl"
+
+PRINT "programming the FPGA design"
+LOCAL &bitfile
+&bitfile="&ppd/../base_zynq_wrapper.bit"
+DO "~~/demo/arm/hardware/zynq-7000/scripts/zynq_bitstream" "&bitfile" 0x00100000
+
+; --------------------------------------------------------------------------------
+; initialize ONCHIP trace (ETM)
+Trace.Method Onchip
+ETM.TraceID 1.
+ETM.Trace ON
+ETM.ON
+
+Trace.Clock 666MHz
+ETM.TimeMode CycleAccurate
+
+; Some optional settings
+SETUP.Var %SpotLight
+MAP.BOnchip 0x0--0xffffffff // force onchip-breakpoints
+MODE.HLL
+
+; load code
+Data.LOAD.Elf "&ppd/../../../out/Aufgabe5_ps7_core0.elf"
+
+; run to main
+Go main
+WAIT !STATE.RUN() 
+
+; open some windows
+DO windowSetting.cmm
+
+; initialize RTOS support
+PRINT "initializing uC/OS-II support..."
+TASK.CONFIG ../ucos    ; load uC/OS-II Awareness
+MENU.ReProgram ../ucos.men ; load uC/OS-II Menu
+HELP.FILTER.Add rtosucos   ; add ucos awareness manual to help filter
+
+ENDDO

Debug/ps7/Aufgabe6/windowSetting.cmm

@@ -0,0 +1,43 @@
+// T3210000 Wed Sep 27 07:34:53 2017
+
+ B::
+ 
+ TOOLBAR ON
+ STATUSBAR ON
+ FramePOS ,,,,Maximized
+ WinPAGE.RESet
+ 
+ WinPAGE.Create P000
+ WinCLEAR
+  
+ WinPOS 0% 0% 50% 78% ,,, W000
+ ;WinTABS 10. 10. 25. 62.
+ wm.List.auto
+ 
+ WinPOS 50% 0% 30% 28% ,,, W001
+ ;WinTABS 13. 0. 0. 0. 0. 0. 0.
+ wm.Break.List
+ 
+ WinPOS 50% 30% 30% 70% ,,, W002
+ wm.Var.Watch %Hex %Decimal
+ 
+ VAR.ADDWATCH OSPrioCur
+ 
+ WinPOS 80% 0% 20% 50% ,,, W003
+ wm.Register /SPOTLIGHT 
+ 
+ WinPOS 0% 80% 50% 20% ,,, W004
+ wm.Symbol.browse \\*\*\*
+ ;WinPAN 0. 239. 
+ 
+ ;WinPOS 50% 50% 30% 50% ,,, W005
+ ;wm.Perf.ListFunc
+ 
+ WinPos 80% 50% 20% 50% ,,, W006
+ wm.Frame /Locals
+ 
+
+ 
+ WinPAGE.select P000
+ 
+ ENDDO

Debug/ps7/Aufgabe6/zc706_onchip_trace.cmm

@@ -0,0 +1,81 @@
+LOCAL &ppd
+&ppd=OS.PPD()
+&tmpDir=OS.PTD()
+
+WinCLEAR
+
+; --------------------------------------------------------------------------------
+; common SYStem settings
+PRINT   "Assigning Cores"
+
+CD &ppd
+RESet
+System.RESet
+SYStem.CPU ZYNQ-7000
+SYStem.CONFIG CORE 1. 1.
+SYStem.CONFIG SLAVE OFF
+CORE.ASSIGN 1.
+
+; set DaisyChaining Parameters of the board
+; check e.g. SYStem.DETECT.ShowCHAIN
+PRINT   "Setting up DaisyChain Parameters"
+SYStem.CONFIG DAPIRPRE  6.
+SYStem.CONFIG DAPIRPOST 0.
+SYStem.CONFIG DAPDRPRE  1.
+SYStem.CONFIG DAPDRPOST 0.
+
+; trigger a soft-reset using the AHB Bus -> we loose the connection
+PRINT   "Trigger Soft-Reset"
+SYStem.Mode.Prepare
+ON ERROR CONTinue
+Data.Set EAHB:0xF8000008 %Long 0xDF0D
+Data.Set EAHB:0xF8000200 %Long 0x1
+WAIT 0.1s
+PRINT ""
+ON ERROR inherit
+
+PRINT   "Attach and initialize"
+SYStem.Mode.Attach
+Break
+
+PRINT "initializing the target"
+DO "~~/demo/arm/hardware/zynq-7000/scripts/trace/ps7_init.cmm" "&ppd/../ps7_init.tcl"
+
+PRINT "programming the FPGA design"
+LOCAL &bitfile
+&bitfile="&ppd/../base_zynq_wrapper.bit"
+DO "~~/demo/arm/hardware/zynq-7000/scripts/zynq_bitstream" "&bitfile" 0x00100000
+
+; --------------------------------------------------------------------------------
+; initialize ONCHIP trace (ETM)
+Trace.Method Onchip
+ETM.TraceID 1.
+ETM.Trace ON
+ETM.ON
+
+Trace.Clock 666MHz
+ETM.TimeMode CycleAccurate
+
+; Some optional settings
+SETUP.Var %SpotLight
+MAP.BOnchip 0x0--0xffffffff // force onchip-breakpoints
+MODE.HLL
+
+; load code
+Data.LOAD.Elf "&ppd/../../../out/Aufgabe6_ps7_core0.elf"
+
+; run to main
+Go main
+WAIT !STATE.RUN() 
+
+; open some windows
+DO windowSetting.cmm
+
+; initialize RTOS support
+PRINT "initializing uC/OS-II support..."
+TASK.CONFIG ../ucos    ; load uC/OS-II Awareness
+MENU.ReProgram ../ucos.men ; load uC/OS-II Menu
+HELP.FILTER.Add rtosucos   ; add ucos awareness manual to help filter
+
+
+ENDDO

Debug/ps7/Aufgabe7/windowSetting.cmm

@@ -0,0 +1,43 @@
+// T3210000 Wed Sep 27 07:34:53 2017
+
+ B::
+ 
+ TOOLBAR ON
+ STATUSBAR ON
+ FramePOS ,,,,Maximized
+ WinPAGE.RESet
+ 
+ WinPAGE.Create P000
+ WinCLEAR
+  
+ WinPOS 0% 0% 50% 78% ,,, W000
+ ;WinTABS 10. 10. 25. 62.
+ wm.List.auto
+ 
+ WinPOS 50% 0% 30% 28% ,,, W001
+ ;WinTABS 13. 0. 0. 0. 0. 0. 0.
+ wm.Break.List
+ 
+ WinPOS 50% 30% 30% 70% ,,, W002
+ wm.Var.Watch %Hex %Decimal
+ 
+ VAR.ADDWATCH OSPrioCur
+ 
+ WinPOS 80% 0% 20% 50% ,,, W003
+ wm.Register /SPOTLIGHT 
+ 
+ WinPOS 0% 80% 50% 20% ,,, W004
+ wm.Symbol.browse \\*\*\*
+ ;WinPAN 0. 239. 
+ 
+ ;WinPOS 50% 50% 30% 50% ,,, W005
+ ;wm.Perf.ListFunc
+ 
+ WinPos 80% 50% 20% 50% ,,, W006
+ wm.Frame /Locals
+ 
+
+ 
+ WinPAGE.select P000
+ 
+ ENDDO

Debug/ps7/Aufgabe7/zc706_onchip_trace.cmm

@@ -0,0 +1,80 @@
+LOCAL &ppd
+&ppd=OS.PPD()
+&tmpDir=OS.PTD()
+
+WinCLEAR
+
+; --------------------------------------------------------------------------------
+; common SYStem settings
+PRINT   "Assigning Cores"
+
+CD &ppd
+RESet
+System.RESet
+SYStem.CPU ZYNQ-7000
+SYStem.CONFIG CORE 1. 1.
+SYStem.CONFIG SLAVE OFF
+CORE.ASSIGN 1.
+
+; set DaisyChaining Parameters of the board
+; check e.g. SYStem.DETECT.ShowCHAIN
+PRINT   "Setting up DaisyChain Parameters"
+SYStem.CONFIG DAPIRPRE  6.
+SYStem.CONFIG DAPIRPOST 0.
+SYStem.CONFIG DAPDRPRE  1.
+SYStem.CONFIG DAPDRPOST 0.
+
+; trigger a soft-reset using the AHB Bus -> we loose the connection
+PRINT   "Trigger Soft-Reset"
+SYStem.Mode.Prepare
+ON ERROR CONTinue
+Data.Set EAHB:0xF8000008 %Long 0xDF0D
+Data.Set EAHB:0xF8000200 %Long 0x1
+WAIT 0.1s
+PRINT ""
+ON ERROR inherit
+
+PRINT   "Attach and initialize"
+SYStem.Mode.Attach
+Break
+
+PRINT "initializing the target"
+DO "~~/demo/arm/hardware/zynq-7000/scripts/trace/ps7_init.cmm" "&ppd/../ps7_init.tcl"
+
+PRINT "programming the FPGA design"
+LOCAL &bitfile
+&bitfile="&ppd/../base_zynq_wrapper.bit"
+DO "~~/demo/arm/hardware/zynq-7000/scripts/zynq_bitstream" "&bitfile" 0x00100000
+
+; --------------------------------------------------------------------------------
+; initialize ONCHIP trace (ETM)
+Trace.Method Onchip
+ETM.TraceID 1.
+ETM.Trace ON
+ETM.ON
+
+Trace.Clock 666MHz
+ETM.TimeMode CycleAccurate
+
+; Some optional settings
+SETUP.Var %SpotLight
+MAP.BOnchip 0x0--0xffffffff // force onchip-breakpoints
+MODE.HLL
+
+; load code
+Data.LOAD.Elf "&ppd/../../../out/Aufgabe7_ps7_core0.elf"
+
+; run to main
+Go main
+WAIT !STATE.RUN() 
+
+; open some windows
+DO windowSetting.cmm
+
+; initialize RTOS support
+PRINT "initializing uC/OS-II support..."
+TASK.CONFIG ../ucos    ; load uC/OS-II Awareness
+MENU.ReProgram ../ucos.men ; load uC/OS-II Menu
+HELP.FILTER.Add rtosucos   ; add ucos awareness manual to help filter
+
+ENDDO

Debug/ps7/config_amp.t32

@@ -0,0 +1,33 @@
+; --------------------------------------------------------------------------------
+; @Title: TRACE32 Configuration file for AMP multicore debugging
+; @Description:
+;   Parametrized configuration file for TRACE32 to start multiple instances of
+;   TRACE32 for AMP debugging
+; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
+; --------------------------------------------------------------------------------
+; $Id: config_amp.t32 10188 2016-11-18 08:23:44Z amerkle $
+
+IC=NETASSIST
+PORT=${1}
+
+; Environment variables
+OS=
+ID=T32_PORT${1}
+TMP=${3}
+SYS=${4}
+HELP=${4}/pdf
+
+PBI=
+${5}
+${6}
+${7}
+${8}
+
+; Screen fonts
+SCREEN=
+VFULL
+HEADER=${2} TRACE32 
+
+TCF=
+PORT=${9}
+

Debug/ps7/ps7_init.tcl

@@ -0,0 +1,874 @@
+proc ps7_pll_init_data_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000110 0x003FFFF0 0x000FA220
+    mask_write 0XF8000100 0x0007F000 0x00028000
+    mask_write 0XF8000100 0x00000010 0x00000010
+    mask_write 0XF8000100 0x00000001 0x00000001
+    mask_write 0XF8000100 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000001
+    mask_write 0XF8000100 0x00000010 0x00000000
+    mask_write 0XF8000120 0x1F003F30 0x1F000200
+    mask_write 0XF8000114 0x003FFFF0 0x0012C220
+    mask_write 0XF8000104 0x0007F000 0x00020000
+    mask_write 0XF8000104 0x00000010 0x00000010
+    mask_write 0XF8000104 0x00000001 0x00000001
+    mask_write 0XF8000104 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000002
+    mask_write 0XF8000104 0x00000010 0x00000000
+    mask_write 0XF8000124 0xFFF00003 0x0C200003
+    mask_write 0XF8000118 0x003FFFF0 0x001452C0
+    mask_write 0XF8000108 0x0007F000 0x0001E000
+    mask_write 0XF8000108 0x00000010 0x00000010
+    mask_write 0XF8000108 0x00000001 0x00000001
+    mask_write 0XF8000108 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000004
+    mask_write 0XF8000108 0x00000010 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_clock_init_data_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000128 0x03F03F01 0x00700F01
+    mask_write 0XF8000138 0x00000011 0x00000001
+    mask_write 0XF8000140 0x03F03F71 0x00500801
+    mask_write 0XF800014C 0x00003F31 0x00000501
+    mask_write 0XF8000150 0x00003F33 0x00001401
+    mask_write 0XF8000154 0x00003F33 0x00001402
+    mask_write 0XF8000168 0x00003F31 0x00000501
+    mask_write 0XF8000170 0x03F03F30 0x00400500
+    mask_write 0XF80001C4 0x00000001 0x00000001
+    mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_ddr_init_data_3_0 {} {
+    mask_write 0XF8006000 0x0001FFFF 0x00000080
+    mask_write 0XF8006004 0x0007FFFF 0x00001081
+    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+    mask_write 0XF800600C 0x03FFFFFF 0x02001001
+    mask_write 0XF8006010 0x03FFFFFF 0x00014001
+    mask_write 0XF8006014 0x001FFFFF 0x0004159B
+    mask_write 0XF8006018 0xF7FFFFFF 0x452440D2
+    mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
+    mask_write 0XF8006020 0x7FDFFFFC 0x27087290
+    mask_write 0XF8006024 0x0FFFFFC3 0x00000000
+    mask_write 0XF8006028 0x00003FFF 0x00002007
+    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+    mask_write 0XF8006030 0xFFFFFFFF 0x00040930
+    mask_write 0XF8006034 0x13FF3FFF 0x000116D4
+    mask_write 0XF8006038 0x00000003 0x00000000
+    mask_write 0XF800603C 0x000FFFFF 0x00000777
+    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+    mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
+    mask_write 0XF8006048 0x0003F03F 0x0003C008
+    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+    mask_write 0XF8006058 0x00010000 0x00000000
+    mask_write 0XF800605C 0x0000FFFF 0x00005003
+    mask_write 0XF8006060 0x000017FF 0x0000003E
+    mask_write 0XF8006064 0x00021FE0 0x00020000
+    mask_write 0XF8006068 0x03FFFFFF 0x00284141
+    mask_write 0XF800606C 0x0000FFFF 0x00001610
+    mask_write 0XF8006078 0x03FFFFFF 0x00466111
+    mask_write 0XF800607C 0x000FFFFF 0x00032222
+    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+    mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+    mask_write 0XF80060AC 0x000001FF 0x000001FE
+    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+    mask_write 0XF80060B4 0x00000200 0x00000200
+    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+    mask_write 0XF80060C4 0x00000003 0x00000000
+    mask_write 0XF80060C8 0x000000FF 0x00000000
+    mask_write 0XF80060DC 0x00000001 0x00000000
+    mask_write 0XF80060F0 0x0000FFFF 0x00000000
+    mask_write 0XF80060F4 0x0000000F 0x00000008
+    mask_write 0XF8006114 0x000000FF 0x00000000
+    mask_write 0XF8006118 0x7FFFFFCF 0x40000001
+    mask_write 0XF800611C 0x7FFFFFCF 0x40000001
+    mask_write 0XF8006120 0x7FFFFFCF 0x40000001
+    mask_write 0XF8006124 0x7FFFFFCF 0x40000001
+    mask_write 0XF800612C 0x000FFFFF 0x0003B81E
+    mask_write 0XF8006130 0x000FFFFF 0x00043425
+    mask_write 0XF8006134 0x000FFFFF 0x0003CC19
+    mask_write 0XF8006138 0x000FFFFF 0x0004242A
+    mask_write 0XF8006140 0x000FFFFF 0x00000035
+    mask_write 0XF8006144 0x000FFFFF 0x00000035
+    mask_write 0XF8006148 0x000FFFFF 0x00000035
+    mask_write 0XF800614C 0x000FFFFF 0x00000035
+    mask_write 0XF8006154 0x000FFFFF 0x0000009E
+    mask_write 0XF8006158 0x000FFFFF 0x000000A5
+    mask_write 0XF800615C 0x000FFFFF 0x00000099
+    mask_write 0XF8006160 0x000FFFFF 0x000000AA
+    mask_write 0XF8006168 0x001FFFFF 0x00000143
+    mask_write 0XF800616C 0x001FFFFF 0x00000162
+    mask_write 0XF8006170 0x001FFFFF 0x00000148
+    mask_write 0XF8006174 0x001FFFFF 0x0000015E
+    mask_write 0XF800617C 0x000FFFFF 0x000000DE
+    mask_write 0XF8006180 0x000FFFFF 0x000000E5
+    mask_write 0XF8006184 0x000FFFFF 0x000000D9
+    mask_write 0XF8006188 0x000FFFFF 0x000000EA
+    mask_write 0XF8006190 0x6FFFFEFE 0x00040080
+    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+    mask_write 0XF8006208 0x000703FF 0x000003FF
+    mask_write 0XF800620C 0x000703FF 0x000003FF
+    mask_write 0XF8006210 0x000703FF 0x000003FF
+    mask_write 0XF8006214 0x000703FF 0x000003FF
+    mask_write 0XF8006218 0x000F03FF 0x000003FF
+    mask_write 0XF800621C 0x000F03FF 0x000003FF
+    mask_write 0XF8006220 0x000F03FF 0x000003FF
+    mask_write 0XF8006224 0x000F03FF 0x000003FF
+    mask_write 0XF80062A8 0x00000FF5 0x00000000
+    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+    mask_write 0XF80062B0 0x003FFFFF 0x00005125
+    mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+    mask_poll 0XF8000B74 0x00002000
+    mask_write 0XF8006000 0x0001FFFF 0x00000081
+    mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B00 0x00000071 0x00000001
+    mask_write 0XF8000B40 0x00000FFF 0x00000600
+    mask_write 0XF8000B44 0x00000FFF 0x00000600
+    mask_write 0XF8000B48 0x00000FFF 0x00000672
+    mask_write 0XF8000B4C 0x00000FFF 0x00000672
+    mask_write 0XF8000B50 0x00000FFF 0x00000674
+    mask_write 0XF8000B54 0x00000FFF 0x00000674
+    mask_write 0XF8000B58 0x00000FFF 0x00000600
+    mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
+    mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B6C 0x00007FFF 0x00000209
+    mask_write 0XF8000B70 0x00000001 0x00000001
+    mask_write 0XF8000B70 0x00000021 0x00000020
+    mask_write 0XF8000B70 0x07FEFFFF 0x00000823
+    mask_write 0XF8000700 0x00003FFF 0x00001202
+    mask_write 0XF8000704 0x00003FFF 0x00001202
+    mask_write 0XF8000708 0x00003FFF 0x00000202
+    mask_write 0XF800070C 0x00003FFF 0x00000202
+    mask_write 0XF8000710 0x00003FFF 0x00000202
+    mask_write 0XF8000714 0x00003FFF 0x00000202
+    mask_write 0XF8000718 0x00003FFF 0x00000202
+    mask_write 0XF800071C 0x00003FFF 0x00000200
+    mask_write 0XF8000720 0x00003FFF 0x00000202
+    mask_write 0XF8000724 0x00003FFF 0x00001202
+    mask_write 0XF8000728 0x00003FFF 0x00001202
+    mask_write 0XF800072C 0x00003FFF 0x00001202
+    mask_write 0XF8000730 0x00003FFF 0x00001202
+    mask_write 0XF8000734 0x00003FFF 0x00001202
+    mask_write 0XF8000738 0x00003F01 0x00001201
+    mask_write 0XF800073C 0x00003F01 0x00001201
+    mask_write 0XF8000740 0x00003FFF 0x00002802
+    mask_write 0XF8000744 0x00003FFF 0x00002802
+    mask_write 0XF8000748 0x00003FFF 0x00002802
+    mask_write 0XF800074C 0x00003FFF 0x00002802
+    mask_write 0XF8000750 0x00003FFF 0x00002802
+    mask_write 0XF8000754 0x00003FFF 0x00002802
+    mask_write 0XF8000758 0x00003FFF 0x00000803
+    mask_write 0XF800075C 0x00003FFF 0x00000803
+    mask_write 0XF8000760 0x00003FFF 0x00000803
+    mask_write 0XF8000764 0x00003FFF 0x00000803
+    mask_write 0XF8000768 0x00003FFF 0x00000803
+    mask_write 0XF800076C 0x00003FFF 0x00000803
+    mask_write 0XF8000770 0x00003FFF 0x00000204
+    mask_write 0XF8000774 0x00003FFF 0x00000205
+    mask_write 0XF8000778 0x00003FFF 0x00000204
+    mask_write 0XF800077C 0x00003FFF 0x00000205
+    mask_write 0XF8000780 0x00003FFF 0x00000204
+    mask_write 0XF8000784 0x00003FFF 0x00000204
+    mask_write 0XF8000788 0x00003FFF 0x00000204
+    mask_write 0XF800078C 0x00003FFF 0x00000204
+    mask_write 0XF8000790 0x00003FFF 0x00000205
+    mask_write 0XF8000794 0x00003FFF 0x00000204
+    mask_write 0XF8000798 0x00003FFF 0x00000204
+    mask_write 0XF800079C 0x00003FFF 0x00000204
+    mask_write 0XF80007A0 0x00003FFF 0x00000280
+    mask_write 0XF80007A4 0x00003FFF 0x00000280
+    mask_write 0XF80007A8 0x00003FFF 0x00000280
+    mask_write 0XF80007AC 0x00003FFF 0x00000280
+    mask_write 0XF80007B0 0x00003FFF 0x00000280
+    mask_write 0XF80007B4 0x00003FFF 0x00000280
+    mask_write 0XF80007B8 0x00003FFF 0x00001200
+    mask_write 0XF80007BC 0x00003FFF 0x00001200
+    mask_write 0XF80007C0 0x00003FFF 0x000002E0
+    mask_write 0XF80007C4 0x00003FFF 0x000002E1
+    mask_write 0XF80007C8 0x00003FFF 0x00001240
+    mask_write 0XF80007CC 0x00003FFF 0x00001240
+    mask_write 0XF80007D0 0x00003FFF 0x00000280
+    mask_write 0XF80007D4 0x00003FFF 0x00000280
+    mask_write 0XF8000830 0x003F003F 0x000E000F
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_peripherals_init_data_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B48 0x00000180 0x00000180
+    mask_write 0XF8000B4C 0x00000180 0x00000180
+    mask_write 0XF8000B50 0x00000180 0x00000180
+    mask_write 0XF8000B54 0x00000180 0x00000180
+    mwr -force 0XF8000004 0x0000767B
+    mask_write 0XE0001034 0x000000FF 0x00000006
+    mask_write 0XE0001018 0x0000FFFF 0x0000003E
+    mask_write 0XE0001000 0x000001FF 0x00000017
+    mask_write 0XE0001004 0x000003FF 0x00000020
+    mask_write 0XE000D000 0x00080000 0x00080000
+    mask_write 0XF8007000 0x20000000 0x00000000
+    mask_write 0XE000A204 0xFFFFFFFF 0x00000080
+    mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080
+    mask_write 0XE000A208 0xFFFFFFFF 0x00000080
+    mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080
+    mask_write 0XE000A244 0x003FFFFF 0x0000C000
+    mask_write 0XE000A008 0xFFFFFFFF 0x7FFF8000
+    mask_write 0XE000A248 0x003FFFFF 0x0000C000
+    mask_write 0XE000A008 0xFFFFFFFF 0x7FFF0000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A008 0xFFFFFFFF 0x7FFF8000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A244 0x003FFFFF 0x0000C000
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
+    mask_write 0XE000A248 0x003FFFFF 0x0000C000
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
+}
+proc ps7_post_config_3_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000900 0x0000000F 0x0000000F
+    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_debug_3_0 {} {
+    mwr -force 0XF8898FB0 0xC5ACCE55
+    mwr -force 0XF8899FB0 0xC5ACCE55
+    mwr -force 0XF8809FB0 0xC5ACCE55
+}
+proc ps7_pll_init_data_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000110 0x003FFFF0 0x000FA220
+    mask_write 0XF8000100 0x0007F000 0x00028000
+    mask_write 0XF8000100 0x00000010 0x00000010
+    mask_write 0XF8000100 0x00000001 0x00000001
+    mask_write 0XF8000100 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000001
+    mask_write 0XF8000100 0x00000010 0x00000000
+    mask_write 0XF8000120 0x1F003F30 0x1F000200
+    mask_write 0XF8000114 0x003FFFF0 0x0012C220
+    mask_write 0XF8000104 0x0007F000 0x00020000
+    mask_write 0XF8000104 0x00000010 0x00000010
+    mask_write 0XF8000104 0x00000001 0x00000001
+    mask_write 0XF8000104 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000002
+    mask_write 0XF8000104 0x00000010 0x00000000
+    mask_write 0XF8000124 0xFFF00003 0x0C200003
+    mask_write 0XF8000118 0x003FFFF0 0x001452C0
+    mask_write 0XF8000108 0x0007F000 0x0001E000
+    mask_write 0XF8000108 0x00000010 0x00000010
+    mask_write 0XF8000108 0x00000001 0x00000001
+    mask_write 0XF8000108 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000004
+    mask_write 0XF8000108 0x00000010 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_clock_init_data_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000128 0x03F03F01 0x00700F01
+    mask_write 0XF8000138 0x00000011 0x00000001
+    mask_write 0XF8000140 0x03F03F71 0x00500801
+    mask_write 0XF800014C 0x00003F31 0x00000501
+    mask_write 0XF8000150 0x00003F33 0x00001401
+    mask_write 0XF8000154 0x00003F33 0x00001402
+    mask_write 0XF8000168 0x00003F31 0x00000501
+    mask_write 0XF8000170 0x03F03F30 0x00400500
+    mask_write 0XF80001C4 0x00000001 0x00000001
+    mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_ddr_init_data_2_0 {} {
+    mask_write 0XF8006000 0x0001FFFF 0x00000080
+    mask_write 0XF8006004 0x1FFFFFFF 0x00081081
+    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+    mask_write 0XF800600C 0x03FFFFFF 0x02001001
+    mask_write 0XF8006010 0x03FFFFFF 0x00014001
+    mask_write 0XF8006014 0x001FFFFF 0x0004159B
+    mask_write 0XF8006018 0xF7FFFFFF 0x452440D2
+    mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
+    mask_write 0XF8006020 0xFFFFFFFC 0x27287290
+    mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
+    mask_write 0XF8006028 0x00003FFF 0x00002007
+    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+    mask_write 0XF8006030 0xFFFFFFFF 0x00040930
+    mask_write 0XF8006034 0x13FF3FFF 0x000116D4
+    mask_write 0XF8006038 0x00001FC3 0x00000000
+    mask_write 0XF800603C 0x000FFFFF 0x00000777
+    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+    mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
+    mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
+    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+    mask_write 0XF8006058 0x0001FFFF 0x00000101
+    mask_write 0XF800605C 0x0000FFFF 0x00005003
+    mask_write 0XF8006060 0x000017FF 0x0000003E
+    mask_write 0XF8006064 0x00021FE0 0x00020000
+    mask_write 0XF8006068 0x03FFFFFF 0x00284141
+    mask_write 0XF800606C 0x0000FFFF 0x00001610
+    mask_write 0XF8006078 0x03FFFFFF 0x00466111
+    mask_write 0XF800607C 0x000FFFFF 0x00032222
+    mask_write 0XF80060A0 0x00FFFFFF 0x00008000
+    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+    mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+    mask_write 0XF80060AC 0x000001FF 0x000001FE
+    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+    mask_write 0XF80060B4 0x000007FF 0x00000200
+    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+    mask_write 0XF80060C4 0x00000003 0x00000000
+    mask_write 0XF80060C8 0x000000FF 0x00000000
+    mask_write 0XF80060DC 0x00000001 0x00000000
+    mask_write 0XF80060F0 0x0000FFFF 0x00000000
+    mask_write 0XF80060F4 0x0000000F 0x00000008
+    mask_write 0XF8006114 0x000000FF 0x00000000
+    mask_write 0XF8006118 0x7FFFFFFF 0x40000001
+    mask_write 0XF800611C 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006120 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006124 0x7FFFFFFF 0x40000001
+    mask_write 0XF800612C 0x000FFFFF 0x0003B81E
+    mask_write 0XF8006130 0x000FFFFF 0x00043425
+    mask_write 0XF8006134 0x000FFFFF 0x0003CC19
+    mask_write 0XF8006138 0x000FFFFF 0x0004242A
+    mask_write 0XF8006140 0x000FFFFF 0x00000035
+    mask_write 0XF8006144 0x000FFFFF 0x00000035
+    mask_write 0XF8006148 0x000FFFFF 0x00000035
+    mask_write 0XF800614C 0x000FFFFF 0x00000035
+    mask_write 0XF8006154 0x000FFFFF 0x0000009E
+    mask_write 0XF8006158 0x000FFFFF 0x000000A5
+    mask_write 0XF800615C 0x000FFFFF 0x00000099
+    mask_write 0XF8006160 0x000FFFFF 0x000000AA
+    mask_write 0XF8006168 0x001FFFFF 0x00000143
+    mask_write 0XF800616C 0x001FFFFF 0x00000162
+    mask_write 0XF8006170 0x001FFFFF 0x00000148
+    mask_write 0XF8006174 0x001FFFFF 0x0000015E
+    mask_write 0XF800617C 0x000FFFFF 0x000000DE
+    mask_write 0XF8006180 0x000FFFFF 0x000000E5
+    mask_write 0XF8006184 0x000FFFFF 0x000000D9
+    mask_write 0XF8006188 0x000FFFFF 0x000000EA
+    mask_write 0XF8006190 0xFFFFFFFF 0x10040080
+    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+    mask_write 0XF8006208 0x000F03FF 0x000803FF
+    mask_write 0XF800620C 0x000F03FF 0x000803FF
+    mask_write 0XF8006210 0x000F03FF 0x000803FF
+    mask_write 0XF8006214 0x000F03FF 0x000803FF
+    mask_write 0XF8006218 0x000F03FF 0x000003FF
+    mask_write 0XF800621C 0x000F03FF 0x000003FF
+    mask_write 0XF8006220 0x000F03FF 0x000003FF
+    mask_write 0XF8006224 0x000F03FF 0x000003FF
+    mask_write 0XF80062A8 0x00000FF7 0x00000000
+    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+    mask_write 0XF80062B0 0x003FFFFF 0x00005125
+    mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+    mask_poll 0XF8000B74 0x00002000
+    mask_write 0XF8006000 0x0001FFFF 0x00000081
+    mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B00 0x00000303 0x00000001
+    mask_write 0XF8000B40 0x00000FFF 0x00000600
+    mask_write 0XF8000B44 0x00000FFF 0x00000600
+    mask_write 0XF8000B48 0x00000FFF 0x00000672
+    mask_write 0XF8000B4C 0x00000FFF 0x00000672
+    mask_write 0XF8000B50 0x00000FFF 0x00000674
+    mask_write 0XF8000B54 0x00000FFF 0x00000674
+    mask_write 0XF8000B58 0x00000FFF 0x00000600
+    mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
+    mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B6C 0x00007FFF 0x00000209
+    mask_write 0XF8000B70 0x00000021 0x00000021
+    mask_write 0XF8000B70 0x00000021 0x00000020
+    mask_write 0XF8000B70 0x07FFFFFF 0x00000823
+    mask_write 0XF8000700 0x00003FFF 0x00001202
+    mask_write 0XF8000704 0x00003FFF 0x00001202
+    mask_write 0XF8000708 0x00003FFF 0x00000202
+    mask_write 0XF800070C 0x00003FFF 0x00000202
+    mask_write 0XF8000710 0x00003FFF 0x00000202
+    mask_write 0XF8000714 0x00003FFF 0x00000202
+    mask_write 0XF8000718 0x00003FFF 0x00000202
+    mask_write 0XF800071C 0x00003FFF 0x00000200
+    mask_write 0XF8000720 0x00003FFF 0x00000202
+    mask_write 0XF8000724 0x00003FFF 0x00001202
+    mask_write 0XF8000728 0x00003FFF 0x00001202
+    mask_write 0XF800072C 0x00003FFF 0x00001202
+    mask_write 0XF8000730 0x00003FFF 0x00001202
+    mask_write 0XF8000734 0x00003FFF 0x00001202
+    mask_write 0XF8000738 0x00003F01 0x00001201
+    mask_write 0XF800073C 0x00003F01 0x00001201
+    mask_write 0XF8000740 0x00003FFF 0x00002802
+    mask_write 0XF8000744 0x00003FFF 0x00002802
+    mask_write 0XF8000748 0x00003FFF 0x00002802
+    mask_write 0XF800074C 0x00003FFF 0x00002802
+    mask_write 0XF8000750 0x00003FFF 0x00002802
+    mask_write 0XF8000754 0x00003FFF 0x00002802
+    mask_write 0XF8000758 0x00003FFF 0x00000803
+    mask_write 0XF800075C 0x00003FFF 0x00000803
+    mask_write 0XF8000760 0x00003FFF 0x00000803
+    mask_write 0XF8000764 0x00003FFF 0x00000803
+    mask_write 0XF8000768 0x00003FFF 0x00000803
+    mask_write 0XF800076C 0x00003FFF 0x00000803
+    mask_write 0XF8000770 0x00003FFF 0x00000204
+    mask_write 0XF8000774 0x00003FFF 0x00000205
+    mask_write 0XF8000778 0x00003FFF 0x00000204
+    mask_write 0XF800077C 0x00003FFF 0x00000205
+    mask_write 0XF8000780 0x00003FFF 0x00000204
+    mask_write 0XF8000784 0x00003FFF 0x00000204
+    mask_write 0XF8000788 0x00003FFF 0x00000204
+    mask_write 0XF800078C 0x00003FFF 0x00000204
+    mask_write 0XF8000790 0x00003FFF 0x00000205
+    mask_write 0XF8000794 0x00003FFF 0x00000204
+    mask_write 0XF8000798 0x00003FFF 0x00000204
+    mask_write 0XF800079C 0x00003FFF 0x00000204
+    mask_write 0XF80007A0 0x00003FFF 0x00000280
+    mask_write 0XF80007A4 0x00003FFF 0x00000280
+    mask_write 0XF80007A8 0x00003FFF 0x00000280
+    mask_write 0XF80007AC 0x00003FFF 0x00000280
+    mask_write 0XF80007B0 0x00003FFF 0x00000280
+    mask_write 0XF80007B4 0x00003FFF 0x00000280
+    mask_write 0XF80007B8 0x00003FFF 0x00001200
+    mask_write 0XF80007BC 0x00003FFF 0x00001200
+    mask_write 0XF80007C0 0x00003FFF 0x000002E0
+    mask_write 0XF80007C4 0x00003FFF 0x000002E1
+    mask_write 0XF80007C8 0x00003FFF 0x00001240
+    mask_write 0XF80007CC 0x00003FFF 0x00001240
+    mask_write 0XF80007D0 0x00003FFF 0x00000280
+    mask_write 0XF80007D4 0x00003FFF 0x00000280
+    mask_write 0XF8000830 0x003F003F 0x000E000F
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_peripherals_init_data_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B48 0x00000180 0x00000180
+    mask_write 0XF8000B4C 0x00000180 0x00000180
+    mask_write 0XF8000B50 0x00000180 0x00000180
+    mask_write 0XF8000B54 0x00000180 0x00000180
+    mwr -force 0XF8000004 0x0000767B
+    mask_write 0XE0001034 0x000000FF 0x00000006
+    mask_write 0XE0001018 0x0000FFFF 0x0000003E
+    mask_write 0XE0001000 0x000001FF 0x00000017
+    mask_write 0XE0001004 0x00000FFF 0x00000020
+    mask_write 0XE000D000 0x00080000 0x00080000
+    mask_write 0XF8007000 0x20000000 0x00000000
+    mask_write 0XE000A204 0xFFFFFFFF 0x00000080
+    mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080
+    mask_write 0XE000A208 0xFFFFFFFF 0x00000080
+    mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080
+    mask_write 0XE000A244 0x003FFFFF 0x0000C000
+    mask_write 0XE000A008 0xFFFFFFFF 0x7FFF8000
+    mask_write 0XE000A248 0x003FFFFF 0x0000C000
+    mask_write 0XE000A008 0xFFFFFFFF 0x7FFF0000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A008 0xFFFFFFFF 0x7FFF8000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A244 0x003FFFFF 0x0000C000
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
+    mask_write 0XE000A248 0x003FFFFF 0x0000C000
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
+}
+proc ps7_post_config_2_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000900 0x0000000F 0x0000000F
+    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_debug_2_0 {} {
+    mwr -force 0XF8898FB0 0xC5ACCE55
+    mwr -force 0XF8899FB0 0xC5ACCE55
+    mwr -force 0XF8809FB0 0xC5ACCE55
+}
+proc ps7_pll_init_data_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000110 0x003FFFF0 0x000FA220
+    mask_write 0XF8000100 0x0007F000 0x00028000
+    mask_write 0XF8000100 0x00000010 0x00000010
+    mask_write 0XF8000100 0x00000001 0x00000001
+    mask_write 0XF8000100 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000001
+    mask_write 0XF8000100 0x00000010 0x00000000
+    mask_write 0XF8000120 0x1F003F30 0x1F000200
+    mask_write 0XF8000114 0x003FFFF0 0x0012C220
+    mask_write 0XF8000104 0x0007F000 0x00020000
+    mask_write 0XF8000104 0x00000010 0x00000010
+    mask_write 0XF8000104 0x00000001 0x00000001
+    mask_write 0XF8000104 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000002
+    mask_write 0XF8000104 0x00000010 0x00000000
+    mask_write 0XF8000124 0xFFF00003 0x0C200003
+    mask_write 0XF8000118 0x003FFFF0 0x001452C0
+    mask_write 0XF8000108 0x0007F000 0x0001E000
+    mask_write 0XF8000108 0x00000010 0x00000010
+    mask_write 0XF8000108 0x00000001 0x00000001
+    mask_write 0XF8000108 0x00000001 0x00000000
+    mask_poll 0XF800010C 0x00000004
+    mask_write 0XF8000108 0x00000010 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_clock_init_data_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000128 0x03F03F01 0x00700F01
+    mask_write 0XF8000138 0x00000011 0x00000001
+    mask_write 0XF8000140 0x03F03F71 0x00500801
+    mask_write 0XF800014C 0x00003F31 0x00000501
+    mask_write 0XF8000150 0x00003F33 0x00001401
+    mask_write 0XF8000154 0x00003F33 0x00001402
+    mask_write 0XF8000168 0x00003F31 0x00000501
+    mask_write 0XF8000170 0x03F03F30 0x00400500
+    mask_write 0XF80001C4 0x00000001 0x00000001
+    mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_ddr_init_data_1_0 {} {
+    mask_write 0XF8006000 0x0001FFFF 0x00000080
+    mask_write 0XF8006004 0x1FFFFFFF 0x00081081
+    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
+    mask_write 0XF800600C 0x03FFFFFF 0x02001001
+    mask_write 0XF8006010 0x03FFFFFF 0x00014001
+    mask_write 0XF8006014 0x001FFFFF 0x0004159B
+    mask_write 0XF8006018 0xF7FFFFFF 0x452440D2
+    mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
+    mask_write 0XF8006020 0xFFFFFFFC 0x27287290
+    mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
+    mask_write 0XF8006028 0x00003FFF 0x00002007
+    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
+    mask_write 0XF8006030 0xFFFFFFFF 0x00040930
+    mask_write 0XF8006034 0x13FF3FFF 0x000116D4
+    mask_write 0XF8006038 0x00001FC3 0x00000000
+    mask_write 0XF800603C 0x000FFFFF 0x00000777
+    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
+    mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
+    mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
+    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
+    mask_write 0XF8006058 0x0001FFFF 0x00000101
+    mask_write 0XF800605C 0x0000FFFF 0x00005003
+    mask_write 0XF8006060 0x000017FF 0x0000003E
+    mask_write 0XF8006064 0x00021FE0 0x00020000
+    mask_write 0XF8006068 0x03FFFFFF 0x00284141
+    mask_write 0XF800606C 0x0000FFFF 0x00001610
+    mask_write 0XF80060A0 0x00FFFFFF 0x00008000
+    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
+    mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
+    mask_write 0XF80060AC 0x000001FF 0x000001FE
+    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
+    mask_write 0XF80060B4 0x000007FF 0x00000200
+    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
+    mask_write 0XF80060C4 0x00000003 0x00000000
+    mask_write 0XF80060C8 0x000000FF 0x00000000
+    mask_write 0XF80060DC 0x00000001 0x00000000
+    mask_write 0XF80060F0 0x0000FFFF 0x00000000
+    mask_write 0XF80060F4 0x0000000F 0x00000008
+    mask_write 0XF8006114 0x000000FF 0x00000000
+    mask_write 0XF8006118 0x7FFFFFFF 0x40000001
+    mask_write 0XF800611C 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006120 0x7FFFFFFF 0x40000001
+    mask_write 0XF8006124 0x7FFFFFFF 0x40000001
+    mask_write 0XF800612C 0x000FFFFF 0x0003B81E
+    mask_write 0XF8006130 0x000FFFFF 0x00043425
+    mask_write 0XF8006134 0x000FFFFF 0x0003CC19
+    mask_write 0XF8006138 0x000FFFFF 0x0004242A
+    mask_write 0XF8006140 0x000FFFFF 0x00000035
+    mask_write 0XF8006144 0x000FFFFF 0x00000035
+    mask_write 0XF8006148 0x000FFFFF 0x00000035
+    mask_write 0XF800614C 0x000FFFFF 0x00000035
+    mask_write 0XF8006154 0x000FFFFF 0x0000009E
+    mask_write 0XF8006158 0x000FFFFF 0x000000A5
+    mask_write 0XF800615C 0x000FFFFF 0x00000099
+    mask_write 0XF8006160 0x000FFFFF 0x000000AA
+    mask_write 0XF8006168 0x001FFFFF 0x00000143
+    mask_write 0XF800616C 0x001FFFFF 0x00000162
+    mask_write 0XF8006170 0x001FFFFF 0x00000148
+    mask_write 0XF8006174 0x001FFFFF 0x0000015E
+    mask_write 0XF800617C 0x000FFFFF 0x000000DE
+    mask_write 0XF8006180 0x000FFFFF 0x000000E5
+    mask_write 0XF8006184 0x000FFFFF 0x000000D9
+    mask_write 0XF8006188 0x000FFFFF 0x000000EA
+    mask_write 0XF8006190 0xFFFFFFFF 0x10040080
+    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
+    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
+    mask_write 0XF8006208 0x000F03FF 0x000803FF
+    mask_write 0XF800620C 0x000F03FF 0x000803FF
+    mask_write 0XF8006210 0x000F03FF 0x000803FF
+    mask_write 0XF8006214 0x000F03FF 0x000803FF
+    mask_write 0XF8006218 0x000F03FF 0x000003FF
+    mask_write 0XF800621C 0x000F03FF 0x000003FF
+    mask_write 0XF8006220 0x000F03FF 0x000003FF
+    mask_write 0XF8006224 0x000F03FF 0x000003FF
+    mask_write 0XF80062A8 0x00000FF7 0x00000000
+    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
+    mask_write 0XF80062B0 0x003FFFFF 0x00005125
+    mask_write 0XF80062B4 0x0003FFFF 0x000012A8
+    mask_poll 0XF8000B74 0x00002000
+    mask_write 0XF8006000 0x0001FFFF 0x00000081
+    mask_poll 0XF8006054 0x00000007
+}
+proc ps7_mio_init_data_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B00 0x00000303 0x00000001
+    mask_write 0XF8000B40 0x00000FFF 0x00000600
+    mask_write 0XF8000B44 0x00000FFF 0x00000600
+    mask_write 0XF8000B48 0x00000FFF 0x00000672
+    mask_write 0XF8000B4C 0x00000FFF 0x00000672
+    mask_write 0XF8000B50 0x00000FFF 0x00000674
+    mask_write 0XF8000B54 0x00000FFF 0x00000674
+    mask_write 0XF8000B58 0x00000FFF 0x00000600
+    mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
+    mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
+    mask_write 0XF8000B6C 0x000073FF 0x00000209
+    mask_write 0XF8000B70 0x00000021 0x00000021
+    mask_write 0XF8000B70 0x00000021 0x00000020
+    mask_write 0XF8000B70 0x07FFFFFF 0x00000823
+    mask_write 0XF8000700 0x00003FFF 0x00001202
+    mask_write 0XF8000704 0x00003FFF 0x00001202
+    mask_write 0XF8000708 0x00003FFF 0x00000202
+    mask_write 0XF800070C 0x00003FFF 0x00000202
+    mask_write 0XF8000710 0x00003FFF 0x00000202
+    mask_write 0XF8000714 0x00003FFF 0x00000202
+    mask_write 0XF8000718 0x00003FFF 0x00000202
+    mask_write 0XF800071C 0x00003FFF 0x00000200
+    mask_write 0XF8000720 0x00003FFF 0x00000202
+    mask_write 0XF8000724 0x00003FFF 0x00001202
+    mask_write 0XF8000728 0x00003FFF 0x00001202
+    mask_write 0XF800072C 0x00003FFF 0x00001202
+    mask_write 0XF8000730 0x00003FFF 0x00001202
+    mask_write 0XF8000734 0x00003FFF 0x00001202
+    mask_write 0XF8000738 0x00003F01 0x00001201
+    mask_write 0XF800073C 0x00003F01 0x00001201
+    mask_write 0XF8000740 0x00003FFF 0x00002802
+    mask_write 0XF8000744 0x00003FFF 0x00002802
+    mask_write 0XF8000748 0x00003FFF 0x00002802
+    mask_write 0XF800074C 0x00003FFF 0x00002802
+    mask_write 0XF8000750 0x00003FFF 0x00002802
+    mask_write 0XF8000754 0x00003FFF 0x00002802
+    mask_write 0XF8000758 0x00003FFF 0x00000803
+    mask_write 0XF800075C 0x00003FFF 0x00000803
+    mask_write 0XF8000760 0x00003FFF 0x00000803
+    mask_write 0XF8000764 0x00003FFF 0x00000803
+    mask_write 0XF8000768 0x00003FFF 0x00000803
+    mask_write 0XF800076C 0x00003FFF 0x00000803
+    mask_write 0XF8000770 0x00003FFF 0x00000204
+    mask_write 0XF8000774 0x00003FFF 0x00000205
+    mask_write 0XF8000778 0x00003FFF 0x00000204
+    mask_write 0XF800077C 0x00003FFF 0x00000205
+    mask_write 0XF8000780 0x00003FFF 0x00000204
+    mask_write 0XF8000784 0x00003FFF 0x00000204
+    mask_write 0XF8000788 0x00003FFF 0x00000204
+    mask_write 0XF800078C 0x00003FFF 0x00000204
+    mask_write 0XF8000790 0x00003FFF 0x00000205
+    mask_write 0XF8000794 0x00003FFF 0x00000204
+    mask_write 0XF8000798 0x00003FFF 0x00000204
+    mask_write 0XF800079C 0x00003FFF 0x00000204
+    mask_write 0XF80007A0 0x00003FFF 0x00000280
+    mask_write 0XF80007A4 0x00003FFF 0x00000280
+    mask_write 0XF80007A8 0x00003FFF 0x00000280
+    mask_write 0XF80007AC 0x00003FFF 0x00000280
+    mask_write 0XF80007B0 0x00003FFF 0x00000280
+    mask_write 0XF80007B4 0x00003FFF 0x00000280
+    mask_write 0XF80007B8 0x00003FFF 0x00001200
+    mask_write 0XF80007BC 0x00003FFF 0x00001200
+    mask_write 0XF80007C0 0x00003FFF 0x000002E0
+    mask_write 0XF80007C4 0x00003FFF 0x000002E1
+    mask_write 0XF80007C8 0x00003FFF 0x00001240
+    mask_write 0XF80007CC 0x00003FFF 0x00001240
+    mask_write 0XF80007D0 0x00003FFF 0x00000280
+    mask_write 0XF80007D4 0x00003FFF 0x00000280
+    mask_write 0XF8000830 0x003F003F 0x000E000F
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_peripherals_init_data_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000B48 0x00000180 0x00000180
+    mask_write 0XF8000B4C 0x00000180 0x00000180
+    mask_write 0XF8000B50 0x00000180 0x00000180
+    mask_write 0XF8000B54 0x00000180 0x00000180
+    mwr -force 0XF8000004 0x0000767B
+    mask_write 0XE0001034 0x000000FF 0x00000006
+    mask_write 0XE0001018 0x0000FFFF 0x0000003E
+    mask_write 0XE0001000 0x000001FF 0x00000017
+    mask_write 0XE0001004 0x00000FFF 0x00000020
+    mask_write 0XE000D000 0x00080000 0x00080000
+    mask_write 0XF8007000 0x20000000 0x00000000
+    mask_write 0XE000A204 0xFFFFFFFF 0x00000080
+    mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080
+    mask_write 0XE000A208 0xFFFFFFFF 0x00000080
+    mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080
+    mask_write 0XE000A244 0x003FFFFF 0x0000C000
+    mask_write 0XE000A008 0xFFFFFFFF 0x7FFF8000
+    mask_write 0XE000A248 0x003FFFFF 0x0000C000
+    mask_write 0XE000A008 0xFFFFFFFF 0x7FFF0000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A008 0xFFFFFFFF 0x7FFF8000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A244 0x003FFFFF 0x0000C000
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
+    mask_write 0XE000A248 0x003FFFFF 0x0000C000
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF0000
+    mask_delay 0XF8F00200 1
+    mask_write 0XE000A008 0xFFFFFFFF 0xBFFF4000
+}
+proc ps7_post_config_1_0 {} {
+    mwr -force 0XF8000008 0x0000DF0D
+    mask_write 0XF8000900 0x0000000F 0x0000000F
+    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
+    mwr -force 0XF8000004 0x0000767B
+}
+proc ps7_debug_1_0 {} {
+    mwr -force 0XF8898FB0 0xC5ACCE55
+    mwr -force 0XF8899FB0 0xC5ACCE55
+    mwr -force 0XF8809FB0 0xC5ACCE55
+}
+set PCW_SILICON_VER_1_0 "0x0"
+set PCW_SILICON_VER_2_0 "0x1"
+set PCW_SILICON_VER_3_0 "0x2"
+set APU_FREQ  667000000
+
+
+
+proc mask_poll { addr mask } {
+    set count 1
+    set curval "0x[string range [mrd $addr] end-8 end]"
+    set maskedval [expr {$curval & $mask}]
+    while { $maskedval == 0 } {
+        set curval "0x[string range [mrd $addr] end-8 end]"
+        set maskedval [expr {$curval & $mask}]
+        set count [ expr { $count + 1 } ]
+        if { $count == 100000000 } {
+          puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
+          break
+        }
+    }
+}
+
+
+
+proc mask_delay { addr val } {
+    set delay  [ get_number_of_cycles_for_delay $val ]
+    perf_reset_and_start_timer
+    set curval "0x[string range [mrd $addr] end-8 end]"
+    set maskedval [expr {$curval < $delay}]
+    while { $maskedval == 1 } {
+        set curval "0x[string range [mrd $addr] end-8 end]"
+        set maskedval [expr {$curval < $delay}]
+    }
+    perf_reset_clock 
+}
+
+proc ps_version { } {
+    set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
+    set mask_sil_ver "0x[expr {$si_ver >> 28}]"
+    return $mask_sil_ver;
+}
+
+proc ps7_post_config {} {
+    set saved_mode [configparams force-mem-accesses]                  
+    configparams force-mem-accesses 1 
+    
+	variable PCW_SILICON_VER_1_0
+    variable PCW_SILICON_VER_2_0
+    variable PCW_SILICON_VER_3_0
+    set sil_ver [ps_version]
+
+    if { $sil_ver == $PCW_SILICON_VER_1_0} {
+        ps7_post_config_1_0   
+    } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+        ps7_post_config_2_0   
+    } else {
+        ps7_post_config_3_0   
+    }
+	configparams force-mem-accesses $saved_mode                                       
+}
+
+proc ps7_debug {} {
+    variable PCW_SILICON_VER_1_0
+    variable PCW_SILICON_VER_2_0
+    variable PCW_SILICON_VER_3_0
+    set sil_ver [ps_version]
+
+    if { $sil_ver == $PCW_SILICON_VER_1_0} {
+        ps7_debug_1_0   
+    } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+        ps7_debug_2_0   
+    } else {
+        ps7_debug_3_0   
+    }
+}
+proc ps7_init {} {
+    variable PCW_SILICON_VER_1_0
+    variable PCW_SILICON_VER_2_0
+    variable PCW_SILICON_VER_3_0
+    set sil_ver [ps_version]
+    if { $sil_ver == $PCW_SILICON_VER_1_0} {
+            ps7_mio_init_data_1_0
+            ps7_pll_init_data_1_0
+            ps7_clock_init_data_1_0
+            ps7_ddr_init_data_1_0
+            ps7_peripherals_init_data_1_0
+            #puts "PCW Silicon Version : 1.0"
+    } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
+            ps7_mio_init_data_2_0
+            ps7_pll_init_data_2_0
+            ps7_clock_init_data_2_0
+            ps7_ddr_init_data_2_0
+            ps7_peripherals_init_data_2_0
+            #puts "PCW Silicon Version : 2.0"
+    } else {
+            ps7_mio_init_data_3_0
+            ps7_pll_init_data_3_0
+            ps7_clock_init_data_3_0
+            ps7_ddr_init_data_3_0
+            ps7_peripherals_init_data_3_0
+            #puts "PCW Silicon Version : 3.0"
+    }
+}
+
+
+# For delay calculation using global timer 
+
+# start timer 
+ proc perf_start_clock { } {
+
+    #writing SCU_GLOBAL_TIMER_CONTROL register
+
+    mask_write 0xF8F00208 0x00000109 0x00000009
+}
+
+# stop timer and reset timer count regs 
+ proc perf_reset_clock { } {
+	perf_disable_clock
+    mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
+    mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
+}
+
+# Compute mask for given delay in miliseconds
+proc get_number_of_cycles_for_delay { delay } {
+
+  # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+  variable APU_FREQ
+  return [ expr ($delay * $APU_FREQ /(2 * 1000))]
+}
+
+
+# stop timer 
+proc perf_disable_clock {} {
+    mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 
+}
+
+proc perf_reset_and_start_timer {} {
+  	    perf_reset_clock 
+	    perf_start_clock 
+}
+
+

Debug/ps7/start_amp_session.sh

@@ -0,0 +1,66 @@
+#!/bin/bash
+# --------------------------------------------------------------------------------
+# @Title: Bash script to start TRACE32 with AMP mode
+# @Description:
+#   Linux/MacOS bash script for a one-click start of the amp demo. It assumes
+#   TRACE32 is installed to /opt/t32, modify it to fit your needs.
+#   Usage USB:
+#     ./amp_demo_start_session0.sh
+#   Usage Ethernet:
+#     ./amp_demo_start_session0.sh <ip>
+#     ./amp_demo_start_session0.sh <dns-name>
+#   Other core(s) will be started by the t32_amp.cmm practice script.
+# @Props: NoWelcome NoMetaTags Template
+# @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
+# --------------------------------------------------------------------------------
+# $Id: amp_demo_start_session0.sh 10188 2016-11-18 08:23:44Z amerkle $
+
+
+# ppwd will be the absolute path to the current bash script
+export ppwd=$( cd $(dirname "$0") && pwd)
+
+USER_ID=`id -u`
+USER_ID_SUFFIX=${USER_ID:(-4)} 
+
+P1_PORT=$((10000+$USER_ID_SUFFIX))
+P2_TITLE=ARM_AMP_CORE0
+P3_TMP=/tmp
+P4_SYS=/tools/lauterbach/r_2018_02
+P9_TCF="$((20000+$USER_ID_SUFFIX))"
+
+if [[ ! ${1} ]]; then
+  echo "Please specify lauterbach hostname"
+  exit -1
+else
+  # Parameters for Ethernet connection
+  P5_PBI=NET
+  P6_OPT=NODE=${1}
+  P7_OPT=PACKLEN=1024
+  P8_OPT=CORE=1
+fi
+
+# Detect the system is 32bit or 64bit
+MACHINE='pc_linux'
+MACHINE_TYPE=`uname -m`
+if [ $MACHINE_TYPE == 'x86_64' ]; then
+  MACHINE='pc_linux64'
+fi
+
+if [ ! -x ${T32MARCH_EXE} ]; then
+  echo "t32marm-qt not found."
+  echo "Please check that P4_SYS is set to your TRACE32 system directory."
+  echo "(Current value: ${P4_SYS})"
+  pause
+  exit -1
+else
+  # set T32SYS environment variable
+  export T32SYS=${P4_SYS}
+fi
+
+cd ${ppwd}
+# Last but not least start TRACE32
+
+${T32SYS}/bin/${MACHINE}/t32marm-qt \
+    -graphicssystem raster \
+    -c "${ppwd}/config_amp.t32" ${P1_PORT} ${P2_TITLE} ${P3_TMP} ${P4_SYS} ${P5_PBI} ${P6_OPT} ${P7_OPT} ${P8_OPT} ${P9_TCF} 
+

Debug/ps7/ucos.men

@@ -0,0 +1,284 @@
+; --------------------------------------------------------------------------------
+; @Title: Menu File for TRACE32 uC/OS-II Awareness
+; @Description: -
+; @Keywords: ucos menu awareness
+; @Author: DIE
+; @Copyright: (C) 1989-2014 Lauterbach GmbH, licensed for use with TRACE32(R) only
+; --------------------------------------------------------------------------------
+; $Id: ucos.men 1958 2017-02-28 08:02:50Z rdienstbeck $
+
+add
+menu
+(
+  popup "&uC/OS"
+  (
+    if y.exist(T32OUT)
+    (
+        menuitem "&RTOS Terminal" "TERM T32OUT 0"
+        separator
+    )
+    default
+    menuitem "Display &Tasks"      "TASK.Task"
+    menuitem "Display &Events"     "TASK.Event"
+    menuitem "Display &Flags"      "TASK.Flag"
+    menuitem "Display &Timers"     "TASK.TImer"
+    menuitem "Display &Memory Partitions" "TASK.Memory"
+    if task.par.avail()==1
+    (
+        menuitem "Display &Space Partitions" "TASK.PARTition"
+    )
+    if task.proc.avail()==1
+    (
+        menuitem "Display &Processes" "TASK.PROCess"
+    )
+    separator
+    popup "&Stack Coverage"
+    (
+      menuitem "&List Stacks"
+      (
+        if !ice()
+            TASK.STacK.PATtern 0
+        TASK.STacK
+      )
+      menuitem "Add Task"        "TASK.STacK.ADD"
+      menuitem "Remove Task"     "TASK.STacK.ReMove"
+      enable ice()
+      menuitem "&Reset Coverage" "TASK.STacK.RESet"
+    )
+  )
+  popup "Trace"
+  (
+    popup "List"
+    (
+      separator
+      menuitem "&Task Switches"     "Trace.List List.TASK"
+      menuitem "&Default and Tasks" "Trace.List List.TASK DEFault"
+    )
+  )
+  popup "Perf"
+  (
+    separator
+    popup "&Task Runtime"
+    (
+      menuitem "&Prepare"
+      (
+        if t.method.analyzer()
+        (
+          Analyzer.AutoInit on
+        )
+        if (ice()||fire())&&!a.mode.flow()
+        (
+          Analyzer.ReProgram
+          (
+            Sample.Enable if AlphaBreak&&Write
+          )
+          Break.Delete /Alpha
+          Break.Set task.config(magic)++(task.config(magicsize)-1) /Alpha
+        )
+        if a.mode.flow()
+        (
+          Break.Delete /TraceEnable
+          Break.Set task.config(magic) /TraceEnable
+        )
+      )
+      menuitem "[:perf]Show &Numerical"   "Trace.STATistic.TASK"
+      menuitem "[:achart]Show as &Timing" "Trace.CHART.TASK"
+      menuitem "[:achart]Tracking with Trace &List"
+      (
+        Trace.List List.TASK DEFault /Track
+        Trace.CHART.TASK /Track
+      )
+    )
+    popup "Task &Function Runtime"
+    (
+      menuitem "&Prepare"
+      (
+        if t.method.analyzer()
+        (
+          Analyzer.AutoInit on
+          Analyzer.STATistic.PreFetch on
+        )
+
+        if (ice()||fire())&&!a.mode.flow()
+        (
+          if a.config.hac()
+          (
+             Analyzer.ReProgram
+             (
+               Sample.Enable if AlphaBreak
+               Sample.Enable if BetaBreak
+               Mark.A        if AlphaBreak
+               Mark.B        if BetaBreak
+             )
+          )
+          else
+          (
+             Analyzer.ReProgram
+             (
+               Sample.Enable if AlphaBreak||BetaBreak
+               Mark.A if AlphaBreak
+               Mark.B if BetaBreak
+             )
+          )
+          Break.Delete /Alpha /Beta /Charly
+          Break.SetFunc
+          Break.Set task.config(magic)++(task.config(magicsize)-1) /Alpha
+        )
+        if a.mode.flow()
+        (
+          Break.Delete /TraceData
+          Break.Set task.config(magic) /TraceData
+        )
+      )
+      menuitem "[:perf]Show &Numerical"     "Trace.STATistic.TASKFUNC"
+      menuitem "[:perf]Show as &Tree"       "Trace.STATistic.TASKTREE"
+      menuitem "[:perf]Show &Detailed Tree" "Trace.STATistic.TASKTREE ALL"
+      menuitem "[:achart]Show as &Timing"   "Trace.CHART.TASKFUNC"
+      menuitem "[:alist]Show N&esting"      "Trace.List List.TASK FUNC TI.FUNC"
+    )
+    popup "Task &Status"
+    (
+      menuitem "&Prepare"
+      (
+        if t.method.analyzer()
+        (
+          Analyzer.AutoInit on
+        )
+        if (ice()||fire())&&!a.mode.flow()
+        (
+          Analyzer.ReProgram
+          (
+            Sample.Enable if AlphaBreak&&Write
+          )
+          Break.Delete /Alpha
+          Break.Set task.config(magic)++(task.config(magicsize)-1) /Alpha
+          TASK.TASKState
+        )
+      )
+      menuitem "[:perf]Show &Numerical"   "Trace.STATistic.TASKSTATE"
+      menuitem "[:achart]Show as &Timing" "Trace.CHART.TASKSTATE"
+      menuitem "[:achart]Tracking with Trace &List"
+      (
+        Trace.List List.TASK DEFault /Track
+        Trace.CHART.TASKSTATE /Track
+      )
+    )
+  )
+  popup "&Help"
+  (
+    menuitem "<22>C/OS RTOS Debugger Manual" "HELP __RTOS_UCOS_"
+  )
+)
+
+
+menu "task.task"
+(
+  default
+  menuitem "Display Detailed"  "TASK.Task track.address()"
+  menuitem "Display TCB"
+  (
+    &address=address.offset(track.address())
+    &struct=task.struct(tcb)
+    Var.View %Open %String (&struct)*&address
+  )
+  separator
+  menuitem "Display Stack Frame"
+  (
+    &address=address.offset(track.address())
+    Var.Frame /Locals /Caller /Task &address
+  )
+  menuitem "Switch Context"       "Register.TASK address.offset(track.address())"
+  separator
+  menuitem "Add to Stack Cov"  "TASK.STK.ADD address.offset(track.address())"
+  menuitem "Rm from Stack Cov" "TASK.STK.RM  address.offset(track.address())"
+  separator
+  menuitem "Dump TCB"
+  (
+    &address=address.offset(track.address())
+    Data.dump &address
+  )
+)
+
+
+menu "task.event"
+(
+  default
+  menuitem "Display Detailed"  "TASK.Event track.address()"
+  menuitem "Display ECB"
+  (
+    &address=address.offset(track.address())
+    v.v %m (struct os_event*)&address
+  )
+  menuitem "Dump ECB"
+  (
+    &address=address.offset(track.address())
+    Data.dump &address
+  )
+)
+
+
+menu "task.e.q"
+(
+  menuitem "Display QCB"
+  (
+    &address=address.offset(track.address())
+    v.v %m (struct os_q*)&address
+  )
+  default
+  menuitem "Dump QCB"
+  (
+    &address=address.offset(track.address())
+    Data.dump &address
+  )
+)
+
+
+menu "task.flag"
+(
+  default
+  menuitem "Display Detailed"  "TASK.Flag track.address()"
+  menuitem "Display FCB"
+  (
+    &address=address.offset(track.address())
+    Var.View %m %s (struct os_flag_grp*)&address
+  )
+  menuitem "Dump FCB"
+  (
+    &address=address.offset(track.address())
+    Data.dump &address
+  )
+)
+
+
+menu "task.timer"
+(
+  default
+  menuitem "Display Detailed"  "TASK.TImer track.address()"
+  menuitem "Display Tmr CB"
+  (
+    &address=address.offset(track.address())
+    Var.View %m %s (struct os_tmr*)&address
+  )
+  menuitem "Dump Tmr CB"
+  (
+    &address=address.offset(track.address())
+    Data.dump &address
+  )
+)
+
+
+menu "task.par"
+(
+  default
+  menuitem "Display Detailed"  "TASK.PARtition track.address()"
+  menuitem "Display partition struct"
+  (
+    &address=address.offset(track.address())
+    Var.View %m %s (PAR_PARAM_T*)&address
+  )
+  menuitem "Dump partition struct"
+  (
+    &address=address.offset(track.address())
+    Data.dump &address
+  )
+)

Makefile

@@ -0,0 +1,104 @@
+ifeq ($(ARCH),psua53)
+CC = aarch64-elf-gcc
+AR = aarch64-elf-ar
+AS = aarch64-elf-as
+CP = aarch64-elf-objcopy
+OD = aarch64-elf-objdump
+SIZE = aarch64-elf-size
+else
+CC = arm-none-eabi-gcc
+AR = arm-none-eabi-ar
+AS = arm-none-eabi-as
+CP = arm-none-eabi-objcopy
+OD = arm-none-eabi-objdump
+SIZE = arm-none-eabi-size
+endif
+
+ifeq (, $(shell which ${CC}))
+$(error "No ${CC} in PATH variable, please extend PATH variable")
+endif
+
+SRC_DIR = ./src
+BUILD_DIR = ./Build
+DEBUG_DIR = ./Debug
+OUT_DIR = ./out
+
+TARGET := $(APP)_$(ARCH)_core$(CORE)
+TARGET_DIR := $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/
+
+OBJ_DIR = ./$(OUT_DIR)/$(TARGET)
+
+# Load specific config for compiler, linker, ...
+-include $(TARGET_DIR)/build/config.mk
+
+#Output files: elf, map and list-file
+EXECUTABLE=$(OBJ_DIR)/../$(TARGET).elf
+MAPFILE=$(OBJ_DIR)/../$(TARGET).map
+LISTFILE=$(OBJ_DIR)/../$(TARGET).lst
+
+# Path to linker script
+ifndef LDSCRIPT
+LDSCRIPT = -T$(TARGET_DIR)/linker/lscript.ld
+endif 
+
+#Include source-files: 
+SRC =
+-include $(TARGET_DIR)/build/Sources.mk
+
+INC = -I./
+-include $(TARGET_DIR)/build/includes.mk
+
+#  C source files
+CFILES = $(filter %.c, $(SRC))
+#  Assembly source files
+ASMFILES = $(filter %.s, $(SRC))
+# Object files
+COBJ = $(CFILES:$(SRC_DIR)/%.c=$(OBJ_DIR)/%.o)
+SOBJ = $(ASMFILES:$(SRC_DIR)/%.S=$(OBJ_DIR)/%.o)
+OBJ  = $(SOBJ) $(COBJ)
+
+$(info CFILES     : ${CFILES})
+
+# Flags
+CFLAGS  = $(MCFLAGS) $(DEBUG) $(OPTIMIZE) -MP -MMD -std=gnu11
+ASFLAGS = $(MCFLAGS) $(DEBUG) $(OPTIMIZE) -MP -MMD -x assembler-with-cpp
+ODFLAGS = --source --all-headers --demangle --line-numbers --wide
+
+all: info $(LISTFILE) postbuild
+
+$(LISTFILE): $(EXECUTABLE)
+	@echo 'Generating Listfile: $<'
+	@$(OD) $(ODFLAGS) -d $< > $@
+
+$(EXECUTABLE): $(OBJ)
+	@echo 'Linking: $@'
+	$(CD) $(CFLAGS) $(LDSCRIPT) -Wl,-Map,"$(MAPFILE)" -o "$@" $(sort $(OBJ))  $(LDFLAGS)
+
+$(COBJ): $(OBJ_DIR)/%.o: $(SRC_DIR)/%.c
+	@echo 'Building file: $<'
+	@mkdir -p $(@D)
+	$(CC) -c $(CFLAGS) $(INC) -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -o $@ $< >/dev/null
+
+$(SOBJ): $(OBJ_DIR)/%.o: $(SRC_DIR)/%.S
+	@echo 'Building file: $<'
+	@mkdir -p $(@D)
+	$(CC) -c $(ASFLAGS) $(INC) -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -o $@ $< >/dev/null
+
+.PHONY: clean, info
+
+info:
+	$(info APP         : ${APP})
+	$(info TARGET      : ${TARGET})
+	$(info TARGET_DIR  : ${TARGET_DIR})
+	$(info Linker file : ${LDSCRIPT})
+	$(info CFLAGS      : ${CFLAGS})
+	$(info ASFLAGS     : ${ASFLAGS})
+	$(info ODFLAGS     : ${ODFLAGS})
+	@echo ""
+	@echo ""
+	
+clean:
+	rm -rf $(OUT_DIR)
+	
+postbuild: $(EXECUTABLE)
+	$(SIZE) --format=berkeley $(EXECUTABLE)

README

@@ -0,0 +1,48 @@
+you have to specify three different variables for build
+APP: Your application/project. 
+ARCH: Selected Architecture
+CORE: Core Number
+
+example: make APP=myTestProject ARCH=psur5 CORE=0 all
+
+ARCH examples:
+	stm32f7: 	Cortex M7 on STM32F7 Disco Board
+	ps7:		Cortex A9 on Zynq 7000 (ZC706 Board)
+	psua53:		Cortex A53 on Zynq Ultrascale+ (ZCU102 Board)
+	psur5:		Cortex R5 on Zynq Ultrascale+ (ZCU102 Board)
+
+Naming convention and Folder Structure has to be preserved to ensure Makefile is working
+
+The folder structure is as follows:
+
+
+idaCom.git
+|--- Debug/
+|    |--- $(ARCH)							/* Architecture dependent debug config templates */
+|--- Makefile
+|--- README
+|--- src/
+|    |--- APP/
+|    |    |--- $(APP)/
+|    |         |--- $(ARCH)/
+|    |              |--- core$(CORE)/
+|    |                   |--- build/					/*Build configuration used by makefile (sources.mk, includes.mk, config.mk)
+|    |                   |    |--- sources.mk			/* List of source files */
+|    |                   |    |--- includes.mk       		/* List of include paths */
+|    |                   |    |--- config.mk         		/* Compiler/Linker flags */
+|    |                   |--- cfg/
+|    |                   |    |--- 	/* Typically used for various header files that are project specific */
+|    |                   |--- linker/
+|    |                   |    |--- 	/* Various Linker files */
+|    |                   |--- src/
+|    |                        |--- 	/* Various source files */
+|    |--- Modules/							/* This is a folder for external modules */
+|    |    |--- MMU/							/* Generic MMU Helper Module for Zynq 7000 and Ultrascale */
+|    |    |--- tlsf/							/* TLSF Malloc */
+|    |    |--- further git submodules
+|    |--- ucos_v1_42							/* ucos Sources by micrium */
+|    |--- Xilinx							/* Xilinx BSP for various projects */
+|--- out/ 								/* Generated compiler output, is removed during "make clean" */
+
+
+

README.md

@@ -1,3 +0,0 @@
-# sdes_student
-
-Lauterbach-Praktikum Studenten-Repo

src/APP/Aufgabe1/ps7/core0/build/config.mk

@@ -0,0 +1,11 @@
+#µController dependent flags
+MCFLAGS =-mcpu=cortex-a9 -march=armv7-a -mthumb -mthumb-interwork -mfloat-abi=softfp -mfpu=neon
+#Optimization
+OPTIMIZE=-O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections
+
+#Debug Level
+DEBUG   =-g3
+
+#Linker flags
+LDFLAGS  = -nostartfiles -Xlinker --gc-sections 
+

src/APP/Aufgabe1/ps7/core0/build/includes.mk

@@ -0,0 +1,28 @@
+
+INC += -I"$(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/cfg/"
+
+INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Ports/ARM-Cortex-A/Generic/GNU/"
+INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/ARM-Cortex-A/GNU/"
+INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/"
+INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-Common" 
+INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II" 
+INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Source" 
+INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-LIB" 
+
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/bsp/src/ipi"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/bsp/src/"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/bsp/src/$(ARCH)/"
+
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_cpu_cortexa9/src"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_scugic/src"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_l2cachec/src"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_uartps/src"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_emacps/src"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_scuc/src"
+
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/cortexa9/gcc"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/common"
+
+INC += -I"$(SRC_DIR)/Xilinx/libsrc/ipipsu_v2_3/src/" 
+INC += -I"$(SRC_DIR)/Modules/MMU" 
+

src/APP/Aufgabe1/ps7/core0/build/sources.mk

@@ -0,0 +1,38 @@
+#Startup file
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/bsp/src/$(ARCH)/asm_vectors.S
+-include $(SRC_DIR)/ucos_v1_42/ucos/bsp/src/$(ARCH)/subdir.mk
+-include $(SRC_DIR)/ucos_v1_42/ucos/bsp/src/subdir.mk
+
+-include $(SRC_DIR)/ucos_v1_42/micrium_source/uC-LIB/subdir.mk
+
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/components/ucos_osii/bsp/$(ARCH)/ucos_osii_bsp.c
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/components/ucos_common/src/$(ARCH)/cpu_bsp.c
+
+SRC += $(SRC_DIR)/Modules/MMU/mmu.c
+
+SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/main.c
+SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/app_hooks.c
+SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/uartps_cfg.c
+
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Ports/ARM-Cortex-A/Generic/GNU/os_cpu_a_vfp-none.S
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Ports/ARM-Cortex-A/Generic/GNU/os_cpu_c.c
+
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/Cache/ARM/armv7_generic_l1/GNU/cpu_cache_armv7_generic_l1_a.S
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/Cache/ARM/armv7_generic_l1/cpu_cache_armv7_generic_l1.c
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/ARM-Cortex-A/GNU/cpu_a.S
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/cpu_core.c
+
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_uartps/src/ucos_uartps.c
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_scutimer/src/ucos_scutimer.c
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_scugic/src/ucos_scugic.c
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_scuc/src/ucos_scuc.c
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_l2cachec/src/ucos_l2cachec.c
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_emacps/src/ucos_emacps.c
+
+-include $(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/cortexa9/subdir.mk
+
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-Common/KAL/uCOS-II/kal.c
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-Common/Collections/slist.c
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-Common/Auth/auth.c
+
+-include $(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Source/subdir.mk

src/APP/Aufgabe1/ps7/core0/cfg/app_cfg.h

@@ -0,0 +1,81 @@
+/*
+*********************************************************************************************************
+*
+*                                    MICRIUM BOARD SUPPORT PACKAGE
+*
+*                        (c) Copyright 2014-2015; Micrium, Inc.; Weston, FL
+*
+*               All rights reserved.  Protected by international copyright laws.
+*
+*               This BSP is provided in source form to registered licensees ONLY.  It is
+*               illegal to distribute this source code to any third party unless you receive
+*               written permission by an authorized Micrium representative.  Knowledge of
+*               the source code may NOT be used to develop a similar product.
+*
+*               Please help us continue to provide the Embedded community with the finest
+*               software available.  Your honesty is greatly appreciated.
+*
+*               You can contact us at www.micrium.com.
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                    MICRIUM BOARD SUPPORT PACKAGE
+*
+* Filename      : app_cfg.h
+* Version       : V1.42
+* Programmer(s) : JBL
+*********************************************************************************************************
+*/
+
+#ifndef  UCOS_APP_CFG_PRESENT
+#define  UCOS_APP_CFG_PRESENT
+
+#include  <lib_def.h>
+
+#include  <xparameters.h>
+
+#define  APP_CPU_ENABLED DEF_ENABLED
+
+#define  APP_LIB_ENABLED DEF_ENABLED
+
+#define  APP_COMMON_ENABLED DEF_ENABLED
+
+#define  APP_SHELL_ENABLED DEF_DISABLED
+
+#define  APP_CLK_ENABLED DEF_DISABLED
+
+#define  APP_OSIII_ENABLED DEF_DISABLED
+
+#define  APP_OSII_ENABLED  DEF_ENABLED
+
+#define  APP_TCPIP_ENABLED  DEF_DISABLED
+
+#define  APP_TCPIP_EXP_ENABLED  DEF_DISABLED
+
+#define  APP_DHCPC_ENABLED  DEF_DISABLED
+
+#define  APP_DNSC_ENABLED  DEF_DISABLED
+
+#define  APP_HTTPC_ENABLED  DEF_DISABLED
+
+#define  APP_MQTTC_ENABLED  DEF_DISABLED
+
+#define  APP_TELNETS_ENABLED  DEF_DISABLED
+
+#define  APP_IPERF_ENABLED  DEF_DISABLED
+
+#define  APP_FS_ENABLED  DEF_DISABLED
+
+#define  APP_USBD_ENABLED  DEF_DISABLED
+
+#define  APP_USBH_ENABLED  DEF_DISABLED
+
+#define  APP_OPENAMP_ENABLED  DEF_DISABLED
+
+#define OS_TASK_TMR_PRIO 3
+
+#endif /* #ifndef  UCOS_APP_CFG_PRESENT */
+

src/APP/Aufgabe1/ps7/core0/cfg/can_cfg.h

@@ -0,0 +1,202 @@
+/*
+*********************************************************************************************************
+*                                               uC/CAN
+*                                       The Embedded CAN suite
+*
+*                          (c) Copyright 2003-2014; Micrium, Inc.; Weston, FL
+*
+*               All rights reserved.  Protected by international copyright laws.
+*
+*               uC/CAN is provided in source form to registered licensees ONLY.  It is
+*               illegal to distribute this source code to any third party unless you receive
+*               written permission by an authorized Micrium representative.  Knowledge of
+*               the source code may NOT be used to develop a similar product.
+*
+*               Please help us continue to provide the Embedded community with the finest
+*               software available.  Your honesty is greatly appreciated.
+*
+*               You can contact us at www.micrium.com.
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                                        uC/CAN CONFIGURATION
+*
+*                                         ZYNQ ZC7000 Series
+*                                             CAN DRIVER
+* Filename      : can_cfg.h
+* Version       : V2.41.00
+* Programmer(s) : E0
+*                 DC
+*********************************************************************************************************
+*/
+
+#ifndef _CAN_CFG_H_
+#define _CAN_CFG_H_
+
+#include  "lib_def.h"
+
+
+/*
+*********************************************************************************************************
+*                                    COMMON DEFINES & ENUMERATIONS
+*********************************************************************************************************
+*/
+
+                                                                /* Definiton for CANSIG_GRANULARITY, Options:           */
+#define  CAN_CFG_BIT                            0u              /*      BIT                                             */
+#define  CAN_CFG_BYTE                           1u              /*      BYTE                                            */
+
+#ifndef  CAN_FALSE
+#define  CAN_FALSE                              0u
+#endif
+
+#ifndef  CAN_TRUE
+#define  CAN_TRUE                               1u
+#endif
+
+#ifndef  NULL_PTR
+#define  NULL_PTR                              (void *)0
+#endif
+      
+                                                                /* ------------ APPLICATION ENUMERATIONS -------------- */
+enum {
+   S_NODESTATUS = 0, 
+   S_CPULOAD, 
+   S_COUNTER, 
+   S_MAX,
+};
+
+enum {
+   M_STATUS = 0, 
+   M_COMMAND, 
+   M_MAX
+};
+
+
+/*
+*********************************************************************************************************
+*                                      MULTIPLE CAN CONTROLLERS
+*********************************************************************************************************
+*/
+
+#define  CAN_MODULE_CHANNEL_0                   DEF_ENABLED
+#define  CAN_MODULE_CHANNEL_1                   DEF_DISABLED
+
+
+/*
+*********************************************************************************************************
+*                                       DRIVER SPECIFIC DEFINES
+*********************************************************************************************************
+*/
+                                                                /* ---------------- BAUDRATE SETTINGS ----------------- */
+#define  CAN_DEFAULT_BAUDRATE             1000000u              /* Default Baudrate                                     */
+#define  CAN_DEFAULT_SP                       750u              /* Default Bit Sample Point in 1/10 %                   */
+#define  CAN_DEFAULT_RJW                      125u              /* Default Re-Synch Jump Width in 1/10 %                */
+
+                                                                /* ---------------- TIMEOUT SETTINGS ------------------ */
+#define  CAN_TIMEOUT_ERR_VAL               100000uL             /* Timeout Value for While Loop Error Checks            */
+
+
+/* ==================================  ADVANCED DRIVER CONFIGURATION: DEFAULT VALUES ================================== */
+/*  By Default, the following Driver specific settings for the ZYNQ ZC7xxx Driver are set to their default values       */
+/*  unless they are modified by customer needs.                                                                         */
+/*                                                                                                                      */
+/*  By Default, the Watermark level is configured to Maximum Watermark Value in the Driver, based on the reset value    */
+/*  presented by the Reference Manual. Redefine the following define to modify the Watermark Level for the following.   */
+/*      Tx FIFO Empty & Rx FIFO Full Watermark Level(s):                                                                */
+/*          NOTE : The VALID range is between 1 & 63.                                                                   */
+/*                                                                                                                      */
+/*          #define  CAN_WATERMARK_Rx_Tx_SIZE              63u                                                          */
+/*                                                                                                                      */
+/*  By Default, the Operating Mode of the CAN controller is configured to "NORMAL" Mode. For diagnostic checking,       */
+/*  additional operating modes have been included in the driver. Redefine the following define to modify the Operating  */
+/*  Mode to either "LOOP BACK" or "SNOOP" Mode(s).                                                                      */
+/*      NOTE that only one operating mode can be selected at once at Initialization. Once CAN has been Initialized it   */
+/*           is possible to change between Operating Modes at run-time using the xxx_CAN_IoCtl() API Function call.     */
+/*                                                                                                                      */
+/*          #define  CAN_DIAGNOSTIC_OFF                     0u                                                          */
+/*          #define  CAN_DIAGNOSTIC_LOOPBACK                1u                                                          */
+/*          #define  CAN_DIAGNOSTIC_SNOOP                   2u                                                          */
+/*                                                                                                                      */
+/*          #define  CAN_DIAGNOSTIC_SELECT                  CAN_DIAGNOSTIC_LOOPBACK                                     */
+/*                                                                                                                      */
+/* ==================================================================================================================== */
+
+
+/*
+*********************************************************************************************************
+*                                               CAN BUS
+*********************************************************************************************************
+*/
+
+#define  CANBUS_EN                              1u              /* Enable CAN Bus Management                            */
+#define  CANBUS_N                               3u              /*   Number of busses                                   */
+#define  CANBUS_ARG_CHK_EN                      1u              /*   Enable runtime argument checking                   */
+#define  CANBUS_TX_HANDLER_EN                   1u              /*   Enable usage of CanBusTxHandler                    */
+#define  CANBUS_RX_HANDLER_EN                   1u              /*   Enable usage of CanBusRxHandler                    */
+#define  CANBUS_NS_HANDLER_EN                   1u              /*   Enable usage of CanBusNsHandler                    */
+												  
+#define  CANBUS_STAT_EN                         1u              /*   Enable Bus Statistics                              */
+#define  CANBUS_TX_QSIZE                 (2u * CANBUS_N)        /*   Transmit Queue Size in CAN Frames for each CAN Bus */
+#define  CANBUS_RX_QSIZE                 (2u * CANBUS_N)        /*   Receive Queue Size in CAN Frames for each CAN Bus  */
+
+#define  CANBUS_HOOK_NS_EN                      1u              /*   Enable Node Status Handler Hook Function           */
+#define  CANBUS_HOOK_RX_EN                      1u              /*   Enable Rx Handler Hook Function                    */
+#define  CANBUS_RX_READ_ALWAYS_EN               1u              /*   If enabled the Rx Handler executes a read even..   */
+                                                                /*   .. when frames can't be allocated                  */
+
+
+/*
+*********************************************************************************************************
+*                                             CAN MESSAGE
+*********************************************************************************************************
+*/
+
+#define  CANMSG_EN                              1u              /* Enable CAN Message Support                           */
+#define  CANMSG_N                               2u              /*   Number of messages                                 */
+#define  CANMSG_ARG_CHK_EN                      1u              /*   Enable runtime argument checking                   */
+
+
+/*
+*********************************************************************************************************
+*                                             CAN SIGNAL
+*********************************************************************************************************
+*/
+
+#define  CANSIG_EN                              1u              /* Enable CAN Signal Database                           */
+#define  CANSIG_N                               3u              /*   Number of signals                                  */
+#define  CANSIG_ARG_CHK_EN                      1u              /*   Enable runtime argument checking                   */
+#define  CANSIG_MAX_WIDTH                       4u              /*   Maximal signal width in byte                       */
+#define  CANSIG_GRANULARITY               CAN_CFG_BYTE          /*   Set signal resolution to byte                      */
+#define  CANSIG_STATIC_CONFIG                   1u              /* To reduce memory usage, declare static signal table  */
+#define  CANSIG_USE_DELETE                      0u              /* To reduce memory usage don't use delete functions    */
+#define  CANSIG_CALLBACK_EN                     0u              /* Enable callback functions                            */
+
+
+/*
+*********************************************************************************************************
+*                                              CAN FRAME
+*********************************************************************************************************
+*/
+
+#define  CANFRM_ARG_CHK_EN                      1u              /* Enable runtime argument checking                     */
+
+
+/*
+*********************************************************************************************************
+*                                               CAN OS
+*********************************************************************************************************
+*/
+
+#define  CANOS_ARG_CHK_EN                       1u              /* Enable runtime argument checking                     */
+
+
+/*
+*********************************************************************************************************
+*                                          CONFIGURATION END
+*********************************************************************************************************
+*/
+
+#endif  /* #ifndef _CAN_CFG_H_ */

src/APP/Aufgabe1/ps7/core0/cfg/cpu_cfg.h

@@ -0,0 +1,216 @@
+/*
+*********************************************************************************************************
+*                                                uC/CPU
+*                                    CPU CONFIGURATION & PORT LAYER
+*
+*                          (c) Copyright 2004-2015; Micrium, Inc.; Weston, FL
+*
+*               All rights reserved.  Protected by international copyright laws.
+*
+*               uC/CPU is provided in source form to registered licensees ONLY.  It is 
+*               illegal to distribute this source code to any third party unless you receive 
+*               written permission by an authorized Micrium representative.  Knowledge of 
+*               the source code may NOT be used to develop a similar product.
+*
+*               Please help us continue to provide the Embedded community with the finest 
+*               software available.  Your honesty is greatly appreciated.
+*
+*               You can find our product's user manual, API reference, release notes and
+*               more information at https://doc.micrium.com.
+*               You can contact us at www.micrium.com.
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                       CPU CONFIGURATION FILE
+*
+*                                              TEMPLATE
+*
+* Filename      : cpu_cfg.h
+* Version       : V1.30.02
+* Programmer(s) : SR
+*                 ITJ
+*                 JBL
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                               MODULE
+*********************************************************************************************************
+*/
+
+#ifndef  CPU_CFG_MODULE_PRESENT
+#define  CPU_CFG_MODULE_PRESENT
+
+
+/*
+*********************************************************************************************************
+*                                       CPU NAME CONFIGURATION
+*
+* Note(s) : (1) Configure CPU_CFG_NAME_EN to enable/disable CPU host name feature :
+*
+*               (a) CPU host name storage
+*               (b) CPU host name API functions
+*
+*           (2) Configure CPU_CFG_NAME_SIZE with the desired ASCII string size of the CPU host name, 
+*               including the terminating NULL character.
+*
+*               See also 'cpu_core.h  GLOBAL VARIABLES  Note #1'.
+*********************************************************************************************************
+*/
+
+                                                                /* Configure CPU host name feature (see Note #1) :      */
+#define  CPU_CFG_NAME_EN                        DEF_DISABLED
+                                                                /*   DEF_DISABLED  CPU host name DISABLED               */
+                                                                /*   DEF_ENABLED   CPU host name ENABLED                */
+
+                                                                /* Configure CPU host name ASCII string size ...        */
+#define  CPU_CFG_NAME_SIZE                                16
+
+
+/*
+*********************************************************************************************************
+*                                     CPU TIMESTAMP CONFIGURATION
+*
+* Note(s) : (1) Configure CPU_CFG_TS_xx_EN to enable/disable CPU timestamp features :
+*
+*               (a) CPU_CFG_TS_32_EN   enable/disable 32-bit CPU timestamp feature
+*               (b) CPU_CFG_TS_64_EN   enable/disable 64-bit CPU timestamp feature
+*
+*           (2) (a) Configure CPU_CFG_TS_TMR_SIZE with the CPU timestamp timer's word size :
+*
+*                       CPU_WORD_SIZE_08         8-bit word size
+*                       CPU_WORD_SIZE_16        16-bit word size
+*                       CPU_WORD_SIZE_32        32-bit word size
+*                       CPU_WORD_SIZE_64        64-bit word size
+*
+*               (b) If the size of the CPU timestamp timer is not a binary multiple of 8-bit octets 
+*                   (e.g. 20-bits or even 24-bits), then the next lower, binary-multiple octet word 
+*                   size SHOULD be configured (e.g. to 16-bits).  However, the minimum supported word 
+*                   size for CPU timestamp timers is 8-bits.
+*
+*                   See also 'cpu_core.h  FUNCTION PROTOTYPES  CPU_TS_TmrRd()  Note #2a'.
+*********************************************************************************************************
+*/
+
+                                                                /* Configure CPU timestamp features (see Note #1) :     */
+#define  CPU_CFG_TS_32_EN                       DEF_ENABLED
+#define  CPU_CFG_TS_64_EN                       DEF_ENABLED
+                                                                /*   DEF_DISABLED  CPU timestamps DISABLED              */
+                                                                /*   DEF_ENABLED   CPU timestamps ENABLED               */
+
+                                                                /* Configure CPU timestamp timer word size ...          */
+                                                                /* ... (see Note #2) :                                  */
+#define  CPU_CFG_TS_TMR_SIZE                    CPU_WORD_SIZE_64
+
+
+/*
+*********************************************************************************************************
+*                        CPU INTERRUPTS DISABLED TIME MEASUREMENT CONFIGURATION
+*
+* Note(s) : (1) (a) Configure CPU_CFG_INT_DIS_MEAS_EN to enable/disable measuring CPU's interrupts 
+*                   disabled time :
+*
+*                   (a)  Enabled,       if CPU_CFG_INT_DIS_MEAS_EN      #define'd in 'cpu_cfg.h'
+*
+*                   (b) Disabled,       if CPU_CFG_INT_DIS_MEAS_EN  NOT #define'd in 'cpu_cfg.h'
+*
+*                   See also 'cpu_core.h  FUNCTION PROTOTYPES  Note #1'.
+*
+*               (b) Configure CPU_CFG_INT_DIS_MEAS_OVRHD_NBR with the number of times to measure & 
+*                   average the interrupts disabled time measurements overhead.
+*
+*                   See also 'cpu_core.c  CPU_IntDisMeasInit()  Note #3a'.
+*********************************************************************************************************
+*/
+
+#if 0                                                           /* Configure CPU interrupts disabled time ...           */
+#define  CPU_CFG_INT_DIS_MEAS_EN                                /* ... measurements feature (see Note #1a).             */
+#endif
+
+                                                                /* Configure number of interrupts disabled overhead ... */
+#define  CPU_CFG_INT_DIS_MEAS_OVRHD_NBR                    1u   /* ... time measurements (see Note #1b).                */
+
+
+/*
+*********************************************************************************************************
+*                                    CPU COUNT ZEROS CONFIGURATION
+*
+* Note(s) : (1) (a) Configure CPU_CFG_LEAD_ZEROS_ASM_PRESENT  to define count leading  zeros bits 
+*                   function(s) in :
+*
+*                   (1) 'cpu_a.asm',  if CPU_CFG_LEAD_ZEROS_ASM_PRESENT       #define'd in 'cpu.h'/
+*                                         'cpu_cfg.h' to enable assembly-optimized function(s)
+*
+*                   (2) 'cpu_core.c', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT   NOT #define'd in 'cpu.h'/
+*                                         'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
+*
+*               (b) Configure CPU_CFG_TRAIL_ZEROS_ASM_PRESENT to define count trailing zeros bits 
+*                   function(s) in :
+*
+*                   (1) 'cpu_a.asm',  if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT      #define'd in 'cpu.h'/
+*                                         'cpu_cfg.h' to enable assembly-optimized function(s)
+*
+*                   (2) 'cpu_core.c', if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT  NOT #define'd in 'cpu.h'/
+*                                         'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
+*********************************************************************************************************
+*/
+
+#if 0                                                           /* Configure CPU count leading  zeros bits ...          */
+#define  CPU_CFG_LEAD_ZEROS_ASM_PRESENT                         /* ... assembly-version (see Note #1a).                 */
+#endif
+
+#if 0                                                           /* Configure CPU count trailing zeros bits ...          */
+#define  CPU_CFG_TRAIL_ZEROS_ASM_PRESENT                        /* ... assembly-version (see Note #1b).                 */
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                      CPU ENDIAN TYPE OVERRIDE
+*
+* Note(s) : (1) Configure CPU_CFG_ENDIAN_TYPE to override the default CPU endian type defined in cpu.h.
+*
+*               (a) CPU_ENDIAN_TYPE_BIG         Big-   endian word order (CPU words' most  significant
+*                                                                         octet @ lowest memory address)
+*               (b) CPU_ENDIAN_TYPE_LITTLE      Little-endian word order (CPU words' least significant
+*                                                                         octet @ lowest memory address)
+*
+*           (2) Defining CPU_CFG_ENDIAN_TYPE here is only valid for supported bi-endian architectures.
+*               See  'cpu.h  CPU WORD CONFIGURATION  Note #3' for details
+*********************************************************************************************************
+*/
+
+#if 0
+#define  CPU_CFG_ENDIAN_TYPE            CPU_ENDIAN_TYPE_BIG     /* Defines CPU data    word-memory order (see Note #2). */
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                          CACHE MANAGEMENT
+*
+* Note(s) : (1) Configure CPU_CFG_CACHE_MGMT_EN to enable the cache managment API.
+
+*
+*           (2) Defining CPU_CFG_CACHE_MGMT_EN to DEF_ENABLED only enable the cache management function.
+*               Cache are assumed to be configured and enabled by the time CPU_init() is called.
+*********************************************************************************************************
+*/
+
+#define  CPU_CFG_CACHE_MGMT_EN            DEF_DISABLED
+
+
+/*
+*********************************************************************************************************
+*                                             MODULE END
+*********************************************************************************************************
+*/
+
+#endif                                                          /* End of CPU cfg module include.                       */
+
+#define  CPU_CACHE_CFG_L2C310_BASE_ADDR  0xF8F02000

src/APP/Aufgabe1/ps7/core0/cfg/dhcp-c_cfg.h

@@ -0,0 +1,146 @@
+/*
+*********************************************************************************************************
+*                                               uC/DHCPc
+*                              Dynamic Host Configuration Protocol Client
+*
+*                         (c) Copyright 2004-2014; Micrium, Inc.; Weston, FL
+*
+*                  All rights reserved.  Protected by international copyright laws.
+*
+*                  uC/DHCP is provided in source form to registered licensees ONLY.  It is
+*                  illegal to distribute this source code to any third party unless you receive
+*                  written permission by an authorized Micrium representative.  Knowledge of
+*                  the source code may NOT be used to develop a similar product.
+*
+*                  Please help us continue to provide the Embedded community with the finest
+*                  software available.  Your honesty is greatly appreciated.
+*
+*                  You can find our product's user manual, API reference, release notes and
+*                  more information at: https://doc.micrium.com
+*
+*                  You can contact us at: http://www.micrium.com
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                   DHCP CLIENT CONFIGURATION FILE
+*
+*                                              TEMPLATE
+*
+* Filename      : dhcp-c_cfg.h
+* Version       : V2.10.00
+* Programmer(s) : SR
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                           TASKS PRIORITIES
+* Notes: (1) Task priorities configuration values should be used by the DHCPc OS port. The following task priorities
+*            should be defined:
+*
+*                   DHCPc_OS_CFG_TASK_PRIO
+*                   DHCPc_OS_CFG_TMR_TASK_PRIO
+*
+*            Task priorities can be defined either in this configuration file 'dhcp-c_cfg.h' or in a global
+*            OS tasks priorities configuration header file which must be included in 'dhcp-c_cfg.h'.
+*********************************************************************************************************
+*/
+
+                                                                /* See Note #1.                                         */
+#define  DHCPc_OS_CFG_TASK_PRIO                           13
+#define  DHCPc_OS_CFG_TMR_TASK_PRIO                       14
+
+
+/*
+*********************************************************************************************************
+*                                              STACK SIZES
+*            Size (depth) of the task stacks (See the definition of CPU_STK for stack width)
+*********************************************************************************************************
+*/
+
+#define  DHCPc_OS_CFG_TASK_STK_SIZE                      512
+#define  DHCPc_OS_CFG_TMR_TASK_STK_SIZE 256
+
+
+/*
+*********************************************************************************************************
+*                                                 DHCPc
+*
+* Note(s) : (1) Default port for DHCP server is 67, and default port for DHCP client is 68.
+*
+*           (3) Configure DHCPc_CFG_MAX_NBR_IF to the maximum number of interface this DHCP client will
+*               be able to manage at a given time.
+*
+*           (4) Once the DHCP server has assigned the client an address, the later may perform a final
+*               check prior to use this address in order to make sure it is not being used by another
+*               host on the network.
+*********************************************************************************************************
+*/
+
+#define  DHCPc_CFG_IP_PORT_SERVER                         67
+#define  DHCPc_CFG_IP_PORT_CLIENT                         68
+
+#define  DHCPc_CFG_MAX_RX_TIMEOUT_MS                    1000
+
+#define  DHCPc_CFG_PARAM_REQ_TBL_SIZE                      5
+
+#define  DHCPc_CFG_MAX_NBR_IF                              1
+
+#define  DHCPc_CFG_ADDR_VALIDATE_EN              DEF_ENABLED
+                                                                /* ... (see Note #4) :                                  */
+                                                                /*   DEF_DISABLED  Validation NOT performed             */
+                                                                /*   DEF_ENABLED   Validation     performed             */
+
+#define  DHCPc_CFG_DYN_LOCAL_LINK_ADDR_EN        DEF_ENABLED
+                                                                /*   DEF_DISABLED  local-link configuration DISABLED    */
+                                                                /*   DEF_ENABLED   local-link configuration ENABLED     */
+
+#define  DHCPc_CFG_LOCAL_LINK_MAX_RETRY                    3
+                                                                /* link-local address.                                  */
+
+
+/*
+*********************************************************************************************************
+*                                 DHCPc ARGUMENT CHECK CONFIGURATION
+*
+* Note(s) : (1) Configure DHCPc_CFG_ARG_CHK_EXT_EN to enable/disable the DHCP client external argument
+*               check feature :
+*
+*               (a) When ENABLED,  ALL arguments received from any port interface provided by the developer
+*                   or application are checked/validated.
+*
+*               (b) When DISABLED, NO  arguments received from any port interface provided by the developer
+*                   or application are checked/validated.
+*
+*           (2) Configure DHCPc_CFG_ARG_CHK_DBG_EN to enable/disable the DHCP client internal debug
+*               argument check feature :
+*
+*               (a) When ENABLED,     internal arguments are checked/validated to debug the DHCP client.
+*
+*               (b) When DISABLED, NO internal arguments are checked/validated to debug the DHCP client.
+*
+*           (3) Configure DHCPc_DBG_CFG_MEM_CLR_EN to enable/disable the DHCP client from clearing
+*               internal data structure memory buffers; a convenient feature while debugging.
+*********************************************************************************************************
+*/
+                                                                /* Configure external argument check feature ...        */
+                                                                /* ... (see Note #1) :                                  */
+#define  DHCPc_CFG_ARG_CHK_EXT_EN                DEF_ENABLED
+                                                                /*   DEF_DISABLED     Argument check DISABLED           */
+                                                                /*   DEF_ENABLED      Argument check ENABLED            */
+
+                                                                /* Configure internal argument check feature ...        */
+                                                                /* ... (see Note #2) :                                  */
+#define  DHCPc_CFG_ARG_CHK_DBG_EN                DEF_DISABLED
+                                                                /*   DEF_DISABLED     Argument check DISABLED           */
+                                                                /*   DEF_ENABLED      Argument check ENABLED            */
+
+                                                                /* Configure memory clear feature  (see Note #3) :      */
+#define  DHCPc_DBG_CFG_MEM_CLR_EN                DEF_DISABLED
+                                                                /*   DEF_DISABLED     Data structure clears DISABLED    */
+                                                                /*   DEF_ENABLED      Data structure clears ENABLED     */
+

src/APP/Aufgabe1/ps7/core0/cfg/dns-c_cfg.h

@@ -0,0 +1,111 @@
+/*
+*********************************************************************************************************
+*                                               uC/DNSc
+*                                     Domain Name Server (client)
+*
+*                         (c) Copyright 2004-2014; Micrium, Inc.; Weston, FL
+*
+*                  All rights reserved.  Protected by international copyright laws.
+*
+*                  uC/DNSc is provided in source form to registered licensees ONLY.  It is
+*                  illegal to distribute this source code to any third party unless you receive
+*                  written permission by an authorized Micrium representative.  Knowledge of
+*                  the source code may NOT be used to develop a similar product.
+*
+*                  Please help us continue to provide the Embedded community with the finest
+*                  software available.  Your honesty is greatly appreciated.
+*
+*                  You can find our product's user manual, API reference, release notes and
+*                  more information at: https://doc.micrium.com
+*
+*                  You can contact us at: http://www.micrium.com
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                    DNS CLIENT CONFIGURATION FILE
+*
+*                                              TEMPLATE
+*
+* Filename      : dns-c_cfg.h
+* Version       : V2.00.01
+* Programmer(s) : AA
+*********************************************************************************************************
+*/
+
+#ifndef DNSc_CFG_MODULE_PRESENT
+#define DNSc_CFG_MODULE_PRESENT
+
+#include  <Source/dns-c_type.h>
+
+
+/*
+*********************************************************************************************************
+*                                  DNSc ARGUMENT CHECK CONFIGURATION
+*
+* Note(s) : (1) Configure DNSc_CFG_ARG_CHK_EXT_EN to enable/disable the DNS client external argument
+*               check feature :
+*
+*               (a) When ENABLED,  ALL arguments received from any port interface provided by the developer
+*                   are checked/validated.
+*
+*               (b) When DISABLED, NO  arguments received from any port interface provided by the developer
+*                   are checked/validated.
+*********************************************************************************************************
+*/
+                                                                /* Configure external argument check feature ...        */
+                                                                /* See Note 1.                                          */
+#define  DNSc_CFG_ARG_CHK_EXT_EN                    DEF_DISABLED
+                                                                /* DEF_DISABLED     External argument check DISABLED    */
+                                                                /* DEF_ENABLED      External argument check ENABLED     */
+
+/*
+*********************************************************************************************************
+*                                     DNSc FEATURES CONFIGURATION
+*
+* Note(s) : (1) Configure DNSc_CFG_MODE_ASYNC_EN to enable/disable the DNS client asynchronous communication mode:
+*
+*               (a) When ENABLED,  A dedicated task will handle all host resolution request. It will be possible to
+*                   call DNS API to get remote host address without blocking.
+*
+*               (b) When DISABLED, The API to get remote host will always block until the resolution is completed.
+*
+*           (2) Configure DNSc_CFG_MODE_BLOCK_EN to enable/disable the blocking option when the asynchronous
+*               communication is enabled.
+*
+*               (a) When ENABLED,  It will be possible to block when calling the DNS API to get remote host until the
+*                   resolution is completed (via a flag option).
+*
+*               (b) When DISABLED, The API to get remote host will always be non-blocking, must poll DNS client to
+*                   know when the resolution is completed.
+*********************************************************************************************************
+*/
+
+                                                                /* Configure asynchronous mode feature, See Note #1 ... */
+#define  DNSc_CFG_MODE_ASYNC_EN                     DEF_DISABLED
+                                                                /* DEF_DISABLED     Asynchronous mode DISABLED          */
+                                                                /* DEF_ENABLED      Asynchronous mode ENABLED           */
+
+
+                                                                /* Configure blocking option feature, See Note #2 ... */
+#define  DNSc_CFG_MODE_BLOCK_EN                     DEF_DISABLED
+                                                                /* DEF_DISABLED     Blocking option DISABLED            */
+                                                                /* DEF_ENABLED      Blocking option ENABLED             */
+
+/*
+*********************************************************************************************************
+*                                DNSc RUN-TIME STRUCTURE CONFIGURATION
+*
+* Note(s) : (1) These structures should be defined into a 'C' file.
+*********************************************************************************************************
+*/
+
+extern  const  DNSc_CFG       DNSc_Cfg;                         /* Must always be defined.                              */
+
+#if (DNSc_CFG_MODE_ASYNC_EN == DEF_ENABLED)
+extern  const  DNSc_CFG_TASK  DNSc_CfgTask;                     /* Not required when Asynchronous mode is disabled.     */
+#endif
+
+#endif

src/APP/Aufgabe1/ps7/core0/cfg/http-c_cfg.h

@@ -0,0 +1,224 @@
+/*
+*********************************************************************************************************
+*                                               uC/HTTP
+*                                      Hypertext Transfer Protocol
+*
+*                         (c) Copyright 2004-2015; Micrium, Inc.; Weston, FL
+*
+*                  All rights reserved.  Protected by international copyright laws.
+*
+*                  uC/HTTP is provided in source form to registered licensees ONLY.  It is
+*                  illegal to distribute this source code to any third party unless you receive
+*                  written permission by an authorized Micrium representative.  Knowledge of
+*                  the source code may NOT be used to develop a similar product.
+*
+*                  Please help us continue to provide the Embedded community with the finest
+*                  software available.  Your honesty is greatly appreciated.
+*
+*                  You can find our product's user manual, API reference, release notes and
+*                  more information at: https://doc.micrium.com
+*
+*                  You can contact us at: http://www.micrium.com
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                   HTTP CLIENT CONFIGURATION FILE
+*
+*                                              TEMPLATE
+*
+* Filename      : http-c_cfg.h
+* Version       : V3.00.01
+* Programmer(s) : MM
+*                 AL
+*********************************************************************************************************
+* Note(s)       : (1) Assumes the following versions (or more recent) of software modules are included in
+*                     the project build :
+*
+*                       (a) uC/CPU    V1.29.02
+*                       (b) uC/LIB    V1.38.00
+*                       (c) uC/Common V1.00.00
+*                       (d) uC/TCP-IP V3.03.00
+*
+*
+*                 (2) For additional details on the features available with uC/HTTPc, the API, the
+*                     installation, etc. Please refer to the uC/HTTPc documentation available at
+*                     https://doc.micrium.com/HTTPc.
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                           INCLUDE FILES
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#include  <Common/http.h>
+#include  <Client/Source/http-c_type.h>
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                               MODULE
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#ifndef  HTTPc_CFG_MODULE_PRESENT
+#define  HTTPc_CFG_MODULE_PRESENT
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                      COMPILE-TIME CONFIGURATION
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                                   HTTP ARGUMENT CHECK CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_ARG_CHK_EXT_EN to enable/disable the HTTP client external argument
+*               check feature :
+*
+*               (a) When ENABLED,  ALL arguments received from any port interface provided by the developer
+*                   are checked/validated.
+*
+*               (b) When DISABLED, NO  arguments received from any port interface provided by the developer
+*                   are checked/validated.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_ARG_CHK_EXT_EN                 DEF_ENABLED
+
+
+/*
+*********************************************************************************************************
+*                                    HTTP CLIENT TASK CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_MODE_ASYNC_TASK_EN to enable/disable HTTP client task.
+*               (a) DEF_DISABLED : No HTTP client task will be created to process the HTTP requests.
+*                                  The Blocking HTTPc API will be enabled.
+*
+*               (b) DEF_ENABLED  : An HTTP client task will be created to process all the HTTP requests.
+*                                  The Non-Blocking HTTPc API will be enabled. Therefore, multiple
+*                                  connections can be handle by the task simultaneously.
+*
+*           (2) Configure HTTPc_CFG_MODE_BLOCK_EN to enable/disable the blocking option when the
+*               asynchronous HTTPc Task is enabled.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_MODE_ASYNC_TASK_EN           DEF_DISABLED
+
+#define  HTTPc_CFG_MODE_BLOCK_EN                DEF_ENABLED
+
+
+/*
+*********************************************************************************************************
+*                              HTTP CLIENT PERSISTENT CONNECTION CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_PERSISTENT_EN to enable/disable Persistent Connection support.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_PERSISTENT_EN                DEF_ENABLED
+
+
+/*
+*********************************************************************************************************
+*                                HTTP CLIENT CHUNKED TRANSFER CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_CHUNK_TX_EN to enable/disable Chunked Transfer support in Transmission.
+*
+*           (2) Chunked Transfer in Reception is always enabled.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_CHUNK_TX_EN                  DEF_ENABLED
+
+
+/*
+*********************************************************************************************************
+*                                 HTTP CLIENT QUERY STRING CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_QUERY_STR_EN to enable/disable Query String support in URL.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_QUERY_STR_EN                 DEF_ENABLED
+
+
+/*
+*********************************************************************************************************
+*                                HTTP CLIENT HEADER FIELD CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_HDR_RX_EN to enable/disable header field processing in reception
+*               (i.e for headers received in the HTTP response.
+*
+*           (2) Configure HTTPc_CFG_HDR_TX_EN to enable/disable header field processing in transmission
+*               (i.e for headers to include in the HTTP request.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_HDR_RX_EN                    DEF_ENABLED
+
+
+#define  HTTPc_CFG_HDR_TX_EN                    DEF_ENABLED
+
+
+/*
+*********************************************************************************************************
+*                                     HTTP CLIENT FORM CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_FORM_EN to enable/disable HTTP form creation source code.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_FORM_EN                      DEF_ENABLED
+
+
+/*
+*********************************************************************************************************
+*                                   HTTP CLIENT USER DATA CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_USER_DATA_EN         to enable/disable user data pointer in HTTPc_CONN
+*                                                        and HTTPc_REQ structure.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_USER_DATA_EN                 DEF_ENABLED
+
+
+/*
+*********************************************************************************************************
+*                                   HTTP CLIENT WEBSOCKET CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_WEBSOCKET_EN        to enable/disable the Websocket feature.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_WEBSOCKET_EN                 DEF_DISABLED
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                      RUN-TIME CONFIGURATION
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+extern  const  HTTP_TASK_CFG   HTTPc_TaskCfg;
+extern  const  HTTPc_CFG       HTTPc_Cfg;
+
+
+/* =============================================== END =============================================== */
+#endif  /* HTTPc_CFG_MODULE_PRESENT */

src/APP/Aufgabe1/ps7/core0/cfg/lib_cfg.h

@@ -0,0 +1,171 @@
+/*
+*********************************************************************************************************
+*                                            EXAMPLE CODE
+*
+*               This file is provided as an example on how to use Micrium products.
+*
+*               Please feel free to use any application code labeled as 'EXAMPLE CODE' in
+*               your application products.  Example code may be used as is, in whole or in
+*               part, or may be used as a reference only. This file can be modified as
+*               required to meet the end-product requirements.
+*
+*               Please help us continue to provide the Embedded community with the finest
+*               software available.  Your honesty is greatly appreciated.
+*
+*               You can find information about uC/LIB by visiting doc.micrium.com.
+*               You can contact us at: http://www.micrium.com
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                  CUSTOM LIBRARY CONFIGURATION FILE
+*
+*                                              TEMPLATE
+*
+* Filename      : lib_cfg.h
+* Version       : V1.38.01.00
+* Programmer(s) : FBJ
+*                 JFD
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                               MODULE
+*********************************************************************************************************
+*/
+
+#ifndef  LIB_CFG_MODULE_PRESENT
+#define  LIB_CFG_MODULE_PRESENT
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                    MEMORY LIBRARY CONFIGURATION
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                             MEMORY LIBRARY ARGUMENT CHECK CONFIGURATION
+*
+* Note(s) : (1) Configure LIB_MEM_CFG_ARG_CHK_EXT_EN to enable/disable the memory library suite external
+*               argument check feature :
+*
+*               (a) When ENABLED,     arguments received from any port interface provided by the developer
+*                   or application are checked/validated.
+*
+*               (b) When DISABLED, NO arguments received from any port interface provided by the developer
+*                   or application are checked/validated.
+*********************************************************************************************************
+*/
+
+                                                                /* External argument check.                             */
+                                                                /* Indicates if arguments received from any port ...    */
+                                                                /* ... interface provided by the developer or ...       */
+                                                                /* ... application are checked/validated.               */
+#define  LIB_MEM_CFG_ARG_CHK_EXT_EN     DEF_DISABLED
+
+
+/*
+*********************************************************************************************************
+*                         MEMORY LIBRARY ASSEMBLY OPTIMIZATION CONFIGURATION
+*
+* Note(s) : (1) Configure LIB_MEM_CFG_OPTIMIZE_ASM_EN to enable/disable assembly-optimized memory function(s).
+*********************************************************************************************************
+*/
+
+                                                                /* Assembly-optimized function(s).                      */
+                                                                /* Enable/disable assembly-optimized memory ...         */
+                                                                /* ... function(s). [see Note #1]                       */
+#define  LIB_MEM_CFG_OPTIMIZE_ASM_EN    DEF_DISABLED
+
+
+/*
+*********************************************************************************************************
+*                                   MEMORY ALLOCATION CONFIGURATION
+*
+* Note(s) : (1) Configure LIB_MEM_CFG_DBG_INFO_EN to enable/disable memory allocation usage tracking
+*               that associates a name with each segment or dynamic pool allocated.
+*
+*           (2) (a) Configure LIB_MEM_CFG_HEAP_SIZE with the desired size of heap memory (in octets).
+*
+*               (b) Configure LIB_MEM_CFG_HEAP_BASE_ADDR to specify a base address for heap memory :
+*
+*                   (1) Heap initialized to specified application memory, if LIB_MEM_CFG_HEAP_BASE_ADDR
+*                                                                                #define'd in 'lib_cfg.h';
+*                                                                         CANNOT #define to address 0x0
+*
+*                   (2) Heap declared to Mem_Heap[] in 'lib_mem.c',       if LIB_MEM_CFG_HEAP_BASE_ADDR
+*                                                                            NOT #define'd in 'lib_cfg.h'
+*********************************************************************************************************
+*/
+
+                                                                /* Allocation debugging information.                    */
+                                                                /* Enable/disable allocation of debug information ...   */
+                                                                /* ... associated to each memory allocation.            */
+#define  LIB_MEM_CFG_DBG_INFO_EN        DEF_DISABLED
+
+
+                                                                /* Heap memory size (in bytes).                         */
+                                                                /* Configure the desired size of the heap memory. ...   */
+                                                                /* ... Set to 0 to disable heap allocation features.    */
+#define  LIB_MEM_CFG_HEAP_SIZE                  64*1024
+
+
+                                                                /* Heap memory padding alignment (in bytes).            */
+                                                                /* Configure the desired size of padding alignment ...  */
+                                                                /* ... of each buffer allocated from the heap.          */
+#define  LIB_MEM_CFG_HEAP_PADDING_ALIGN    LIB_MEM_PADDING_ALIGN_NONE
+
+#if 0                                                           /* Remove this to have heap alloc at specified addr.    */
+#define  LIB_MEM_CFG_HEAP_BASE_ADDR       0
+#endif
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                    STRING LIBRARY CONFIGURATION
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                                 STRING FLOATING POINT CONFIGURATION
+*
+* Note(s) : (1) Configure LIB_STR_CFG_FP_EN to enable/disable floating point string function(s).
+*
+*           (2) Configure LIB_STR_CFG_FP_MAX_NBR_DIG_SIG to configure the maximum number of significant
+*               digits to calculate &/or display for floating point string function(s).
+*
+*               See also 'lib_str.h  STRING FLOATING POINT DEFINES  Note #1'.
+*********************************************************************************************************
+*/
+
+                                                                /* Floating point feature(s).                           */
+                                                                /* Enable/disable floating point to string functions.   */
+#define  LIB_STR_CFG_FP_EN                      DEF_DISABLED
+
+
+                                                                /* Floating point number of significant digits.         */
+                                                                /* Configure the maximum number of significant ...      */
+                                                                /* ... digits to calculate &/or display for ...         */
+                                                                /* ... floating point string function(s).               */
+#define  LIB_STR_CFG_FP_MAX_NBR_DIG_SIG         LIB_STR_FP_MAX_NBR_DIG_SIG_DFLT
+
+
+/*
+*********************************************************************************************************
+*                                             MODULE END
+*********************************************************************************************************
+*/
+
+#endif                                                          /* End of lib cfg module include.                       */
+

src/APP/Aufgabe1/ps7/core0/cfg/mmu_cfg.h

@@ -0,0 +1,42 @@
+/*
+ * mmu_cfg.h
+ *
+ *  Created on: 25.04.2018
+ *      Author: kaige
+ */
+
+#ifndef SRC_APP_LWIPREWORK_PS7_CORE0_CFG_MMU_CFG_H_
+#define SRC_APP_LWIPREWORK_PS7_CORE0_CFG_MMU_CFG_H_
+
+#include "mmu.h"
+
+/*------------------------------------------------------------------------------------------------*/
+/*!
+* \brief    FIRST LEVEL TRANSLATION TABLE (FTT)
+*
+* \ingroup  PAR_CPU_MMU
+*
+*           This variable represents the first level translation table. Each entry within
+*           the table represents the configuration of a 1MB memory segment. If a memory
+*           portion below 1MB must be accessed, the entry represents a pointer to the
+*           linked coarse page table, which contains the information of that 1MB in detail.
+*
+* \note     This table MUST be aligned at 16kB boundary.
+*/
+/*------------------------------------------------------------------------------------------------*/
+
+const PAR_MEM_REGION_T PARMemTbl_Core[]  = {
+/*   +-------------------------------------------------------------------------------------------+
+*    | virtual   | physical  |     size      |   owner          |  permissions    |    HID Field |
+*    +-----------+-----------+---------------+------------------+-----------------+--------------+*/
+	// First 1MB is marked as non-cacheable/non-bufferable (contains 3x 64KB SRAM @ address 0x00000000
+	{ 0x00000000, 0x00000000, MMU_SIZE_1MB,   PAR_AP_PRW__URW_, PAR_HID_TEX_CB_CACHED_MEMORY | PAR_HID_CACHE_INNER_CB | PAR_HID_CACHE_OUTER_CB },
+    // DDR Memory is marked as normal (only 512MB for now)
+	{ 0x00100000, 0x00100000, MMU_SIZE_16MB, PAR_AP_PRW__URW_, PAR_HID_TEX_CB_CACHED_MEMORY | PAR_HID_CACHE_INNER___ | PAR_HID_CACHE_OUTER___ },
+    // Device section
+	{ 0xE0000000, 0xE0000000, MMU_SIZE_512MB-MMU_SIZE_1MB, PAR_AP_PRW__URW_, PAR_HID_EXCLUSIVE_SYS_DEVICE },
+	// Upper 1MB section contains 1x 64KB SRAM @ address 0xFFFF0000
+	{ 0xFFF00000, 0xFFF00000, MMU_SIZE_1MB,   PAR_AP_PRW__URW_, PAR_HID_TEX_CB_OUT_IN_NON_CACHABLE }
+};
+
+#endif /* SRC_APP_LWIPREWORK_PS7_CORE0_CFG_MMU_CFG_H_ */

src/APP/Aufgabe1/ps7/core0/cfg/net_cfg.h

@@ -0,0 +1,676 @@
+/*
+*********************************************************************************************************
+*                                             uC/TCP-IP
+*                                      The Embedded TCP/IP Suite
+*
+*                         (c) Copyright 2004-2015; Micrium, Inc.; Weston, FL
+*
+*                  All rights reserved.  Protected by international copyright laws.
+*
+*                  uC/TCP-IP is provided in source form to registered licensees ONLY.  It is
+*                  illegal to distribute this source code to any third party unless you receive
+*                  written permission by an authorized Micrium representative.  Knowledge of
+*                  the source code may NOT be used to develop a similar product.
+*
+*                  Please help us continue to provide the Embedded community with the finest
+*                  software available.  Your honesty is greatly appreciated.
+*
+*                  You can find our product's user manual, API reference, release notes and
+*                  more information at: https://doc.micrium.com
+*
+*                  You can contact us at: http://www.micrium.com
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                     NETWORK CONFIGURATION FILE
+*
+*                                              TEMPLATE
+*
+* Filename : net_cfg.h
+* Version  : V3.03.01
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                            INCLUDE FILES
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#include  <net_def.h>
+#include  <net_type.h>
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                               MODULE
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#ifndef  NET_CFG_MODULE_PRESENT
+#define  NET_CFG_MODULE_PRESENT
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                             NETWORK EXTERNAL APPLICATION CONFIGURATION
+*
+* Note(s) : (1) When uC/DNS-Client is present in the project some high level functions can resolve hostname.
+*               So uC/TCPIP should know that uC/DNS-Client is present to call the proper API.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+                                                                /* Configure DNS Client feature  (see Note #1) :        */
+#define  NET_EXT_MODULE_CFG_DNS_EN                                 DEF_ENABLED
+                                                                /*   DEF_DISABLED       DNS Client is DISABLED          */
+                                                                /*   DEF_ENABLED        DNS Client is  ENABLED          */
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                        TASKS CONFIGURATION
+*
+* Note(s) : (1) (a) Each network task maps to a unique, developer-configured task configuration that
+*                   MUST be defined in application files, typically 'net_cfg.c', & SHOULD be forward-
+*                   declared with the exact same name & type in order to be used by the application during
+*                   calls to Net_Init().
+*
+*               (b) Since these task configuration structures are referenced ONLY by application files,
+*                   there is NO required naming convention for these configuration structures.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+extern  const  NET_TASK_CFG  NetRxTaskCfg;
+extern  const  NET_TASK_CFG  NetTxDeallocTaskCfg;
+extern  const  NET_TASK_CFG  NetTmrTaskCfg;
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                        TASKS Q CONFIGURATION
+*
+* Note(s) : (1) Rx queue size should be configured such that it reflects the total number of DMA receive descriptors on all
+*               devices. If DMA is not available, or a combination of DMA and I/O based interfaces are configured then this
+*               number reflects the maximum number of packets that can be acknowledged and signalled during a single receive
+*               interrupt event for all interfaces.
+*
+*           (2) Tx queue size should be defined to be the total number of small and large transmit buffers declared for
+*               all interfaces.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#define  NET_CFG_IF_RX_Q_SIZE                   100
+#define  NET_CFG_IF_TX_DEALLOC_Q_SIZE           100
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                        NETWORK CONFIGURATION
+*
+* Note(s) : (1) uC/TCP-IP code may call optimized assembly functions. Optimized assembly files/functions must be included
+*               in the project to be enabled. Optimized functions are located in files under folders:
+*
+*                   $uC-TCPIP/Ports/<processor>/<compiler>
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+                                                                /* Configure network protocol suite's assembly ...      */
+                                                                /* ... optimization (see Note #1) :                     */
+#define  NET_CFG_OPTIMIZE_ASM_EN                DEF_DISABLED
+                                                                /*   DEF_DISABLED       Assembly optimization DISABLED  */
+                                                                /*   DEF_ENABLED        Assembly optimization ENABLED   */
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                     NETWORK DEBUG CONFIGURATION
+*
+* Note(s) : (1) Configure NET_DBG_CFG_MEM_CLR_EN to enable/disable the network protocol suite from clearing
+*               internal data structure memory buffers; a convenient feature while debugging.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+                                                                /* Configure memory clear feature  (see Note #1) :      */
+#define  NET_DBG_CFG_MEM_CLR_EN                 DEF_DISABLED
+                                                                /*   DEF_DISABLED  Data structure clears DISABLED       */
+                                                                /*   DEF_ENABLED   Data structure clears ENABLED        */
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                NETWORK ARGUMENT CHECK CONFIGURATION
+*
+* Note(s) : (1) Configure NET_ERR_CFG_ARG_CHK_EXT_EN to enable/disable the network protocol suite external
+*               argument check feature :
+*
+*               (a) When ENABLED,  ALL arguments received from any port interface provided by the developer
+*                   or application are checked/validated.
+*
+*               (b) When DISABLED, NO  arguments received from any port interface provided by the developer
+*                   or application are checked/validated.
+*
+*           (2) Configure NET_ERR_CFG_ARG_CHK_DBG_EN to enable/disable the network protocol suite internal,
+*               debug argument check feature :
+*
+*               (a) When ENABLED,     internal arguments are checked/validated to debug the network protocol
+*                   suite.
+*
+*               (b) When DISABLED, NO internal arguments are checked/validated to debug the network protocol
+*                   suite.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+                                                                /* Configure external argument check feature ...        */
+                                                                /* ... (see Note #1) :                                  */
+#define  NET_ERR_CFG_ARG_CHK_EXT_EN             DEF_ENABLED
+                                                                /*   DEF_DISABLED     Argument check DISABLED           */
+                                                                /*   DEF_ENABLED      Argument check ENABLED            */
+
+                                                                /* Configure internal argument check feature ...        */
+                                                                /* ... (see Note #2) :                                  */
+#define  NET_ERR_CFG_ARG_CHK_DBG_EN             DEF_DISABLED
+                                                                /*   DEF_DISABLED     Argument check DISABLED           */
+                                                                /*   DEF_ENABLED      Argument check ENABLED            */
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                               NETWORK COUNTER MANAGEMENT CONFIGURATION
+*
+* Note(s) : (1) Configure NET_CTR_CFG_STAT_EN to enable/disable network protocol suite statistics counters.
+*
+*           (2) Configure NET_CTR_CFG_ERR_EN  to enable/disable network protocol suite error      counters.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+                                                                /* Configure statistics counter feature (see Note #1) : */
+#define  NET_CTR_CFG_STAT_EN                    DEF_DISABLED
+                                                                /*   DEF_DISABLED     Stat  counters DISABLED           */
+                                                                /*   DEF_ENABLED      Stat  counters ENABLED            */
+
+                                                                /* Configure error      counter feature (see Note #2) : */
+#define  NET_CTR_CFG_ERR_EN                     DEF_DISABLED
+                                                                /*   DEF_DISABLED     Error counters DISABLED           */
+                                                                /*   DEF_ENABLED      Error counters ENABLED            */
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                               NETWORK TIMER MANAGEMENT CONFIGURATION
+*
+* Note(s) : (1) Configure NET_TMR_CFG_NBR_TMR with the desired number of network TIMER objects.
+*
+*               Timers are required for :
+*
+*               (a) ARP & NDP cache entries
+*               (b) IP        fragment reassembly
+*               (c) TCP       state machine connections
+*               (d) IF        Link status check-up
+*
+*           (2) Configure NET_TMR_CFG_TASK_FREQ to schedule the execution frequency of the network timer
+*               task -- how often NetTmr_TaskHandler() is scheduled to run per second as implemented in
+*               NetTmr_Task().
+*
+*               (a) NET_TMR_CFG_TASK_FREQ  MUST NOT be configured as a floating-point frequency.
+*
+*               See also 'net_tmr.h  NETWORK TIMER TASK TIME DEFINES  Notes #1 & #2'
+*                      & 'net_tmr.c  NetTmr_Task()  Notes #1 & #2'.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#define  NET_TMR_CFG_NBR_TMR                    100
+#define  NET_TMR_CFG_TASK_FREQ                  10
+
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                NETWORK INTERFACE LAYER CONFIGURATION
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#define  NET_IF_CFG_MAX_NBR_IF                  1
+
+                                                                /* Configure specific interface(s) :                    */
+#define  NET_IF_CFG_LOOPBACK_EN                 DEF_DISABLED
+
+#define  NET_IF_CFG_ETHER_EN                    DEF_ENABLED
+
+#define  NET_IF_CFG_WIFI_EN                     DEF_DISABLED
+                                                                /*   DEF_DISABLED      Interface type DISABLED          */
+                                                                /*   DEF_ENABLED       interface type ENABLED           */
+
+#define  NET_IF_CFG_TX_SUSPEND_TIMEOUT_MS       1
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                           ADDRESS RESOLUTION PROTOCOL LAYER CONFIGURATION
+*
+* Note(s) : (1) Address resolution protocol ONLY required for IPv4.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#define  NET_ARP_CFG_CACHE_NBR                  3
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                           NEIGHBOR DISCOVERY PROTOCOL LAYER CONFIGURATION
+*
+* Note(s) : (1) Neighbor Discovery Protocol ONLY required for IPv6.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#define  NET_NDP_CFG_CACHE_NBR                  5
+#define  NET_NDP_CFG_DEST_NBR                   5
+#define  NET_NDP_CFG_PREFIX_NBR                 5
+#define  NET_NDP_CFG_ROUTER_NBR                 1
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                            INTERNET PROTOCOL LAYER VERSION CONFIGURATION
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                                                IPv4
+*********************************************************************************************************
+*/
+                                                                /* Configure IPv4.                                      */
+#define  NET_IPv4_CFG_EN                        DEF_ENABLED
+                                                                /*   DEF_DISABLED    IPv4 disabled.                     */
+                                                                /*   DEF_ENABLED     IPv4 enabled.                      */
+
+
+#define  NET_IPv4_CFG_IF_MAX_NBR_ADDR           1
+
+/*
+*********************************************************************************************************
+*                                                IPv6
+*********************************************************************************************************
+*/
+
+                                                                /* Configure IPv6.                                      */
+#define  NET_IPv6_CFG_EN                        DEF_DISABLED
+                                                                /*   DEF_DISABLED    IPv6 disabled.                     */
+                                                                /*   DEF_ENABLED     IPv6 enabled.                      */
+
+                                                                /* Configure IPv6 Stateless Address Auto-Configuration. */
+#define  NET_IPv6_CFG_ADDR_AUTO_CFG_EN          DEF_ENABLED
+                                                                /*   DEF_DISABLED    IPv6 Auto-Cfg disabled.            */
+                                                                /*   DEF_ENABLED     IPv6 Auto-Cfg enabled.             */
+
+                                                                /* Configure IPv6 Duplication Address Detection (DAD).  */
+#define  NET_IPv6_CFG_DAD_EN                    DEF_ENABLED
+                                                                /*   DEF_DISABLED    IPv6 DAD disabled.                 */
+                                                                /*   DEF_ENABLED     IPv6 DAD enabled.                  */
+
+#define  NET_IPv6_CFG_IF_MAX_NBR_ADDR           2
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                  INTERNET GROUP MANAGEMENT PROTOCOL(MULTICAST) LAYER CONFIGURATION
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+                                                                /* Configure IPv4 multicast support :                   */
+#define  NET_MCAST_CFG_IPv4_RX_EN               DEF_ENABLED
+#define  NET_MCAST_CFG_IPv4_TX_EN               DEF_ENABLED
+                                                                /*   DEF_DISABLED    Multicast rx or tx disabled.       */
+                                                                /*   DEF_ENABLED     Multicast rx or tx enabled.        */
+
+#define  NET_MCAST_CFG_HOST_GRP_NBR_MAX         2
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                 NETWORK SOCKET LAYER CONFIGURATION
+*
+* Note(s) : (1) The maximum accept queue size represents the number of connection that can be queued by
+*               the stack before being accepted. For a TCP server when a connection is queued, it means
+*               that the SYN, ACK packet has been sent back, so the remote host can start transmitting
+*               data once the connection is queued and the stack will queue up all data received until
+*               the connection is accepted and the data is read.
+*
+*           (2) Receive and transmit queue size MUST be properly configured to optimize performance.
+*
+*               (a) It represents the number of bytes that can be queued by one socket. It's important
+*                   that all socket are not able to queue more data than what the device can hold in its
+*                   buffers.
+*
+*               (b) The size should be also a multiple of the maximum segment size (MSS) to optimize
+*                   performance. UDP MSS is 1470 and TCP MSS is 1460.
+*
+*               (c) RX and TX queue size can be reduce at runtime using socket option API.
+*
+*               (d) Window calculation example:
+*
+*                       Number of TCP connection  : 2
+*                       Number of UDP connection  : 0
+*                       Number of RX large buffer : 10
+*                       Number of TX Large buffer : 6
+*                       Number of TX small buffer : 2
+*                       Size of RX large buffer   : 1518
+*                       Size of TX large buffer   : 1518
+*                       Size of TX small buffer   : 60
+*
+*                       TCP MSS RX                = 1460
+*                       TCP MSS TX large buffer   = 1460
+*                       TCP MSS TX small buffer   = 0
+*
+*                       Maximum receive  window   = (10 * 1460)           = 14600 bytes
+*                       Maximum transmit window   = (6  * 1460) + (2 * 0) = 8760  bytes
+*
+*                       RX window size per socket = (14600 / 2)           =  7300 bytes
+*                       TX window size per socket = (8760  / 2)           =  4380 bytes
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#define  NET_SOCK_CFG_SOCK_NBR_TCP              2
+#define  NET_SOCK_CFG_SOCK_NBR_UDP              1
+
+                                                                /* Configure socket select functionality :              */
+#define  NET_SOCK_CFG_SEL_EN                    DEF_ENABLED
+                                                                /*   DEF_DISABLED  Socket select  DISABLED              */
+                                                                /*   DEF_ENABLED   Socket select  ENABLED               */
+
+                                                                /* Configure stream-type sockets' accept queue          */
+#define  NET_SOCK_CFG_CONN_ACCEPT_Q_SIZE_MAX    2
+
+
+                                                                /* Configure sockets' buffer sizes in number of octets  */
+                                                                /* (see Note #2):                                       */
+#define  NET_SOCK_CFG_RX_Q_SIZE_OCTET           4096
+#define  NET_SOCK_CFG_TX_Q_SIZE_OCTET           4096
+
+
+/* ==================================  ADVANCED SOCKET CONFIGURATION: DEFAULT VALUES ================================== */
+/* By default sockets are set to block. Add the following define to set all sockets as non-blocking. Note that it's     */
+/* possible to change socket's blocking mode at runtime using socket option API.                                        */
+/*                                                                                                                      */
+/*     #define  NET_SOCK_DFLT_NO_BLOCK_EN                     DEF_ENABLED                                               */
+/*                                                                                                                      */
+/* By default random port start at 65000, redefine the following define to modify where random port start:              */
+/*                                                                                                                      */
+/*     #define  NET_SOCK_DFLT_PORT_NBR_RANDOM_BASE            65000u                                                    */
+/*                                                                                                                      */
+/* When a socket is set as blocking the following default timeout values are used. Redefine the following defines to    */
+/* change default timeouts. Timeout values may also be configured with network time constant, NET_TMR_TIME_INFINITE,    */
+/* to never time out. Note that it's possible to change at runtime any timeout values using Socket option API.          */
+/*                                                                                                                      */
+/*     #define  NET_SOCK_DFLT_TIMEOUT_RX_Q_MS                 10000u                                                    */
+/*     #define  NET_SOCK_DFLT_TIMEOUT_CONN_REQ_MS             10000u                                                    */
+/*     #define  NET_SOCK_DFLT_TIMEOUT_CONN_ACCEPT_MS          10000u                                                    */
+/*     #define  NET_SOCK_DFLT_TIMEOUT_CONN_CLOSE_MS           10000u                                                    */
+/* ==================================================================================================================== */
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                          TRANSMISSION CONTROL PROTOCOL LAYER CONFIGURATION
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+                                                                /* Configure TCP support :                              */
+#define  NET_TCP_CFG_EN                         DEF_ENABLED
+                                                                /*   DEF_DISABLED  TCP layer  DISABLED                  */
+                                                                /*   DEF_ENABLED   TCP layer  ENABLED                   */
+
+/* ========================================= ADVANCED TCP LAYER CONFIGURATION ========================================= */
+/* By default TCP RX and TX windows are set to equal the socket RX and TX queue sizes. Default values can be changed by */
+/* redefining the following defines. TCP windows must be properly configured to optimize performance (see note about    */
+/* Socket TX and RX windows). Note that it's possible to decrease window size at run time using Socket option API.      */
+/*                                                                                                                      */
+/*     #define  NET_TCP_DFLT_RX_WIN_SIZE_OCTET      NET_SOCK_CFG_RX_Q_SIZE_OCTET                                        */
+/*     #define  NET_TCP_DFLT_TX_WIN_SIZE_OCTET      NET_SOCK_CFG_TX_Q_SIZE_OCTET                                        */
+/*                                                                                                                      */
+/* As shown in the TCP state diagram (see RFC #793), before moving from 'TIME-WAIT' state to 'CLOSED' state a timeout   */
+/* (2MSL) must expire. This means that the TCP connection cannot be made available for subsequent TCP connections until */
+/* this timeout. It can be a problem for embedded systems with low resources especially when many TCP connections are   */
+/* made in a small period of time since it is possible to run out of free TCP connections quickly. Therefore this       */
+/* timeout is set to 0 by default to avoid this kind of problem and the connection is made available as soon as the     */
+/* 'TIME-WAIT' state is reached. However, it's possible to set the default MSL timeout to something else by redefining  */
+/* the following define. Note that it is possible to change the MSL timeout for a specific TCP connection using Socket  */
+/* option API.                                                                                                          */
+/*                                                                                                                      */
+/*     #define  NET_TCP_DFLT_TIMEOUT_CONN_MAX_SEG_SEC       0u                                                          */
+/*                                                                                                                      */
+/* To avoid leaving a connection in the FIN_WAIT_2 state forever when a connection moves from the 'FIN_WAIT_1' state to */
+/* the FIN_WAIT_2, the TCP connection's timer is set to 15 second, and when it expires the connection is dropped. Thus, */
+/* if the other host doesn't response to the close request, the connection will still be closed after the timeout.      */
+/* This default timeout can be change by redefining the following define.                                               */
+/*                                                                                                                      */
+/*     #define  NET_TCP_DFLT_TIMEOUT_CONN_FIN_WAIT_2_SEC    15u                                                         */
+/*                                                                                                                      */
+/* The number of TCP connections is configured following the number of TCP sockets and the accept queue size when the   */
+/* MSL is set to 0 ms. However, since the default MSL can be modified, it might be needed to increase the number of TCP */
+/* connections to establish more connections when waiting for the MSL expiration. It is possible to add more TCP        */
+/* connections by defining the following define.                                                                        */
+/*                                                                                                                      */
+/*     #define  NET_TCP_CFG_NBR_CONN                        0u                                                          */
+/*                                                                                                                      */
+/* By default an 'ACK' is generated within 500 ms of the arrival of the first unacknowledged packet, as specified in    */
+/* RFC #2581, Section 4.2. However it's possible to modify this value by defining the following define.                 */
+/*                                                                                                                      */
+/*     #define  NET_TCP_DFLT_TIMEOUT_CONN_ACK_DLY_MS        500u                                                        */
+/*                                                                                                                      */
+/* When a socket is set as blocking the following default timeout values are used. Redefine the following defines to    */
+/* change default timeout. Timeout values may also be configured with network time constant, NET_TMR_TIME_INFINITE,     */
+/* to never time out. Note that it's possible to change at runtime any timeout values using Socket option API.          */
+/*     #define  NET_TCP_DFLT_TIMEOUT_CONN_RX_Q_MS           1000u                                                       */
+/*     #define  NET_TCP_DFLT_TIMEOUT_CONN_TX_Q_MS           1000u                                                       */
+/* ==================================================================================================================== */
+
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                             USER DATAGRAM PROTOCOL LAYER CONFIGURATION
+*
+* Note(s) : (1) Configure NET_UDP_CFG_APP_API_SEL with the desired configuration for demultiplexing
+*               UDP datagrams to application connections :
+*
+*                   NET_UDP_APP_API_SEL_SOCK        Demultiplex UDP datagrams to BSD sockets ONLY.
+*                   NET_UDP_APP_API_SEL_APP         Demultiplex UDP datagrams to application-specific
+*                                                       connections ONLY.
+*                   NET_UDP_APP_API_SEL_SOCK_APP    Demultiplex UDP datagrams to BSD sockets first;
+*                                                       if NO socket connection found to demultiplex
+*                                                       a UDP datagram, demultiplex to application-
+*                                                       specific connection.
+*
+*               See also 'net_udp.c  NetUDP_RxPktDemuxDatagram()  Note #1'
+*                      & 'net_udp.c  NetUDP_RxPktDemuxAppData()   Note #1'.
+*
+*           (2) (a) RFC #1122, Section 4.1.3.4 states that "an application MAY optionally ... discard
+*                   ... [or allow] ... received ... UDP datagrams without checksums".
+*
+*               (b) Configure NET_UDP_CFG_RX_CHK_SUM_DISCARD_EN to enable/disable discarding of UDP
+*                   datagrams received with NO computed check-sum :
+*
+*                   (1) When ENABLED,  ALL UDP datagrams received without a check-sum are discarded.
+*
+*                   (2) When DISABLED, ALL UDP datagrams received without a check-sum are flagged so
+*                       that application(s) may handle &/or discard.
+*
+*               See also 'net_udp.c  NetUDP_RxPktValidate()  Note #4d3A'.
+*
+*           (3) (a) RFC #1122, Section 4.1.3.4 states that "an application MAY optionally be able to
+*                   control whether a UDP checksum will be generated".
+*
+*               (b) Configure NET_UDP_CFG_TX_CHK_SUM_EN to enable/disable transmitting UDP datagrams
+*                   with check-sums :
+*
+*                   (1) When ENABLED,  ALL UDP datagrams are transmitted with    a computed check-sum.
+*
+*                   (2) When DISABLED, ALL UDP datagrams are transmitted without a computed check-sum.
+*
+*               See also 'net_udp.c  NetUDP_TxPktPrepareHdr()  Note #3b'.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+                                                                /* Configure UDP Receive Check-Sum Discard feature ...  */
+                                                                /* ... (see Note #2b) :                                 */
+#define  NET_UDP_CFG_RX_CHK_SUM_DISCARD_EN      DEF_DISABLED
+                                                                /*   DEF_DISABLED  UDP Check-Sums  Received without ... */
+                                                                /*                     Check-Sums Validated             */
+                                                                /*   DEF_ENABLED   UDP Datagrams  Received without ...  */
+                                                                /*                     Check-Sums Discarded             */
+
+                                                                /* Configure UDP Transmit Check-Sum feature ...         */
+                                                                /* ... (see Note #3b) :                                 */
+#define  NET_UDP_CFG_TX_CHK_SUM_EN              DEF_DISABLED
+                                                                /*   DEF_DISABLED  Transmit Check-Sums  DISABLED        */
+                                                                /*   DEF_ENABLED   Transmit Check-Sums  ENABLED         */
+
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                               NETWORK SECURITY MANAGER CONFIGURATION
+*
+* Note(s): (1) The network security layer can be enabled ONLY if the application project contains a secure module
+*              supported by uC/TCPIP such as:
+*
+*              (a) NanoSSL provided by Mocana.
+*              (b) CyaSSL  provided by YaSSL.
+*
+*          (2) The network security port must be also added to the project. Security port can be found under the folder:
+*
+*                 $uC-TCPIP/Secure/<module>
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+                                                                /* Configure network security layer (See Note #1 & #2): */
+#define  NET_SECURE_CFG_EN                      DEF_DISABLED
+                                                                /*   DEF_DISABLED  Security layer  DISABLED             */
+                                                                /*   DEF_ENABLED   Security layer  ENABLED              */
+
+#define  NET_SECURE_CFG_MAX_NBR_SOCK_SERVER     2u              /* Configure total number of server secure sockets.     */
+#define  NET_SECURE_CFG_MAX_NBR_SOCK_CLIENT     2u              /* Configure total number of client secure sockets.     */
+
+#define  NET_SECURE_CFG_MAX_CERT_LEN            1500u           /* Configure servers certificate maximum length (bytes) */
+#define  NET_SECURE_CFG_MAX_KEY_LEN             1500u           /* Configure servers key maximum length (bytes)         */
+
+                                                                /* Configure maximum number of certificate authorities  */
+#define  NET_SECURE_CFG_MAX_NBR_CA              1u              /* that can be installed.                               */
+
+#define  NET_SECURE_CFG_MAX_CA_CERT_LEN         1500u           /* Configure CA certificate maximum length (bytes)      */
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                               INTERFACE CHECKSUM OFFLOAD CONFIGURATION
+*
+* Note(s): (1) These configuration can be enabled only if all your interfaces support specific checksum offload
+*              option.
+*
+*          (2) By default a driver should enabled the all checksum offload option.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+/* ========================================== ADVANCED OFFLOAD CONFIGURATION ========================================== */
+/* By default all checksum are validated by the stack however it is possible to enable or disable specific checksum     */
+/* validate and calculation if the interface controller is able to achieve it. You can add the following define in this */
+/* file to change the default behavior.                                                                                 */
+/*                                                                                                                      */
+/* -------------------------------------------------- IPv4 CHECKSUM --------------------------------------------------- */
+/*                                                  Configure validation in reception.                                  */
+/* #define  NET_IPV4_CFG_CHK_SUM_OFFLOAD_RX_EN  DEF_DISABLED                                                            */
+/*                                                                                                                      */
+/*                                                  Configure calculation in transmission.                              */
+/* #define  NET_IPV4_CFG_CHK_SUM_OFFLOAD_TX_EN  DEF_DISABLED                                                            */
+/*                                                                                                                      */
+/*                                                                                                                      */
+/* -------------------------------------------------- ICMP CHECKSUM --------------------------------------------------- */
+/*                                                  Configure validation in reception.                                  */
+/* #define  NET_ICMP_CFG_CHK_SUM_OFFLOAD_RX_EN  DEF_DISABLED                                                            */
+/*                                                                                                                      */
+/*                                                  Configure calculation in transmission.                              */
+/* #define  NET_ICMP_CFG_CHK_SUM_OFFLOAD_TX_EN  DEF_DISABLED                                                            */
+/*                                                                                                                      */
+/*                                                                                                                      */
+/* --------------------------------------------------- UDP CHECKSUM --------------------------------------------------- */
+/*                                                  Configure validation in reception.                                  */
+/* #define  NET_UDP_CFG_CHK_SUM_OFFLOAD_RX_EN   DEF_DISABLED                                                            */
+/*                                                                                                                      */
+/*                                                  Configure calculation in transmission.                              */
+/* #define  NET_UDP_CFG_CHK_SUM_OFFLOAD_TX_EN   DEF_DISABLED                                                            */
+/*                                                                                                                      */
+/*                                                                                                                      */
+/* --------------------------------------------------- TCP CHECKSUM --------------------------------------------------- */
+/*                                                  Configure validation in reception.                                  */
+/* #define  NET_TCP_CFG_CHK_SUM_OFFLOAD_RX_EN   DEF_DISABLED                                                            */
+/*                                                                                                                      */
+/*                                                  Configure calculation in transmission.                              */
+/* #define  NET_TCP_CFG_CHK_SUM_OFFLOAD_TX_EN   DEF_DISABLED                                                            */
+/* ==================================================================================================================== */
+
+
+/* ======================================================= END ======================================================== */
+#endif  /* NET_CFG_MODULE_PRESENT */
+
+#define  NET_IPV4_CFG_CHK_SUM_OFFLOAD_RX_EN  DEF_DISABLED
+#define  NET_IPV4_CFG_CHK_SUM_OFFLOAD_TX_EN  DEF_DISABLED
+#define  NET_ICMP_CFG_CHK_SUM_OFFLOAD_RX_EN  DEF_DISABLED
+#define  NET_ICMP_CFG_CHK_SUM_OFFLOAD_TX_EN  DEF_DISABLED
+#define  NET_UDP_CFG_CHK_SUM_OFFLOAD_RX_EN  DEF_DISABLED
+#define  NET_UDP_CFG_CHK_SUM_OFFLOAD_TX_EN  DEF_DISABLED
+#define  NET_TCP_CFG_CHK_SUM_OFFLOAD_RX_EN  DEF_DISABLED
+#define  NET_TCP_CFG_CHK_SUM_OFFLOAD_TX_EN  DEF_DISABLED

src/APP/Aufgabe1/ps7/core0/cfg/net_xil_ether_lite_dev_cfg.h

@@ -0,0 +1,115 @@
+/*
+*********************************************************************************************************
+*                                             uC/TCP-IP
+*                                      The Embedded TCP/IP Suite
+*
+*                         (c) Copyright 2004-2015; Micrium, Inc.; Weston, FL
+*
+*                  All rights reserved.  Protected by international copyright laws.
+*
+*                  uC/TCP-IP is provided in source form to registered licensees ONLY.  It is
+*                  illegal to distribute this source code to any third party unless you receive
+*                  written permission by an authorized Micrium representative.  Knowledge of
+*                  the source code may NOT be used to develop a similar product.
+*
+*                  Please help us continue to provide the Embedded community with the finest
+*                  software available.  Your honesty is greatly appreciated.
+*
+*                  You can find our product's user manual, API reference, release notes and
+*                  more information at: https://doc.micrium.com
+*
+*                  You can contact us at: http://www.micrium.com
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                  NETWORK DEVICE CONFIGURATION FILE
+*
+*                                              TEMPLATE
+*
+* Filename : net_dev_cfg.h
+* Version  : V3.00.00
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                               MODULE
+*
+* Note(s) : (1) This network device configuration header file is protected from multiple pre-processor
+*               inclusion through use of the network module present pre-processor macro definition.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#ifndef  NET_DEV_CFG_MODULE_PRESENT                             /* See Note #1.                                         */
+#define  NET_DEV_CFG_MODULE_PRESENT
+
+#include   <Source/net_cfg_net.h>
+
+#ifdef  NET_IF_ETHER_MODULE_EN
+#include   <IF/net_if_ether.h>
+#endif
+
+#ifdef  NET_IF_WIFI_MODULE_EN
+#include   <IF/net_if_wifi.h>
+#endif
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                    NETWORK DEVICE CONFIGURATION
+*
+* Note(s) : (1) (a) Each network device maps to a unique, developer-configured device configuration that
+*                   MUST be defined in application files, typically 'net_dev_cfg.c', & SHOULD be forward-
+*                   declared with the exact same name & type in order to be used by the application during
+*                   calls to NetIF_Add().
+*
+*               (b) Since these device configuration structures are referenced ONLY by application files,
+*                   there is NO required naming convention for these configuration structures.  However,
+*                   the following naming convention is suggested for all developer-configured network
+*                   device configuration structures :
+*
+*                       NetDev_Cfg_<Device>[_Number]
+*
+*                           where
+*                                   <Device>        Name of device or device driver
+*                                   [Number]        Network device number for each specific instance of
+*                                                       device (optional if the development board does NOT
+*                                                       support multiple instances of the specific device)
+*
+*                       Examples :
+*
+*                           NET_DEV_CFG_ETHER  NetDev_Cfg_MACB;         Ethernet configuration for MACB
+*
+*                           NET_DEV_CFG_ETHER  NetDev_Cfg_FEC_0;        Ethernet configuration for FEC #0
+*                           NET_DEV_CFG_ETHER  NetDev_Cfg_FEC_1;        Ethernet configuration for FEC #1
+*
+*                           NET_DEV_CFG_WIFI   NetDev_Cfg_RS9110N21_0;  Wireless configuration for RS9110-N-21
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#ifdef  NET_IF_ETHER_MODULE_EN
+
+extern  NET_DEV_CFG_ETHER  NetDev_AXIEthernetLite_0;
+extern  NET_PHY_CFG_ETHER  NetPhy_Cfg_Ether_0;
+
+#endif  /* NET_IF_ETHER_MODULE_EN */
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                             MODULE END
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#endif  /* NET_DEV_CFG_MODULE_PRESENT */
+

src/APP/Aufgabe1/ps7/core0/cfg/os_cfg.h

@@ -0,0 +1,145 @@
+/*
+*********************************************************************************************************
+*                                                uC/OS-II
+*                                          The Real-Time Kernel
+*                                  uC/OS-II Configuration File for V2.9x
+*
+*                               (c) Copyright 2005-2014, Micrium, Weston, FL
+*                                          All Rights Reserved
+*
+*
+* File    : OS_CFG.H
+* By      : Jean J. Labrosse
+* Version : V2.92.11
+*
+* LICENSING TERMS:
+* ---------------
+*   uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research.
+* If you plan on using  uC/OS-II  in a commercial product you need to contact Micrium to properly license
+* its use in your product. We provide ALL the source code for your convenience and to help you experience
+* uC/OS-II.   The fact that the  source is provided does  NOT  mean that you can use it without  paying a
+* licensing fee.
+*********************************************************************************************************
+*/
+
+#ifndef OS_CFG_H
+#define OS_CFG_H
+
+
+                                       /* ---------------------- MISCELLANEOUS ----------------------- */
+#define OS_APP_HOOKS_EN           1u   /* Application-defined hooks are called from the uC/OS-II hooks */
+#define OS_ARG_CHK_EN             0u   /* Enable (1) or Disable (0) argument checking                  */
+#define OS_CPU_HOOKS_EN           1u   /* uC/OS-II hooks are found in the processor port files         */
+
+#define OS_DEBUG_EN               1u   /* Enable(1) debug variables                                    */
+
+#define OS_EVENT_MULTI_EN         1u   /* Include code for OSEventPendMulti()                          */
+#define OS_EVENT_NAME_EN          1u   /* Enable names for Sem, Mutex, Mbox and Q                      */
+
+#define OS_LOWEST_PRIO           63u   /* Defines the lowest priority that can be assigned ...         */
+                                       /* ... MUST NEVER be higher than 254!                           */
+
+#define OS_MAX_EVENTS            20u   /* Max. number of event control blocks in your application      */
+#define OS_MAX_FLAGS              5u   /* Max. number of Event Flag Groups    in your application      */
+#define OS_MAX_MEM_PART           5u   /* Max. number of memory partitions                             */
+#define OS_MAX_QS                 6u   /* Max. number of queue control blocks in your application      */
+#define OS_MAX_TASKS             20u   /* Max. number of tasks in your application, MUST be >= 2       */
+
+#define OS_SCHED_LOCK_EN          1u   /* Include code for OSSchedLock() and OSSchedUnlock()           */
+
+#define OS_TICK_STEP_EN           1u   /* Enable tick stepping feature for uC/OS-View                  */
+#define OS_TICKS_PER_SEC       1000u   /* Set the number of ticks in one second                        */
+
+#define OS_TLS_TBL_SIZE           0u   /* Size of Thread-Local Storage Table                           */
+
+
+                                       /* --------------------- TASK STACK SIZE ---------------------- */
+#define OS_TASK_TMR_STK_SIZE    128u   /* Timer      task stack size (# of OS_STK wide entries)        */
+#define OS_TASK_STAT_STK_SIZE   128u   /* Statistics task stack size (# of OS_STK wide entries)        */
+#define OS_TASK_IDLE_STK_SIZE   128u   /* Idle       task stack size (# of OS_STK wide entries)        */
+
+
+                                       /* --------------------- TASK MANAGEMENT ---------------------- */
+#define OS_TASK_CHANGE_PRIO_EN    1u   /*     Include code for OSTaskChangePrio()                      */
+#define OS_TASK_CREATE_EN         1u   /*     Include code for OSTaskCreate()                          */
+#define OS_TASK_CREATE_EXT_EN     1u   /*     Include code for OSTaskCreateExt()                       */
+#define OS_TASK_DEL_EN            1u   /*     Include code for OSTaskDel()                             */
+#define OS_TASK_NAME_EN           1u   /*     Enable task names                                        */
+#define OS_TASK_PROFILE_EN        1u   /*     Include variables in OS_TCB for profiling                */
+#define OS_TASK_QUERY_EN          1u   /*     Include code for OSTaskQuery()                           */
+#define OS_TASK_REG_TBL_SIZE      1u   /*     Size of task variables array (#of INT32U entries)        */
+#define OS_TASK_STAT_EN           1u   /*     Enable (1) or Disable(0) the statistics task             */
+#define OS_TASK_STAT_STK_CHK_EN   1u   /*     Check task stacks from statistic task                    */
+#define OS_TASK_SUSPEND_EN        1u   /*     Include code for OSTaskSuspend() and OSTaskResume()      */
+#define OS_TASK_SW_HOOK_EN        1u   /*     Include code for OSTaskSwHook()                          */
+
+
+                                       /* ----------------------- EVENT FLAGS ------------------------ */
+#define OS_FLAG_EN                1u   /* Enable (1) or Disable (0) code generation for EVENT FLAGS    */
+#define OS_FLAG_ACCEPT_EN         1u   /*     Include code for OSFlagAccept()                          */
+#define OS_FLAG_DEL_EN            1u   /*     Include code for OSFlagDel()                             */
+#define OS_FLAG_NAME_EN           1u   /*     Enable names for event flag group                        */
+#define OS_FLAG_QUERY_EN          1u   /*     Include code for OSFlagQuery()                           */
+#define OS_FLAG_WAIT_CLR_EN       1u   /* Include code for Wait on Clear EVENT FLAGS                   */
+#define OS_FLAGS_NBITS           16u   /* Size in #bits of OS_FLAGS data type (8, 16 or 32)            */
+
+
+                                       /* -------------------- MESSAGE MAILBOXES --------------------- */
+#define OS_MBOX_EN                1u   /* Enable (1) or Disable (0) code generation for MAILBOXES      */
+#define OS_MBOX_ACCEPT_EN         1u   /*     Include code for OSMboxAccept()                          */
+#define OS_MBOX_DEL_EN            1u   /*     Include code for OSMboxDel()                             */
+#define OS_MBOX_PEND_ABORT_EN     1u   /*     Include code for OSMboxPendAbort()                       */
+#define OS_MBOX_POST_EN           1u   /*     Include code for OSMboxPost()                            */
+#define OS_MBOX_POST_OPT_EN       1u   /*     Include code for OSMboxPostOpt()                         */
+#define OS_MBOX_QUERY_EN          1u   /*     Include code for OSMboxQuery()                           */
+
+
+                                       /* --------------------- MEMORY MANAGEMENT -------------------- */
+#define OS_MEM_EN                 1u   /* Enable (1) or Disable (0) code generation for MEMORY MANAGER */
+#define OS_MEM_NAME_EN            1u   /*     Enable memory partition names                            */
+#define OS_MEM_QUERY_EN           1u   /*     Include code for OSMemQuery()                            */
+
+
+                                       /* ---------------- MUTUAL EXCLUSION SEMAPHORES --------------- */
+#define OS_MUTEX_EN               1u   /* Enable (1) or Disable (0) code generation for MUTEX          */
+#define OS_MUTEX_ACCEPT_EN        1u   /*     Include code for OSMutexAccept()                         */
+#define OS_MUTEX_DEL_EN           1u   /*     Include code for OSMutexDel()                            */
+#define OS_MUTEX_QUERY_EN         1u   /*     Include code for OSMutexQuery()                          */
+
+
+                                       /* ---------------------- MESSAGE QUEUES ---------------------- */
+#define OS_Q_EN                   1u   /* Enable (1) or Disable (0) code generation for QUEUES         */
+#define OS_Q_ACCEPT_EN            1u   /*     Include code for OSQAccept()                             */
+#define OS_Q_DEL_EN               1u   /*     Include code for OSQDel()                                */
+#define OS_Q_FLUSH_EN             1u   /*     Include code for OSQFlush()                              */
+#define OS_Q_PEND_ABORT_EN        1u   /*     Include code for OSQPendAbort()                          */
+#define OS_Q_POST_EN              1u   /*     Include code for OSQPost()                               */
+#define OS_Q_POST_FRONT_EN        1u   /*     Include code for OSQPostFront()                          */
+#define OS_Q_POST_OPT_EN          1u   /*     Include code for OSQPostOpt()                            */
+#define OS_Q_QUERY_EN             1u   /*     Include code for OSQQuery()                              */
+
+
+                                       /* ------------------------ SEMAPHORES ------------------------ */
+#define OS_SEM_EN                 1u   /* Enable (1) or Disable (0) code generation for SEMAPHORES     */
+#define OS_SEM_ACCEPT_EN          1u   /*    Include code for OSSemAccept()                            */
+#define OS_SEM_DEL_EN             1u   /*    Include code for OSSemDel()                               */
+#define OS_SEM_PEND_ABORT_EN      1u   /*    Include code for OSSemPendAbort()                         */
+#define OS_SEM_QUERY_EN           1u   /*    Include code for OSSemQuery()                             */
+#define OS_SEM_SET_EN             1u   /*    Include code for OSSemSet()                               */
+
+
+                                       /* --------------------- TIME MANAGEMENT ---------------------- */
+#define OS_TIME_DLY_HMSM_EN       1u   /*     Include code for OSTimeDlyHMSM()                         */
+#define OS_TIME_DLY_RESUME_EN     1u   /*     Include code for OSTimeDlyResume()                       */
+#define OS_TIME_GET_SET_EN        1u   /*     Include code for OSTimeGet() and OSTimeSet()             */
+#define OS_TIME_TICK_HOOK_EN      1u   /*     Include code for OSTimeTickHook()                        */
+
+
+                                       /* --------------------- TIMER MANAGEMENT --------------------- */
+#define OS_TMR_EN                 0u   /* Enable (1) or Disable (0) code generation for TIMERS         */
+#define OS_TMR_CFG_MAX           16u   /*     Maximum number of timers                                 */
+#define OS_TMR_CFG_NAME_EN        1u   /*     Determine timer names                                    */
+#define OS_TMR_CFG_WHEEL_SIZE     7u   /*     Size of timer wheel (#Spokes)                            */
+#define OS_TMR_CFG_TICKS_PER_SEC 10u   /*     Rate at which timer management task runs (Hz)            */
+
+#endif

src/APP/Aufgabe1/ps7/core0/cfg/shell_cfg.h

@@ -0,0 +1,96 @@
+/*
+*********************************************************************************************************
+*                                              uC/Shell
+*                                            Shell Utility
+*
+*                          (c) Copyright 2007-2013; Micrium, Inc.; Weston, FL
+*
+*               All rights reserved.  Protected by international copyright laws.
+*
+*               uC/Shell is provided in source form to registered licensees ONLY.  It is
+*               illegal to distribute this source code to any third party unless you receive
+*               written permission by an authorized Micrium representative.  Knowledge of
+*               the source code may NOT be used to develop a similar product.
+*
+*               Please help us continue to provide the Embedded community with the finest
+*               software available.  Your honesty is greatly appreciated.
+*
+*               You can contact us at www.micrium.com.
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                  SHELL UTILITY CONFIGURATION FILE
+*
+*                                              TEMPLATE
+*
+* Filename      : shell_cfg.h
+* Version       : V1.03.01
+* Programmer(s) : SR
+*                 FBJ
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                                 MODULE
+*********************************************************************************************************
+*/
+
+#ifndef  SHELL_CFG_H
+#define  SHELL_CFG_H
+
+
+/*
+*********************************************************************************************************
+*                                                 SHELL
+*
+* Note(s) : (1) Defines the size of the table used to hold the various modules' command tables.  Command
+*               tables are added using the Shell_CmdTblAdd() function.  Once the table is full, it is not
+*               possible to add any more unless Shell_CmdTblRem() is first called.
+*
+*           (2) Defines the maximum number or argument(s) a command may pass on the string holding the
+*               complete command.  The minimum value is 1.
+*
+*           (3) Defines the maximum length for module command name, including the NULL character.
+*********************************************************************************************************
+*/
+
+#define  SHELL_CFG_CMD_TBL_SIZE                            3    /* Cfg Shell cmd tbl size  (see Note #1).               */
+#define  SHELL_CFG_CMD_ARG_NBR_MAX                         5    /* Cfg cmd max nbr of arg  (see Note #2).               */
+
+#define  SHELL_CFG_MODULE_CMD_NAME_LEN_MAX                 6    /* Cfg module cmd name len (See Note #3).               */
+
+
+/*
+*********************************************************************************************************
+*                                                TRACING
+*********************************************************************************************************
+*/
+
+#ifndef  TRACE_LEVEL_OFF
+#define  TRACE_LEVEL_OFF                                  0u
+#endif
+
+#ifndef  TRACE_LEVEL_INFO
+#define  TRACE_LEVEL_INFO                                 1u
+#endif
+
+#ifndef  TRACE_LEVEL_DBG
+#define  TRACE_LEVEL_DBG                                  2u
+#endif
+
+#define  SHELL_TRACE_LEVEL                   TRACE_LEVEL_OFF
+#define  SHELL_TRACE                                  printf
+
+
+/*
+*********************************************************************************************************
+*                                          MODULE END
+*********************************************************************************************************
+*/
+
+#endif

src/APP/Aufgabe1/ps7/core0/cfg/terminal_cfg.h

@@ -0,0 +1,70 @@
+/*
+*********************************************************************************************************
+*                                               uC/Shell
+*                                            Shell utility
+*
+*                             (c) Copyright 2007-2013; Micrium, Inc.; Weston, FL
+*
+*                   All rights reserved.  Protected by international copyright laws.
+*                   Knowledge of the source code may not be used to write a similar
+*                   product.  This file may only be used in accordance with a license
+*                   and should not be redistributed in any way.
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                               TERMINAL
+*
+*                                      CONFIGURATION TEMPLATE FILE
+*
+* Filename      : terminal_cfg.h
+* Version       : V1.03.01
+* Programmer(s) : BAN
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                                           TASKS PRIORITIES
+*********************************************************************************************************
+*/
+
+#define  TERMINAL_OS_CFG_TASK_PRIO                        16u
+
+
+/*
+*********************************************************************************************************
+*                                              STACK SIZES
+*                             Size of the task stacks (# of OS_STK entries)
+*********************************************************************************************************
+*/
+
+#define  TERMINAL_OS_CFG_TASK_STK_SIZE                  1024u
+
+
+/*
+*********************************************************************************************************
+*                                               TERMINAL
+*
+* Note(s) : (1) Defines the maximum length of a command entered on the terminal, in characters.
+*
+*           (2) Defines the maximum path length of the Current Working Directory (CWD).
+*
+*           (3) Enables/disables command history.
+*
+*           (4) Defines the number of items to hold in the command history.
+*
+*           (5) Defines the length of a item in the command history.  If a command is entered into the
+*               terminal that exceeds this length, then only the first characters, up to this number of
+*               characters, will be copied into the command history.
+*********************************************************************************************************
+*/
+
+#define  TERMINAL_CFG_MAX_CMD_LEN                        260u   /* Cfg max cmd  len         (see Note #1).              */
+#define  TERMINAL_CFG_MAX_PATH_LEN                       260u   /* Cfg max path len         (see Note #2).              */
+
+#define  TERMINAL_CFG_HISTORY_EN                 DEF_ENABLED    /* En/dis history           (see Note #3).              */
+#define  TERMINAL_CFG_HISTORY_ITEMS_NBR                   16u   /* Cfg nbr history items    (see Note #4).              */
+#define  TERMINAL_CFG_HISTORY_ITEM_LEN                    64u   /* Cfg history item len     (see Note #5).              */

src/APP/Aufgabe1/ps7/core0/cfg/xparameters.h

@@ -0,0 +1,706 @@
+/******************************************************************/
+
+/* Definition for CPU ID */
+#define XPAR_CPU_ID 0
+
+/* Definitions for peripheral PS7_CORTEXA9_0 */
+#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
+#define XPAR_PS7_CORTEXA9_1_CPU_CLK_FREQ_HZ XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_CORTEXA9_0 */
+#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
+#define XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+
+/******************************************************************/
+
+#undef DEF_DISABLED
+#undef DEF_ENABLED
+#define DEF_ENABLED 1
+#define DEF_DISABLED 0
+
+#include "xparameters_ps.h"
+
+
+
+/******************************************************************/
+
+/* Definitions for driver BRAM */
+#define XPAR_XBRAM_NUM_INSTANCES 1
+
+/* Definitions for peripheral AXI_BRAM_CTRL_0 */
+#define XPAR_AXI_BRAM_CTRL_0_DEVICE_ID 0
+#define XPAR_AXI_BRAM_CTRL_0_DATA_WIDTH 32
+#define XPAR_AXI_BRAM_CTRL_0_ECC 0
+#define XPAR_AXI_BRAM_CTRL_0_FAULT_INJECT 0
+#define XPAR_AXI_BRAM_CTRL_0_CE_FAILING_REGISTERS 0
+#define XPAR_AXI_BRAM_CTRL_0_UE_FAILING_REGISTERS 0
+#define XPAR_AXI_BRAM_CTRL_0_ECC_STATUS_REGISTERS 0
+#define XPAR_AXI_BRAM_CTRL_0_CE_COUNTER_WIDTH 0
+#define XPAR_AXI_BRAM_CTRL_0_ECC_ONOFF_REGISTER 0
+#define XPAR_AXI_BRAM_CTRL_0_ECC_ONOFF_RESET_VALUE 0
+#define XPAR_AXI_BRAM_CTRL_0_WRITE_ACCESS 0
+#define XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR 0x40000000
+#define XPAR_AXI_BRAM_CTRL_0_S_AXI_HIGHADDR 0x40001FFF
+#define XPAR_AXI_BRAM_CTRL_0_S_AXI_CTRL_BASEADDR 0xFFFFFFFF
+#define XPAR_AXI_BRAM_CTRL_0_S_AXI_CTRL_HIGHADDR 0xFFFFFFFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral AXI_BRAM_CTRL_0 */
+#define XPAR_BRAM_0_DEVICE_ID XPAR_AXI_BRAM_CTRL_0_DEVICE_ID
+#define XPAR_BRAM_0_DATA_WIDTH 32
+#define XPAR_BRAM_0_ECC 0
+#define XPAR_BRAM_0_FAULT_INJECT 0
+#define XPAR_BRAM_0_CE_FAILING_REGISTERS 0
+#define XPAR_BRAM_0_UE_FAILING_REGISTERS 0
+#define XPAR_BRAM_0_ECC_STATUS_REGISTERS 0
+#define XPAR_BRAM_0_CE_COUNTER_WIDTH 0
+#define XPAR_BRAM_0_ECC_ONOFF_REGISTER 0
+#define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 0
+#define XPAR_BRAM_0_WRITE_ACCESS 0
+#define XPAR_BRAM_0_BASEADDR 0x40000000
+#define XPAR_BRAM_0_HIGHADDR 0x40001FFF
+
+
+/******************************************************************/
+
+
+/* Definitions for peripheral PS7_DDR_0 */
+#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
+#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver DEVCFG */
+#define XPAR_XDCFG_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_DEV_CFG_0 */
+#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0
+#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000
+#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_DEV_CFG_0 */
+#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
+#define XPAR_XDCFG_0_BASEADDR 0xF8007000
+#define XPAR_XDCFG_0_HIGHADDR 0xF80070FF
+
+
+/******************************************************************/
+
+/* Definitions for driver DMAPS */
+#define XPAR_XDMAPS_NUM_INSTANCES 2
+
+/* Definitions for peripheral PS7_DMA_NS */
+#define XPAR_PS7_DMA_NS_DEVICE_ID 0
+#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
+#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF
+
+
+/* Definitions for peripheral PS7_DMA_S */
+#define XPAR_PS7_DMA_S_DEVICE_ID 1
+#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
+#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_DMA_NS */
+#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
+#define XPAR_XDMAPS_0_BASEADDR 0xF8004000
+#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF
+
+/* Canonical definitions for peripheral PS7_DMA_S */
+#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
+#define XPAR_XDMAPS_1_BASEADDR 0xF8003000
+#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF
+
+
+/******************************************************************/
+
+
+/* Definitions for peripheral PS7_AFI_0 */
+#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
+#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
+
+
+/* Definitions for peripheral PS7_AFI_1 */
+#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000
+#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF
+
+
+/* Definitions for peripheral PS7_AFI_2 */
+#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000
+#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF
+
+
+/* Definitions for peripheral PS7_AFI_3 */
+#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000
+#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
+
+
+/* Definitions for peripheral PS7_DDRC_0 */
+#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
+#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
+
+
+/* Definitions for peripheral PS7_GLOBALTIMER_0 */
+#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200
+#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF
+
+
+/* Definitions for peripheral PS7_GPV_0 */
+#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000
+#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF
+
+
+/* Definitions for peripheral PS7_INTC_DIST_0 */
+#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000
+#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF
+
+
+/* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
+#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
+#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
+
+
+/* Definitions for peripheral PS7_OCMC_0 */
+#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000
+#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF
+
+
+/* Definitions for peripheral PS7_PL310_0 */
+#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000
+#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF
+
+
+/* Definitions for peripheral PS7_PMU_0 */
+#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000
+#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF
+#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000
+#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF
+
+
+/* Definitions for peripheral PS7_QSPI_LINEAR_0 */
+#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
+#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFDFFFFFF
+
+
+/* Definitions for peripheral PS7_RAM_0 */
+#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
+#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
+
+
+/* Definitions for peripheral PS7_RAM_1 */
+#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000
+#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
+
+
+/* Definitions for peripheral PS7_SLCR_0 */
+#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
+#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF
+
+
+/******************************************************************/
+
+/* Definitions for driver GPIO */
+#define XPAR_XGPIO_NUM_INSTANCES 1
+
+/* Definitions for peripheral AXI_GPIO_0 */
+#define XPAR_AXI_GPIO_0_BASEADDR 0x41200000
+#define XPAR_AXI_GPIO_0_HIGHADDR 0x4120FFFF
+#define XPAR_AXI_GPIO_0_DEVICE_ID 0
+#define XPAR_AXI_GPIO_0_INTERRUPT_PRESENT 0
+#define XPAR_AXI_GPIO_0_IS_DUAL 0
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral AXI_GPIO_0 */
+#define XPAR_GPIO_0_BASEADDR 0x41200000
+#define XPAR_GPIO_0_HIGHADDR 0x4120FFFF
+#define XPAR_GPIO_0_DEVICE_ID XPAR_AXI_GPIO_0_DEVICE_ID
+#define XPAR_GPIO_0_INTERRUPT_PRESENT 0
+#define XPAR_GPIO_0_IS_DUAL 0
+
+
+/******************************************************************/
+
+/* Definitions for driver GPIOPS */
+#define XPAR_XGPIOPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_GPIO_0 */
+#define XPAR_PS7_GPIO_0_DEVICE_ID 0
+#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
+#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_GPIO_0 */
+#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
+#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
+#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
+
+
+/******************************************************************/
+
+///* Definitions for driver IICPS */
+//#define XPAR_XIICPS_NUM_INSTANCES 1
+//
+///* Definitions for peripheral PS7_I2C_0 */
+//#define XPAR_PS7_I2C_0_DEVICE_ID 0
+//#define XPAR_PS7_I2C_0_BASEADDR 0xE0004000
+//#define XPAR_PS7_I2C_0_HIGHADDR 0xE0004FFF
+//#define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 111111115
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_I2C_0 */
+#define XPAR_XIICPS_0_DEVICE_ID XPAR_PS7_I2C_0_DEVICE_ID
+#define XPAR_XIICPS_0_BASEADDR 0xE0004000
+#define XPAR_XIICPS_0_HIGHADDR 0xE0004FFF
+#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 111111115
+
+
+/******************************************************************/
+
+/* Definitions for driver QSPIPS */
+#define XPAR_XQSPIPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_QSPI_0 */
+#define XPAR_PS7_QSPI_0_DEVICE_ID 0
+#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000
+#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
+#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000
+#define XPAR_PS7_QSPI_0_QSPI_MODE 2
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_QSPI_0 */
+#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID
+#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000
+#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
+#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000
+#define XPAR_XQSPIPS_0_QSPI_MODE 2
+
+
+/******************************************************************/
+
+/* Definitions for driver SCUWDT */
+#define XPAR_XSCUWDT_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SCUWDT_0 */
+#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
+#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
+#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_SCUWDT_0 */
+#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
+#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
+#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
+
+
+/******************************************************************/
+
+/* Definitions for driver UCOS_EMACPS */
+#define XPAR_UCOS_EMACPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_ETHERNET_0 */
+#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0
+#define XPAR_PS7_ETHERNET_0_BASEADDR 0x00000000
+#define XPAR_PS7_ETHERNET_0_HIGHADDR 0x00000000
+#define XPAR_PS7_ETHERNET_0_CLOCK_FREQ_HZ 0
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_ETHERNET_0 */
+#define XPAR_UCOS_EMACPS_0_NUM_INSTANCES 0
+#define XPAR_UCOS_EMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID
+#define XPAR_UCOS_EMACPS_0_BASEADDR 0x00000000
+#define XPAR_UCOS_EMACPS_0_HIGHADDR 0x00000000
+#define XPAR_UCOS_EMACPS_0_CLOCK_FREQ_HZ 0
+
+
+/******************************************************************/
+
+/* Definitions for driver UCOS_L2CACHEC */
+#define XPAR_UCOS_L2CACHEC_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_L2CACHEC_0 */
+#define XPAR_PS7_L2CACHEC_0_DEVICE_ID 0
+#define XPAR_PS7_L2CACHEC_0_BASEADDR 0xF8F02000
+#define XPAR_PS7_L2CACHEC_0_HIGHADDR 0xF8F02FFF
+
+
+/******************************************************************/
+
+/* Definitions for driver UCOS_SCUC */
+#define XPAR_UCOS_L2CACHEC_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SCUC_0 */
+#define XPAR_PS7_SCUC_0_DEVICE_ID 0
+#define XPAR_PS7_SCUC_0_BASEADDR 0xF8F00000
+#define XPAR_PS7_SCUC_0_HIGHADDR 0xF8F000FC
+
+
+/******************************************************************/
+
+
+/***Definitions for Core_nIRQ/nFIQ interrupts ****/
+/* Definitions for driver UCOS_SCUGIC */
+#define XPAR_XSCUGIC_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SCUGIC_0 */
+#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0
+#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100
+#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FF
+#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_SCUGIC_0 */
+#define XPAR_SCUGIC_0_DEVICE_ID 0
+#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100
+#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FF
+#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000
+
+
+/******************************************************************/
+
+/* Definitions for driver UCOS_SCUTIMER */
+#define XPAR_UCOS_SCUC_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SCUTIMER_0 */
+#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
+#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
+#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F
+
+
+/******************************************************************/
+
+/* Definitions for driver UCOS_SDPS */
+#define XPAR_UCOS_SDPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SD_0 */
+#define XPAR_PS7_SD_0_DEVICE_ID 0
+#define XPAR_PS7_SD_0_BASEADDR 0xE0100000
+#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
+#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_SD_0 */
+#define XPAR_UCOS_SDPS_0_NUM_INSTANCES 0
+#define XPAR_UCOS_SDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID
+#define XPAR_UCOS_SDPS_0_BASEADDR 0xE0100000
+#define XPAR_UCOS_SDPS_0_HIGHADDR 0xE0100FFF
+#define XPAR_UCOS_SDPS_0_SDIO_CLK_FREQ_HZ 50000000
+
+
+/******************************************************************/
+
+///* Definitions for driver UCOS_TTCPS */
+//#define XPAR_UCOS_TTCPS_NUM_INSTANCES 3
+//
+///* Definitions for peripheral PS7_TTC_0 */
+//#define XPAR_PS7_TTC_0_DEVICE_ID 0
+//#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000
+//#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115
+//#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0
+//#define XPAR_PS7_TTC_1_DEVICE_ID 1
+//#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004
+//#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115
+//#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0
+//#define XPAR_PS7_TTC_2_DEVICE_ID 2
+//#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008
+//#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115
+//#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0
+
+
+/******************************************************************/
+
+/* Definitions for driver UCOS_UARTPS */
+#define XPAR_UCOS_UARTPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_UART_1 */
+#define XPAR_PS7_UART_1_DEVICE_ID 0
+#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
+#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
+#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 50000000
+#define XPAR_PS7_UART_1_HAS_MODEM 0
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_UART_1 */
+#define XPAR_UCOS_UARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
+#define XPAR_UCOS_UARTPS_0_BASEADDR 0xE0001000
+#define XPAR_UCOS_UARTPS_0_HIGHADDR 0xE0001FFF
+#define XPAR_UCOS_UARTPS_0_UART_CLK_FREQ_HZ 50000000
+#define XPAR_UCOS_UARTPS_0_HAS_MODEM 0
+
+
+/******************************************************************/
+
+/* Definitions for driver UCOS_USBPS */
+#define XPAR_UCOS_USBPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_USB_0 */
+#define XPAR_PS7_USB_0_DEVICE_ID 0
+#define XPAR_PS7_USB_0_BASEADDR 0xE0002000
+#define XPAR_PS7_USB_0_HIGHADDR 0xE0002FFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_USB_0 */
+#define XPAR_UCOS_USBPS_0_DEVICE_ID XPAR_PS7_USB_0_DEVICE_ID
+#define XPAR_UCOS_USBPS_0_BASEADDR 0xE0002000
+#define XPAR_UCOS_USBPS_0_HIGHADDR 0xE0002FFF
+
+
+/******************************************************************/
+
+/* Definitions for driver XADCPS */
+#define XPAR_XADCPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_XADC_0 */
+#define XPAR_PS7_XADC_0_DEVICE_ID 0
+#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100
+#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_XADC_0 */
+#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
+#define XPAR_XADCPS_0_BASEADDR 0xF8007100
+#define XPAR_XADCPS_0_HIGHADDR 0xF8007120
+
+
+/******************************************************************/
+
+
+//UCOS STDOUT
+#define UCOS_STDOUT_DRIVER UCOS_UART_PS7_UART
+#define UCOS_STDOUT_DEVICE_ID 0
+#define STDOUT_BASEADDRESS
+
+//UCOS Ethernet
+#define UCOS_ETHERNET_DRIVER UCOS_ETHERNET_EMACPS
+
+//UCOS TASK PARAMETERS
+#define UCOS_START_TASK_PRIO 5
+#define UCOS_START_TASK_STACK_SIZE 784
+#define UCOS_START_DEBUG_TRACE DEF_ENABLED
+#define NET_TASK_CFG_RX_PRIO 30
+#define NET_TASK_CFG_RX_STACK_SIZE 3072
+#define NET_TASK_CFG_TXDEALLOC_PRIO 6
+#define NET_TASK_CFG_TXDEALLOC_STACK_SIZE 2048
+#define NET_TASK_CFG_TMR_PRIO 18
+#define NET_TASK_CFG_TMR_STACK_SIZE 2048
+#define HTTPc_OS_CFG_TASK_PRIO 20
+#define HTTPc_OS_CFG_TASK_STK_SIZE 2048
+#define UCOS_HTTPc_OS_CFG_TASK_DELAY 1
+#define UCOS_HTTPc_OS_CFG_MSG_Q_SIZE 5
+#define UCOS_HTTPc_OS_CFG_TIMEOUT 2000
+#define UCOS_HTTPc_OS_CFG_INACTIVITY_TIMEOUT 30
+
+#define UCOS_AMP_MASTER DEF_ENABLED
+
+
+#define UCOS_CFG_INIT_CAN DEF_ENABLED
+#define UCOS_CFG_INIT_NET DEF_ENABLED
+#define UCOS_CFG_INIT_FS DEF_DISABLED
+#define UCOS_CFG_INIT_OPENAMP DEF_DISABLED
+#define UCOS_CFG_INIT_USBD DEF_DISABLED
+#define UCOS_CFG_INIT_USBH DEF_DISABLED
+
+
+#define UCOS_ETHERNET_ADDRESS "10.10.110.2"
+#define UCOS_ETHERNET_GATEWAY "10.10.110.1"
+#define UCOS_ETHERNET_SUBMASK "255.255.255.0"
+#define UCOS_ETHERNET_DHCP DEF_ENABLED
+
+
+#define UCOS_IF_RX_BUF_NBR 12
+#define UCOS_IF_TX_LARGE_BUF_NBR 8
+#define UCOS_IF_TX_SMALL_BUF_NBR 8
+#define UCOS_IF_RX_DESC_NBR 0
+#define UCOS_IF_TX_DESC_NBR 0
+#define UCOS_IF_DEDIC_MEM_ADDR 0
+#define UCOS_IF_DEDIC_MEM_SIZE 0
+#define UCOS_IF_HW_ADDR "50:E5:49:E6:8D:28"
+
+
+#define UCOS_PHY_BUS_ADDR 255
+#define UCOS_PHY_BUS_MODE UCOS_NET_PHY_BUS_MODE_GMII
+#define UCOS_PHY_TYPE UCOS_NET_PHY_TYPE_INT
+#define UCOS_PHY_SPEED UCOS_NET_PHY_SPD_AUTO
+#define UCOS_PHY_DUPLEX UCOS_NET_PHY_DUPLEX_AUTO
+
+
+#define UCOS_USB_DRIVER UCOS_USB_NONE
+#define UCOS_USB_DEVICE_ID 0
+#define UCOS_USB_TYPE UCOS_USB_TYPE_DEVICE
+
+
+#define UCOS_RAMDISK_EN DEF_DISABLED
+#define UCOS_RAMDISK_SIZE 128
+#define UCOS_RAMDISK_SECTOR_SIZE 512
+#define UCOS_RAMDISK_BASE_ADDRESS 0
+
+
+#define UCOS_SDCARD_EN DEF_DISABLED
+
+
+#define XPAR_PS7_ETHERNET_0_INT_SOURCE 54
+#define XPAR_PS7_SD_0_INT_SOURCE 56
+#define XPAR_PS7_UART_1_INT_SOURCE 82
+#define XPAR_PS7_USB_0_INT_SOURCE 53
+
+#define UCOS_ZYNQ_CONFIG_MMU DEF_DISABLED
+#define UCOS_ZYNQ_ENABLE_MMU DEF_DISABLED
+#define UCOS_ZYNQ_CONFIG_CACHES DEF_DISABLED
+#define UCOS_ZYNQ_ENABLE_CACHES DEF_DISABLED
+#define UCOS_ZYNQ_ENABLE_OPTIMS DEF_DISABLED
+#define ZYNQ_ENABLE_EARLY_L1_I_EN DEF_DISABLED
+#define ZYNQ_ENABLE_EARLY_L1_D_EN DEF_DISABLED
+#define UCOS_CPU_TYPE UCOS_CPU_TYPE_PS7
+
+//Parameters added by Kai Gemlau
+#define UCOS_SMP_ENABLE DEF_DISABLED
+
+/******************************************************************/
+
+/* Definitions for driver TTCPS */
+#define XPAR_XTTCPS_NUM_INSTANCES 3U
+
+/* Definitions for peripheral PS7_TTC_0 */
+#define XPAR_PS7_TTC_0_DEVICE_ID 0U
+#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000U
+#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115U
+#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0U
+#define XPAR_PS7_TTC_1_DEVICE_ID 1U
+#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004U
+#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115U
+#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0U
+#define XPAR_PS7_TTC_2_DEVICE_ID 2U
+#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008U
+#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115U
+#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0U
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_TTC_0 */
+#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PS7_TTC_0_DEVICE_ID
+#define XPAR_XTTCPS_0_BASEADDR 0xF8001000U
+#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 111111115U
+#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0U
+
+#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PS7_TTC_1_DEVICE_ID
+#define XPAR_XTTCPS_1_BASEADDR 0xF8001004U
+#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 111111115U
+#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0U
+
+#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PS7_TTC_2_DEVICE_ID
+#define XPAR_XTTCPS_2_BASEADDR 0xF8001008U
+#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 111111115U
+#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0U
+
+
+/******************************************************************/
+
+/******************************************************************/
+/* Definitions for driver GPIOPS */
+#define XPAR_XGPIOPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_GPIO_0 */
+#define XPAR_PS7_GPIO_0_DEVICE_ID 0
+#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
+#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_GPIO_0 */
+#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
+#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
+#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver IICPS */
+#define XPAR_XIICPS_NUM_INSTANCES 2
+
+/* Definitions for peripheral PS7_I2C_0 */
+#define XPAR_PS7_I2C_0_DEVICE_ID 0
+#define XPAR_PS7_I2C_0_BASEADDR 0xE0004000
+#define XPAR_PS7_I2C_0_HIGHADDR 0xE0004FFF
+#define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 111111115
+
+
+/* Definitions for peripheral PS7_I2C_1 */
+#define XPAR_PS7_I2C_1_DEVICE_ID 1
+#define XPAR_PS7_I2C_1_BASEADDR 0xE0005000
+#define XPAR_PS7_I2C_1_HIGHADDR 0xE0005FFF
+#define XPAR_PS7_I2C_1_I2C_CLK_FREQ_HZ 111111115
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_I2C_0 */
+#define XPAR_XIICPS_0_DEVICE_ID XPAR_PS7_I2C_0_DEVICE_ID
+#define XPAR_XIICPS_0_BASEADDR 0xE0004000
+#define XPAR_XIICPS_0_HIGHADDR 0xE0004FFF
+#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 111111115
+
+/* Canonical definitions for peripheral PS7_I2C_1 */
+#define XPAR_XIICPS_1_DEVICE_ID XPAR_PS7_I2C_1_DEVICE_ID
+#define XPAR_XIICPS_1_BASEADDR 0xE0005000
+#define XPAR_XIICPS_1_HIGHADDR 0xE0005FFF
+#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 111111115
+
+
+/******************************************************************/
+
+/* Definitions for driver UARTPS */
+#define XPAR_XUARTPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_UART_1 */
+#define XPAR_PS7_UART_1_DEVICE_ID 0
+#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
+#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
+#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 50000000
+#define XPAR_PS7_UART_1_HAS_MODEM 0
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_UART_1 */
+#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
+#define XPAR_XUARTPS_0_BASEADDR 0xE0001000
+#define XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF
+#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 50000000
+#define XPAR_XUARTPS_0_HAS_MODEM 0
+
+
+/******************************************************************/

src/APP/Aufgabe1/ps7/core0/cfg/xparameters_ps.h

@@ -0,0 +1,325 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xparameters_ps.h
+*
+* This file contains the address definitions for the hard peripherals
+* attached to the ARM Cortex A9 core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 02/01/10 Initial version
+* 3.04a sdm     02/02/12 Removed some of the defines as they are being generated through
+*                        driver tcl
+* 5.0	pkp		01/16/15 Added interrupt ID definition of ttc for TEST APP
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XPARAMETERS_PS_H_
+#define _XPARAMETERS_PS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock
+ */
+
+/* Canonical definitions for DDR MEMORY */
+#define XPAR_DDR_MEM_BASEADDR		0x00000000U
+#define XPAR_DDR_MEM_HIGHADDR		0x3FFFFFFFU
+
+/* Canonical definitions for Interrupts  */
+#define XPAR_XUARTPS_0_INTR		XPS_UART0_INT_ID
+#define XPAR_XUARTPS_1_INTR		XPS_UART1_INT_ID
+#define XPAR_XUSBPS_0_INTR		XPS_USB0_INT_ID
+#define XPAR_XUSBPS_1_INTR		XPS_USB1_INT_ID
+#define XPAR_XIICPS_0_INTR		XPS_I2C0_INT_ID
+#define XPAR_XIICPS_1_INTR		XPS_I2C1_INT_ID
+#define XPAR_XSPIPS_0_INTR		XPS_SPI0_INT_ID
+#define XPAR_XSPIPS_1_INTR		XPS_SPI1_INT_ID
+#define XPAR_XCANPS_0_INTR		XPS_CAN0_INT_ID
+#define XPAR_XCANPS_1_INTR		XPS_CAN1_INT_ID
+#define XPAR_XGPIOPS_0_INTR		XPS_GPIO_INT_ID
+#define XPAR_XEMACPS_0_INTR		XPS_GEM0_INT_ID
+#define XPAR_XEMACPS_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
+#define XPAR_XEMACPS_1_INTR		XPS_GEM1_INT_ID
+#define XPAR_XEMACPS_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
+#define XPAR_XSDIOPS_0_INTR		XPS_SDIO0_INT_ID
+#define XPAR_XQSPIPS_0_INTR		XPS_QSPI_INT_ID
+#define XPAR_XSDIOPS_1_INTR		XPS_SDIO1_INT_ID
+#define XPAR_XWDTPS_0_INTR		XPS_WDT_INT_ID
+#define XPAR_XDCFG_0_INTR		XPS_DVC_INT_ID
+#define XPAR_SCUTIMER_INTR		XPS_SCU_TMR_INT_ID
+#define XPAR_SCUWDT_INTR		XPS_SCU_WDT_INT_ID
+#define XPAR_XTTCPS_0_INTR		XPS_TTC0_0_INT_ID
+#define XPAR_XTTCPS_1_INTR		XPS_TTC0_1_INT_ID
+#define XPAR_XTTCPS_2_INTR		XPS_TTC0_2_INT_ID
+#define XPAR_XTTCPS_3_INTR		XPS_TTC1_0_INT_ID
+#define XPAR_XTTCPS_4_INTR		XPS_TTC1_1_INT_ID
+#define XPAR_XTTCPS_5_INTR		XPS_TTC1_2_INT_ID
+#define XPAR_XDMAPS_0_FAULT_INTR	XPS_DMA0_ABORT_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_0	XPS_DMA0_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_1	XPS_DMA1_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_2	XPS_DMA2_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_3	XPS_DMA3_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_4	XPS_DMA4_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_5	XPS_DMA5_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_6	XPS_DMA6_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_7	XPS_DMA7_INT_ID
+
+
+#define XPAR_XQSPIPS_0_LINEAR_BASEADDR	XPS_QSPI_LINEAR_BASEADDR
+#define XPAR_XPARPORTPS_CTRL_BASEADDR	XPS_PARPORT_CRTL_BASEADDR
+
+
+
+/* Canonical definitions for DMAC */
+
+
+/* Canonical definitions for WDT */
+
+/* Canonical definitions for SLCR */
+#define XPAR_XSLCR_NUM_INSTANCES	1U
+#define XPAR_XSLCR_0_DEVICE_ID		0U
+#define XPAR_XSLCR_0_BASEADDR		XPS_SYS_CTRL_BASEADDR
+
+/* Canonical definitions for SCU GIC */
+#define XPAR_SCUGIC_NUM_INSTANCES	1U
+#define XPAR_SCUGIC_SINGLE_DEVICE_ID	0U
+#define XPAR_SCUGIC_CPU_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00000100U)
+#define XPAR_SCUGIC_DIST_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00001000U)
+#define XPAR_SCUGIC_ACK_BEFORE		0U
+
+/* Canonical definitions for Global Timer */
+#define XPAR_GLOBAL_TMR_NUM_INSTANCES	1U
+#define XPAR_GLOBAL_TMR_DEVICE_ID	0U
+#define XPAR_GLOBAL_TMR_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00000200U)
+#define XPAR_GLOBAL_TMR_INTR		XPS_GLOBAL_TMR_INT_ID
+
+
+/* Xilinx Parallel Flash Library (XilFlash) User Settings */
+#define XPAR_AXI_EMC
+
+
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock. These have been put for bacwards compatibilty
+ */
+
+#define XPS_PERIPHERAL_BASEADDR		0xE0000000U
+#define XPS_UART0_BASEADDR		0xE0000000U
+#define XPS_UART1_BASEADDR		0xE0001000U
+#define XPS_USB0_BASEADDR		0xE0002000U
+#define XPS_USB1_BASEADDR		0xE0003000U
+#define XPS_I2C0_BASEADDR		0xE0004000U
+#define XPS_I2C1_BASEADDR		0xE0005000U
+#define XPS_SPI0_BASEADDR		0xE0006000U
+#define XPS_SPI1_BASEADDR		0xE0007000U
+#define XPS_CAN0_BASEADDR		0xE0008000U
+#define XPS_CAN1_BASEADDR		0xE0009000U
+#define XPS_GPIO_BASEADDR		0xE000A000U
+#define XPS_GEM0_BASEADDR		0xE000B000U
+#define XPS_GEM1_BASEADDR		0xE000C000U
+#define XPS_QSPI_BASEADDR		0xE000D000U
+#define XPS_PARPORT_CRTL_BASEADDR	0xE000E000U
+#define XPS_SDIO0_BASEADDR		0xE0100000U
+#define XPS_SDIO1_BASEADDR		0xE0101000U
+#define XPS_IOU_BUS_CFG_BASEADDR	0xE0200000U
+#define XPS_NAND_BASEADDR		0xE1000000U
+#define XPS_PARPORT0_BASEADDR		0xE2000000U
+#define XPS_PARPORT1_BASEADDR		0xE4000000U
+#define XPS_QSPI_LINEAR_BASEADDR	0xFC000000U
+#define XPS_SYS_CTRL_BASEADDR		0xF8000000U	/* AKA SLCR */
+#define XPS_TTC0_BASEADDR		0xF8001000U
+#define XPS_TTC1_BASEADDR		0xF8002000U
+#define XPS_DMAC0_SEC_BASEADDR		0xF8003000U
+#define XPS_DMAC0_NON_SEC_BASEADDR	0xF8004000U
+#define XPS_WDT_BASEADDR		0xF8005000U
+#define XPS_DDR_CTRL_BASEADDR		0xF8006000U
+#define XPS_DEV_CFG_APB_BASEADDR	0xF8007000U
+#define XPS_AFI0_BASEADDR		0xF8008000U
+#define XPS_AFI1_BASEADDR		0xF8009000U
+#define XPS_AFI2_BASEADDR		0xF800A000U
+#define XPS_AFI3_BASEADDR		0xF800B000U
+#define XPS_OCM_BASEADDR		0xF800C000U
+#define XPS_EFUSE_BASEADDR		0xF800D000U
+#define XPS_CORESIGHT_BASEADDR		0xF8800000U
+#define XPS_TOP_BUS_CFG_BASEADDR	0xF8900000U
+#define XPS_SCU_PERIPH_BASE		0xF8F00000U
+#define XPS_L2CC_BASEADDR		0xF8F02000U
+#define XPS_SAM_RAM_BASEADDR		0xFFFC0000U
+#define XPS_FPGA_AXI_S0_BASEADDR	0x40000000U
+#define XPS_FPGA_AXI_S1_BASEADDR	0x80000000U
+#define XPS_IOU_S_SWITCH_BASEADDR	0xE0000000U
+#define XPS_PERIPH_APB_BASEADDR		0xF8000000U
+
+/* Shared Peripheral Interrupts (SPI) */
+#define XPS_CORE_PARITY0_INT_ID		32U
+#define XPS_CORE_PARITY1_INT_ID		33U
+#define XPS_L2CC_INT_ID			34U
+#define XPS_OCMINTR_INT_ID		35U
+#define XPS_ECC_INT_ID			36U
+#define XPS_PMU0_INT_ID			37U
+#define XPS_PMU1_INT_ID			38U
+#define XPS_SYSMON_INT_ID		39U
+#define XPS_DVC_INT_ID			40U
+#define XPS_WDT_INT_ID			41U
+#define XPS_TTC0_0_INT_ID		42U
+#define XPS_TTC0_1_INT_ID		43U
+#define XPS_TTC0_2_INT_ID 		44U
+#define XPS_DMA0_ABORT_INT_ID		45U
+#define XPS_DMA0_INT_ID			46U
+#define XPS_DMA1_INT_ID			47U
+#define XPS_DMA2_INT_ID			48U
+#define XPS_DMA3_INT_ID			49U
+#define XPS_SMC_INT_ID			50U
+#define XPS_QSPI_INT_ID			51U
+#define XPS_GPIO_INT_ID			52U
+#define XPS_USB0_INT_ID			53U
+#define XPS_GEM0_INT_ID			54U
+#define XPS_GEM0_WAKE_INT_ID		55U
+#define XPS_SDIO0_INT_ID		56U
+#define XPS_I2C0_INT_ID			57U
+#define XPS_SPI0_INT_ID			58U
+#define XPS_UART0_INT_ID		59U
+#define XPS_CAN0_INT_ID			60U
+#define XPS_FPGA0_INT_ID		61U
+#define XPS_FPGA1_INT_ID		62U
+#define XPS_FPGA2_INT_ID		63U
+#define XPS_FPGA3_INT_ID		64U
+#define XPS_FPGA4_INT_ID		65U
+#define XPS_FPGA5_INT_ID		66U
+#define XPS_FPGA6_INT_ID		67U
+#define XPS_FPGA7_INT_ID		68U
+#define XPS_TTC1_0_INT_ID		69U
+#define XPS_TTC1_1_INT_ID		70U
+#define XPS_TTC1_2_INT_ID		71U
+#define XPS_DMA4_INT_ID			72U
+#define XPS_DMA5_INT_ID			73U
+#define XPS_DMA6_INT_ID			74U
+#define XPS_DMA7_INT_ID			75U
+#define XPS_USB1_INT_ID			76U
+#define XPS_GEM1_INT_ID			77U
+#define XPS_GEM1_WAKE_INT_ID		78U
+#define XPS_SDIO1_INT_ID		79U
+#define XPS_I2C1_INT_ID			80U
+#define XPS_SPI1_INT_ID			81U
+#define XPS_UART1_INT_ID		82U
+#define XPS_CAN1_INT_ID			83U
+#define XPS_FPGA8_INT_ID		84U
+#define XPS_FPGA9_INT_ID		85U
+#define XPS_FPGA10_INT_ID		86U
+#define XPS_FPGA11_INT_ID		87U
+#define XPS_FPGA12_INT_ID		88U
+#define XPS_FPGA13_INT_ID		89U
+#define XPS_FPGA14_INT_ID		90U
+#define XPS_FPGA15_INT_ID		91U
+
+/* Private Peripheral Interrupts (PPI) */
+#define XPS_GLOBAL_TMR_INT_ID		27U	/* SCU Global Timer interrupt */
+#define XPS_FIQ_INT_ID			28U	/* FIQ from FPGA fabric */
+#define XPS_SCU_TMR_INT_ID		29U	/* SCU Private Timer interrupt */
+#define XPS_SCU_WDT_INT_ID		30U	/* SCU Private WDT interrupt */
+#define XPS_IRQ_INT_ID			31U	/* IRQ from FPGA fabric */
+
+
+/* REDEFINES for TEST APP */
+/* Definitions for UART */
+#define XPAR_PS7_UART_0_INTR		XPS_UART0_INT_ID
+#define XPAR_PS7_UART_1_INTR		XPS_UART1_INT_ID
+#define XPAR_PS7_USB_0_INTR		XPS_USB0_INT_ID
+#define XPAR_PS7_USB_1_INTR		XPS_USB1_INT_ID
+#define XPAR_PS7_I2C_0_INTR		XPS_I2C0_INT_ID
+#define XPAR_PS7_I2C_1_INTR		XPS_I2C1_INT_ID
+#define XPAR_PS7_SPI_0_INTR		XPS_SPI0_INT_ID
+#define XPAR_PS7_SPI_1_INTR		XPS_SPI1_INT_ID
+#define XPAR_PS7_CAN_0_INTR		XPS_CAN0_INT_ID
+#define XPAR_PS7_CAN_1_INTR		XPS_CAN1_INT_ID
+#define XPAR_PS7_GPIO_0_INTR		XPS_GPIO_INT_ID
+#define XPAR_PS7_ETHERNET_0_INTR	XPS_GEM0_INT_ID
+#define XPAR_PS7_ETHERNET_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_1_INTR	XPS_GEM1_INT_ID
+#define XPAR_PS7_ETHERNET_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
+#define XPAR_PS7_QSPI_0_INTR		XPS_QSPI_INT_ID
+#define XPAR_PS7_WDT_0_INTR		XPS_WDT_INT_ID
+#define XPAR_PS7_SCUWDT_0_INTR		XPS_SCU_WDT_INT_ID
+#define XPAR_PS7_SCUTIMER_0_INTR	XPS_SCU_TMR_INT_ID
+#define XPAR_PS7_XADC_0_INTR		XPS_SYSMON_INT_ID
+#define XPAR_PS7_TTC_0_INTR         XPS_TTC0_0_INT_ID
+#define XPAR_PS7_TTC_1_INTR         XPS_TTC0_1_INT_ID
+#define XPAR_PS7_TTC_2_INTR         XPS_TTC0_2_INT_ID
+#define XPAR_PS7_TTC_3_INTR         XPS_TTC1_0_INT_ID
+#define XPAR_PS7_TTC_4_INTR         XPS_TTC1_1_INT_ID
+#define XPAR_PS7_TTC_5_INTR         XPS_TTC1_2_INT_ID
+
+#define XPAR_XADCPS_INT_ID		XPS_SYSMON_INT_ID
+
+/* For backwards compatibilty */
+#define XPAR_XUARTPS_0_CLOCK_HZ		XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
+#define XPAR_XUARTPS_1_CLOCK_HZ		XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
+#define XPAR_XTTCPS_0_CLOCK_HZ		XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_1_CLOCK_HZ		XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_2_CLOCK_HZ		XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_3_CLOCK_HZ		XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_4_CLOCK_HZ		XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_5_CLOCK_HZ		XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
+#define XPAR_XIICPS_0_CLOCK_HZ		XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
+#define XPAR_XIICPS_1_CLOCK_HZ		XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
+
+#define XPAR_XQSPIPS_0_CLOCK_HZ		XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
+
+#define XPAR_SCUTIMER_DEVICE_ID		0U
+#define XPAR_SCUWDT_DEVICE_ID		0U
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */

src/APP/Aufgabe1/ps7/core0/linker/lscript.ld

@@ -0,0 +1,291 @@
+/*******************************************************************/
+/*                                                                 */
+/* This file is automatically generated by linker script generator.*/
+/*                                                                 */
+/* Version:                                 */
+/*                                                                 */
+/* Copyright (c) 2010-2016 Xilinx, Inc.  All rights reserved.      */
+/*                                                                 */
+/* Description : Cortex-A9 Linker Script                          */
+/*                                                                 */
+/*******************************************************************/
+
+_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
+_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
+
+_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
+_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
+_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
+_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
+_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
+
+/* Define Memories in the system */
+
+MEMORY
+{
+   axi_bram_ctrl_0_Mem0 : ORIGIN = 0x40000000, LENGTH = 0x2000
+   ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x3FF00000
+   ps7_qspi_linear_0 : ORIGIN = 0xFC000000, LENGTH = 0x2000000
+   ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000
+   ps7_ram_1 : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00
+   ps7_ddr_core_0 : ORIGIN = 0x100000, LENGTH = 0x700000
+   ps7_ddr_core_1 : ORIGIN = 0x800000, LENGTH = 0x800000
+}
+
+/* Specify the default entry point to the program */
+
+ENTRY(_vector_table)
+
+/* Define the sections, and where they are mapped in memory */
+
+SECTIONS
+{
+.text : {
+   KEEP (*(.vectors))
+   *(.boot)
+   *(.text)
+   *(.text.*)
+   *(.gnu.linkonce.t.*)
+   *(.plt)
+   *(.gnu_warning)
+   *(.gcc_execpt_table)
+   *(.glue_7)
+   *(.glue_7t)
+   *(.vfp11_veneer)
+   *(.ARM.extab)
+   *(.gnu.linkonce.armextab.*)
+} > ps7_ddr_core_0
+
+.init : {
+   KEEP (*(.init))
+} > ps7_ddr_core_0
+
+.fini : {
+   KEEP (*(.fini))
+} > ps7_ddr_core_0
+
+.rodata : {
+   __rodata_start = .;
+   *(.rodata)
+   *(.rodata.*)
+   *(.gnu.linkonce.r.*)
+   __rodata_end = .;
+} > ps7_ddr_core_0
+
+.rodata1 : {
+   __rodata1_start = .;
+   *(.rodata1)
+   *(.rodata1.*)
+   __rodata1_end = .;
+} > ps7_ddr_core_0
+
+.sdata2 : {
+   __sdata2_start = .;
+   *(.sdata2)
+   *(.sdata2.*)
+   *(.gnu.linkonce.s2.*)
+   __sdata2_end = .;
+} > ps7_ddr_core_0
+
+.sbss2 : {
+   __sbss2_start = .;
+   *(.sbss2)
+   *(.sbss2.*)
+   *(.gnu.linkonce.sb2.*)
+   __sbss2_end = .;
+} > ps7_ddr_core_0
+
+.data : {
+   __data_start = .;
+   *(.data)
+   *(.data.*)
+   *(.gnu.linkonce.d.*)
+   *(.jcr)
+   *(.got)
+   *(.got.plt)
+   __data_end = .;
+} > ps7_ddr_core_0
+
+.data1 : {
+   __data1_start = .;
+   *(.data1)
+   *(.data1.*)
+   __data1_end = .;
+} > ps7_ddr_core_0
+
+.got : {
+   *(.got)
+} > ps7_ddr_core_0
+
+.ctors : {
+   __CTOR_LIST__ = .;
+   ___CTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.ctors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
+   KEEP (*(SORT(.ctors.*)))
+   KEEP (*(.ctors))
+   __CTOR_END__ = .;
+   ___CTORS_END___ = .;
+} > ps7_ddr_core_0
+
+.dtors : {
+   __DTOR_LIST__ = .;
+   ___DTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.dtors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
+   KEEP (*(SORT(.dtors.*)))
+   KEEP (*(.dtors))
+   __DTOR_END__ = .;
+   ___DTORS_END___ = .;
+} > ps7_ddr_core_0
+
+.fixup : {
+   __fixup_start = .;
+   *(.fixup)
+   __fixup_end = .;
+} > ps7_ddr_core_0
+
+.eh_frame : {
+   *(.eh_frame)
+} > ps7_ddr_core_0
+
+.eh_framehdr : {
+   __eh_framehdr_start = .;
+   *(.eh_framehdr)
+   __eh_framehdr_end = .;
+} > ps7_ddr_core_0
+
+.gcc_except_table : {
+   *(.gcc_except_table)
+} > ps7_ddr_core_0
+
+.mmu_tbl (ALIGN(16384)) : {
+   __mmu_tbl_start = .;
+   *(.mmu_tbl)
+   __mmu_tbl_end = .;
+} > ps7_ddr_core_0
+
+.ARM.exidx : {
+   __exidx_start = .;
+   *(.ARM.exidx*)
+   *(.gnu.linkonce.armexidix.*.*)
+   __exidx_end = .;
+} > ps7_ddr_core_0
+
+.preinit_array : {
+   __preinit_array_start = .;
+   KEEP (*(SORT(.preinit_array.*)))
+   KEEP (*(.preinit_array))
+   __preinit_array_end = .;
+} > ps7_ddr_core_0
+
+.init_array : {
+   __init_array_start = .;
+   KEEP (*(SORT(.init_array.*)))
+   KEEP (*(.init_array))
+   __init_array_end = .;
+} > ps7_ddr_core_0
+
+.fini_array : {
+   __fini_array_start = .;
+   KEEP (*(SORT(.fini_array.*)))
+   KEEP (*(.fini_array))
+   __fini_array_end = .;
+} > ps7_ddr_core_0
+
+.ARM.attributes : {
+   __ARM.attributes_start = .;
+   *(.ARM.attributes)
+   __ARM.attributes_end = .;
+} > ps7_ddr_core_0
+
+.sdata : {
+   __sdata_start = .;
+   *(.sdata)
+   *(.sdata.*)
+   *(.gnu.linkonce.s.*)
+   __sdata_end = .;
+} > ps7_ddr_core_0
+
+.sbss (NOLOAD) : {
+   __sbss_start = .;
+   *(.sbss)
+   *(.sbss.*)
+   *(.gnu.linkonce.sb.*)
+   __sbss_end = .;
+} > ps7_ddr_core_0
+
+.tdata : {
+   __tdata_start = .;
+   *(.tdata)
+   *(.tdata.*)
+   *(.gnu.linkonce.td.*)
+   __tdata_end = .;
+} > ps7_ddr_core_0
+
+.tbss : {
+   __tbss_start = .;
+   *(.tbss)
+   *(.tbss.*)
+   *(.gnu.linkonce.tb.*)
+   __tbss_end = .;
+} > ps7_ddr_core_0
+
+.bss (NOLOAD) : {
+   __bss_start = .;
+   *(.bss)
+   *(.bss.*)
+   *(.gnu.linkonce.b.*)
+   *(COMMON)
+   __bss_end = .;
+} > ps7_ddr_core_0
+
+_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
+
+_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
+
+/* Generate Stack and Heap definitions */
+
+.heap (NOLOAD) : {
+   . = ALIGN(16);
+   _heap = .;
+   HeapBase = .;
+   _heap_start = .;
+   . += _HEAP_SIZE;
+   _heap_end = .;
+   HeapLimit = .;
+} > ps7_ddr_core_0
+
+.stack (NOLOAD) : {
+   . = ALIGN(16);
+   _stack_end = .;
+   . += _STACK_SIZE;
+   . = ALIGN(16);
+   _stack = .;
+   __stack = _stack;
+   . = ALIGN(16);
+   _irq_stack_end = .;
+   . += _IRQ_STACK_SIZE;
+   . = ALIGN(16);
+   __irq_stack = .;
+   _supervisor_stack_end = .;
+   . += _SUPERVISOR_STACK_SIZE;
+   . = ALIGN(16);
+   __supervisor_stack = .;
+   _abort_stack_end = .;
+   . += _ABORT_STACK_SIZE;
+   . = ALIGN(16);
+   __abort_stack = .;
+   _fiq_stack_end = .;
+   . += _FIQ_STACK_SIZE;
+   . = ALIGN(16);
+   __fiq_stack = .;
+   _undef_stack_end = .;
+   . += _UNDEF_STACK_SIZE;
+   . = ALIGN(16);
+   __undef_stack = .;
+} > ps7_ddr_core_0
+
+_end = .;
+}
+

src/APP/Aufgabe1/ps7/core0/main.c

@@ -0,0 +1,23 @@
+#include <mmu.h>
+#include <stdio.h>
+#include "ucos_uartps.h"
+#include "ucos_ii.h"
+#include "ucos_bsp.h"
+#include "xil_testmem.h"
+#include "xil_printf.h"
+
+void InitDoneCallback(void * p_arg){
+	(void) p_arg;
+	while(1){
+		OSTimeDly(OS_TICK_STEP_EN * 5);
+		UCOS_Print("I'LL BE BACK!\r\n");
+	}
+}
+
+int main(void) {
+
+	MMUInit();
+	UCOSStartup(InitDoneCallback);
+	//this should never been reached
+	while (1);
+}

src/APP/Aufgabe1/ps7/core0/src/app_hooks.c

@@ -0,0 +1,259 @@
+/*
+*********************************************************************************************************
+*                                            EXAMPLE CODE
+*
+*               This file is provided as an example on how to use Micrium products.
+*
+*               Please feel free to use any application code labeled as 'EXAMPLE CODE' in
+*               your application products.  Example code may be used as is, in whole or in
+*               part, or may be used as a reference only. This file can be modified as
+*               required to meet the end-product requirements.
+*
+*               Please help us continue to provide the Embedded community with the finest
+*               software available.  Your honesty is greatly appreciated.
+*
+*               You can find our product's user manual, API reference, release notes and
+*               more information at https://doc.micrium.com.
+*               You can contact us at www.micrium.com.
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                             uC/OS-II
+*                                         Application Hooks
+*
+* Filename      : app_hooks.c
+* Version       : V1.00
+* Programmer(s) : FT
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                                             INCLUDE FILES
+*********************************************************************************************************
+*/
+
+#include  <ucos_ii.h>
+
+
+/*
+*********************************************************************************************************
+*                                       EXTERN  GLOBAL VARIABLES
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                           LOCAL CONSTANTS
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                          LOCAL DATA TYPES
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                                            LOCAL TABLES
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                       LOCAL GLOBAL VARIABLES
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                      LOCAL FUNCTION PROTOTYPES
+*********************************************************************************************************
+*/
+
+
+
+/*
+**********************************************************************************************************
+**********************************************************************************************************
+**                                        GLOBAL FUNCTIONS
+**********************************************************************************************************
+**********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+**                                         uC/OS-II APP HOOKS
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#if (OS_APP_HOOKS_EN > 0)
+
+/*
+*********************************************************************************************************
+*                                      TASK CREATION HOOK (APPLICATION)
+*
+* Description : This function is called when a task is created.
+*
+* Argument(s) : ptcb   is a pointer to the task control block of the task being created.
+*
+* Note(s)     : (1) Interrupts are disabled during this call.
+*********************************************************************************************************
+*/
+
+void  App_TaskCreateHook (OS_TCB *ptcb)
+{
+#if (APP_CFG_PROBE_OS_PLUGIN_EN == DEF_ENABLED) && (OS_PROBE_HOOKS_EN > 0)
+    OSProbe_TaskCreateHook(ptcb);
+#endif
+}
+
+/*
+*********************************************************************************************************
+*                                    TASK DELETION HOOK (APPLICATION)
+*
+* Description : This function is called when a task is deleted.
+*
+* Argument(s) : ptcb   is a pointer to the task control block of the task being deleted.
+*
+* Note(s)     : (1) Interrupts are disabled during this call.
+*********************************************************************************************************
+*/
+
+void  App_TaskDelHook (OS_TCB *ptcb)
+{
+    (void)ptcb;
+}
+
+/*
+*********************************************************************************************************
+*                                      IDLE TASK HOOK (APPLICATION)
+*
+* Description : This function is called by OSTaskIdleHook(), which is called by the idle task.  This hook
+*               has been added to allow you to do such things as STOP the CPU to conserve power.
+*
+* Argument(s) : none.
+*
+* Note(s)     : (1) Interrupts are enabled during this call.
+*********************************************************************************************************
+*/
+
+#if OS_VERSION >= 251
+void  App_TaskIdleHook (void)
+{
+}
+#endif
+
+/*
+*********************************************************************************************************
+*                                        STATISTIC TASK HOOK (APPLICATION)
+*
+* Description : This function is called by OSTaskStatHook(), which is called every second by uC/OS-II's
+*               statistics task.  This allows your application to add functionality to the statistics task.
+*
+* Argument(s) : none.
+*********************************************************************************************************
+*/
+
+void  App_TaskStatHook (void)
+{
+}
+
+/*
+*********************************************************************************************************
+*                                            TASK RETURN HOOK (APPLICATION)
+*
+* Description: This function is called if a task accidentally returns.  In other words, a task should
+*              either be an infinite loop or delete itself when done.
+*
+* Arguments  : ptcb      is a pointer to the task control block of the task that is returning.
+*
+* Note(s)    : none
+*********************************************************************************************************
+*/
+
+
+#if OS_VERSION >= 289
+void  App_TaskReturnHook (OS_TCB  *ptcb)
+{
+    (void)ptcb;
+}
+#endif
+
+/*
+*********************************************************************************************************
+*                                        TASK SWITCH HOOK (APPLICATION)
+*
+* Description : This function is called when a task switch is performed.  This allows you to perform other
+*               operations during a context switch.
+*
+* Argument(s) : none.
+*
+* Note(s)     : (1) Interrupts are disabled during this call.
+*
+*               (2) It is assumed that the global pointer 'OSTCBHighRdy' points to the TCB of the task that
+*                   will be 'switched in' (i.e. the highest priority task) and, 'OSTCBCur' points to the
+*                  task being switched out (i.e. the preempted task).
+*********************************************************************************************************
+*/
+
+#if OS_TASK_SW_HOOK_EN > 0
+void  App_TaskSwHook (void)
+{
+#if (APP_CFG_PROBE_OS_PLUGIN_EN > 0) && (OS_PROBE_HOOKS_EN > 0)
+    OSProbe_TaskSwHook();
+#endif
+}
+#endif
+
+/*
+*********************************************************************************************************
+*                                     OS_TCBInit() HOOK (APPLICATION)
+*
+* Description : This function is called by OSTCBInitHook(), which is called by OS_TCBInit() after setting
+*               up most of the TCB.
+*
+* Argument(s) : ptcb    is a pointer to the TCB of the task being created.
+*
+* Note(s)     : (1) Interrupts may or may not be ENABLED during this call.
+*********************************************************************************************************
+*/
+
+#if OS_VERSION >= 204
+void  App_TCBInitHook (OS_TCB *ptcb)
+{
+    (void)ptcb;
+}
+#endif
+
+/*
+*********************************************************************************************************
+*                                        TICK HOOK (APPLICATION)
+*
+* Description : This function is called every tick.
+*
+* Argument(s) : none.
+*
+* Note(s)     : (1) Interrupts may or may not be ENABLED during this call.
+*********************************************************************************************************
+*/
+
+#if OS_TIME_TICK_HOOK_EN > 0
+void  App_TimeTickHook (void)
+{
+#if (APP_CFG_PROBE_OS_PLUGIN_EN == DEF_ENABLED) && (OS_PROBE_HOOKS_EN > 0)
+    OSProbe_TickHook();
+#endif
+}
+#endif
+#endif

src/APP/Aufgabe1/ps7/core0/src/uartps_cfg.c

@@ -0,0 +1,17 @@
+
+#include "ucos_uartps.h"
+#include "xparameters.h"
+#include "xparameters_ps.h"
+
+/*
+ * The uart configuration table for devices
+ */
+UCOS_UARTPS_Config UCOS_UARTPS_ConfigTable[] = {
+		{
+			XPAR_PS7_UART_1_DEVICE_ID,
+			XPAR_PS7_UART_1_BASEADDR,
+			XPAR_PS7_UART_1_UART_CLK_FREQ_HZ,
+			XPAR_PS7_UART_1_HAS_MODEM,
+			XPAR_PS7_UART_1_INT_SOURCE
+		}
+};

src/APP/Aufgabe2/ps7/core0/build/config.mk

@@ -0,0 +1,11 @@
+#µController dependent flags
+MCFLAGS =-mcpu=cortex-a9 -march=armv7-a -mthumb -mthumb-interwork -mfloat-abi=softfp -mfpu=neon
+#Optimization
+OPTIMIZE=-O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections
+
+#Debug Level
+DEBUG   =-g3
+
+#Linker flags
+LDFLAGS  = -nostartfiles -Xlinker --gc-sections 
+

src/APP/Aufgabe2/ps7/core0/build/includes.mk

@@ -0,0 +1,29 @@
+
+INC += -I"$(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/cfg/"
+
+INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Ports/ARM-Cortex-A/Generic/GNU/"
+INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/ARM-Cortex-A/GNU/"
+INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/"
+INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-Common" 
+INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II" 
+INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Source" 
+INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-LIB" 
+
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/bsp/src/ipi"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/bsp/src/"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/bsp/src/$(ARCH)/"
+
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_cpu_cortexa9/src"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_scugic/src"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_l2cachec/src"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_uartps/src"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_emacps/src"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_scuc/src"
+
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/cortexa9"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/cortexa9/gcc"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/common"
+
+INC += -I"$(SRC_DIR)/Xilinx/libsrc/ipipsu_v2_3/src/" 
+INC += -I"$(SRC_DIR)/Modules/MMU" 
+

src/APP/Aufgabe2/ps7/core0/build/sources.mk

@@ -0,0 +1,38 @@
+#Startup file
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/bsp/src/$(ARCH)/asm_vectors.S
+-include $(SRC_DIR)/ucos_v1_42/ucos/bsp/src/$(ARCH)/subdir.mk
+-include $(SRC_DIR)/ucos_v1_42/ucos/bsp/src/subdir.mk
+
+-include $(SRC_DIR)/ucos_v1_42/micrium_source/uC-LIB/subdir.mk
+
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/components/ucos_osii/src/bsp/$(ARCH)/ucos_osii_bsp.c
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/components/ucos_common/src/$(ARCH)/cpu_bsp.c
+
+SRC += $(SRC_DIR)/Modules/MMU/mmu.c
+
+SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/main.c
+SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/app_hooks.c
+SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/uartps_cfg.c
+
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Ports/ARM-Cortex-A/Generic/GNU/os_cpu_a_vfp-none.S
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Ports/ARM-Cortex-A/Generic/GNU/os_cpu_c.c
+
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/Cache/ARM/armv7_generic_l1/GNU/cpu_cache_armv7_generic_l1_a.S
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/Cache/ARM/armv7_generic_l1/cpu_cache_armv7_generic_l1.c
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/ARM-Cortex-A/GNU/cpu_a.S
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/cpu_core.c
+
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_uartps/src/ucos_uartps.c
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_scutimer/src/ucos_scutimer.c
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_scugic/src/ucos_scugic.c
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_scuc/src/ucos_scuc.c
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_l2cachec/src/ucos_l2cachec.c
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_emacps/src/ucos_emacps.c
+
+-include $(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/cortexa9/subdir.mk
+
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-Common/KAL/uCOS-II/kal.c
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-Common/Collections/slist.c
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-Common/Auth/auth.c
+
+-include $(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Source/subdir.mk

src/APP/Aufgabe2/ps7/core0/cfg/app_cfg.h

@@ -0,0 +1,82 @@
+/*
+*********************************************************************************************************
+*
+*                                    MICRIUM BOARD SUPPORT PACKAGE
+*
+*                        (c) Copyright 2014-2015; Micrium, Inc.; Weston, FL
+*
+*               All rights reserved.  Protected by international copyright laws.
+*
+*               This BSP is provided in source form to registered licensees ONLY.  It is
+*               illegal to distribute this source code to any third party unless you receive
+*               written permission by an authorized Micrium representative.  Knowledge of
+*               the source code may NOT be used to develop a similar product.
+*
+*               Please help us continue to provide the Embedded community with the finest
+*               software available.  Your honesty is greatly appreciated.
+*
+*               You can contact us at www.micrium.com.
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                    MICRIUM BOARD SUPPORT PACKAGE
+*
+* Filename      : app_cfg.h
+* Version       : V1.42
+* Programmer(s) : JBL
+*********************************************************************************************************
+*/
+
+#ifndef  UCOS_APP_CFG_PRESENT
+#define  UCOS_APP_CFG_PRESENT
+
+#include  <lib_def.h>
+
+#include  <xparameters.h>
+
+#define  APP_CPU_ENABLED DEF_ENABLED
+
+#define  APP_LIB_ENABLED DEF_ENABLED
+
+#define  APP_COMMON_ENABLED DEF_ENABLED
+
+#define  APP_SHELL_ENABLED DEF_DISABLED
+
+#define  APP_CLK_ENABLED DEF_DISABLED
+
+#define  APP_OSIII_ENABLED DEF_DISABLED
+
+#define  APP_OSII_ENABLED  DEF_ENABLED
+
+#define  APP_TCPIP_ENABLED  DEF_DISABLED
+
+#define  APP_TCPIP_EXP_ENABLED  DEF_DISABLED
+
+#define  APP_DHCPC_ENABLED  DEF_DISABLED
+
+#define  APP_DNSC_ENABLED  DEF_DISABLED
+
+#define  APP_HTTPC_ENABLED  DEF_DISABLED
+
+#define  APP_MQTTC_ENABLED  DEF_DISABLED
+
+#define  APP_TELNETS_ENABLED  DEF_DISABLED
+
+#define  APP_IPERF_ENABLED  DEF_DISABLED
+
+#define  APP_FS_ENABLED  DEF_DISABLED
+
+#define  APP_USBD_ENABLED  DEF_DISABLED
+
+#define  APP_USBH_ENABLED  DEF_DISABLED
+
+#define  APP_OPENAMP_ENABLED  DEF_DISABLED
+
+#define OS_TASK_TMR_PRIO 3
+
+
+#endif /* #ifndef  UCOS_APP_CFG_PRESENT */
+

src/APP/Aufgabe2/ps7/core0/cfg/can_cfg.h

@@ -0,0 +1,202 @@
+/*
+*********************************************************************************************************
+*                                               uC/CAN
+*                                       The Embedded CAN suite
+*
+*                          (c) Copyright 2003-2014; Micrium, Inc.; Weston, FL
+*
+*               All rights reserved.  Protected by international copyright laws.
+*
+*               uC/CAN is provided in source form to registered licensees ONLY.  It is
+*               illegal to distribute this source code to any third party unless you receive
+*               written permission by an authorized Micrium representative.  Knowledge of
+*               the source code may NOT be used to develop a similar product.
+*
+*               Please help us continue to provide the Embedded community with the finest
+*               software available.  Your honesty is greatly appreciated.
+*
+*               You can contact us at www.micrium.com.
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                                        uC/CAN CONFIGURATION
+*
+*                                         ZYNQ ZC7000 Series
+*                                             CAN DRIVER
+* Filename      : can_cfg.h
+* Version       : V2.41.00
+* Programmer(s) : E0
+*                 DC
+*********************************************************************************************************
+*/
+
+#ifndef _CAN_CFG_H_
+#define _CAN_CFG_H_
+
+#include  "lib_def.h"
+
+
+/*
+*********************************************************************************************************
+*                                    COMMON DEFINES & ENUMERATIONS
+*********************************************************************************************************
+*/
+
+                                                                /* Definiton for CANSIG_GRANULARITY, Options:           */
+#define  CAN_CFG_BIT                            0u              /*      BIT                                             */
+#define  CAN_CFG_BYTE                           1u              /*      BYTE                                            */
+
+#ifndef  CAN_FALSE
+#define  CAN_FALSE                              0u
+#endif
+
+#ifndef  CAN_TRUE
+#define  CAN_TRUE                               1u
+#endif
+
+#ifndef  NULL_PTR
+#define  NULL_PTR                              (void *)0
+#endif
+      
+                                                                /* ------------ APPLICATION ENUMERATIONS -------------- */
+enum {
+   S_NODESTATUS = 0, 
+   S_CPULOAD, 
+   S_COUNTER, 
+   S_MAX,
+};
+
+enum {
+   M_STATUS = 0, 
+   M_COMMAND, 
+   M_MAX
+};
+
+
+/*
+*********************************************************************************************************
+*                                      MULTIPLE CAN CONTROLLERS
+*********************************************************************************************************
+*/
+
+#define  CAN_MODULE_CHANNEL_0                   DEF_ENABLED
+#define  CAN_MODULE_CHANNEL_1                   DEF_DISABLED
+
+
+/*
+*********************************************************************************************************
+*                                       DRIVER SPECIFIC DEFINES
+*********************************************************************************************************
+*/
+                                                                /* ---------------- BAUDRATE SETTINGS ----------------- */
+#define  CAN_DEFAULT_BAUDRATE             1000000u              /* Default Baudrate                                     */
+#define  CAN_DEFAULT_SP                       750u              /* Default Bit Sample Point in 1/10 %                   */
+#define  CAN_DEFAULT_RJW                      125u              /* Default Re-Synch Jump Width in 1/10 %                */
+
+                                                                /* ---------------- TIMEOUT SETTINGS ------------------ */
+#define  CAN_TIMEOUT_ERR_VAL               100000uL             /* Timeout Value for While Loop Error Checks            */
+
+
+/* ==================================  ADVANCED DRIVER CONFIGURATION: DEFAULT VALUES ================================== */
+/*  By Default, the following Driver specific settings for the ZYNQ ZC7xxx Driver are set to their default values       */
+/*  unless they are modified by customer needs.                                                                         */
+/*                                                                                                                      */
+/*  By Default, the Watermark level is configured to Maximum Watermark Value in the Driver, based on the reset value    */
+/*  presented by the Reference Manual. Redefine the following define to modify the Watermark Level for the following.   */
+/*      Tx FIFO Empty & Rx FIFO Full Watermark Level(s):                                                                */
+/*          NOTE : The VALID range is between 1 & 63.                                                                   */
+/*                                                                                                                      */
+/*          #define  CAN_WATERMARK_Rx_Tx_SIZE              63u                                                          */
+/*                                                                                                                      */
+/*  By Default, the Operating Mode of the CAN controller is configured to "NORMAL" Mode. For diagnostic checking,       */
+/*  additional operating modes have been included in the driver. Redefine the following define to modify the Operating  */
+/*  Mode to either "LOOP BACK" or "SNOOP" Mode(s).                                                                      */
+/*      NOTE that only one operating mode can be selected at once at Initialization. Once CAN has been Initialized it   */
+/*           is possible to change between Operating Modes at run-time using the xxx_CAN_IoCtl() API Function call.     */
+/*                                                                                                                      */
+/*          #define  CAN_DIAGNOSTIC_OFF                     0u                                                          */
+/*          #define  CAN_DIAGNOSTIC_LOOPBACK                1u                                                          */
+/*          #define  CAN_DIAGNOSTIC_SNOOP                   2u                                                          */
+/*                                                                                                                      */
+/*          #define  CAN_DIAGNOSTIC_SELECT                  CAN_DIAGNOSTIC_LOOPBACK                                     */
+/*                                                                                                                      */
+/* ==================================================================================================================== */
+
+
+/*
+*********************************************************************************************************
+*                                               CAN BUS
+*********************************************************************************************************
+*/
+
+#define  CANBUS_EN                              1u              /* Enable CAN Bus Management                            */
+#define  CANBUS_N                               3u              /*   Number of busses                                   */
+#define  CANBUS_ARG_CHK_EN                      1u              /*   Enable runtime argument checking                   */
+#define  CANBUS_TX_HANDLER_EN                   1u              /*   Enable usage of CanBusTxHandler                    */
+#define  CANBUS_RX_HANDLER_EN                   1u              /*   Enable usage of CanBusRxHandler                    */
+#define  CANBUS_NS_HANDLER_EN                   1u              /*   Enable usage of CanBusNsHandler                    */
+												  
+#define  CANBUS_STAT_EN                         1u              /*   Enable Bus Statistics                              */
+#define  CANBUS_TX_QSIZE                 (2u * CANBUS_N)        /*   Transmit Queue Size in CAN Frames for each CAN Bus */
+#define  CANBUS_RX_QSIZE                 (2u * CANBUS_N)        /*   Receive Queue Size in CAN Frames for each CAN Bus  */
+
+#define  CANBUS_HOOK_NS_EN                      1u              /*   Enable Node Status Handler Hook Function           */
+#define  CANBUS_HOOK_RX_EN                      1u              /*   Enable Rx Handler Hook Function                    */
+#define  CANBUS_RX_READ_ALWAYS_EN               1u              /*   If enabled the Rx Handler executes a read even..   */
+                                                                /*   .. when frames can't be allocated                  */
+
+
+/*
+*********************************************************************************************************
+*                                             CAN MESSAGE
+*********************************************************************************************************
+*/
+
+#define  CANMSG_EN                              1u              /* Enable CAN Message Support                           */
+#define  CANMSG_N                               2u              /*   Number of messages                                 */
+#define  CANMSG_ARG_CHK_EN                      1u              /*   Enable runtime argument checking                   */
+
+
+/*
+*********************************************************************************************************
+*                                             CAN SIGNAL
+*********************************************************************************************************
+*/
+
+#define  CANSIG_EN                              1u              /* Enable CAN Signal Database                           */
+#define  CANSIG_N                               3u              /*   Number of signals                                  */
+#define  CANSIG_ARG_CHK_EN                      1u              /*   Enable runtime argument checking                   */
+#define  CANSIG_MAX_WIDTH                       4u              /*   Maximal signal width in byte                       */
+#define  CANSIG_GRANULARITY               CAN_CFG_BYTE          /*   Set signal resolution to byte                      */
+#define  CANSIG_STATIC_CONFIG                   1u              /* To reduce memory usage, declare static signal table  */
+#define  CANSIG_USE_DELETE                      0u              /* To reduce memory usage don't use delete functions    */
+#define  CANSIG_CALLBACK_EN                     0u              /* Enable callback functions                            */
+
+
+/*
+*********************************************************************************************************
+*                                              CAN FRAME
+*********************************************************************************************************
+*/
+
+#define  CANFRM_ARG_CHK_EN                      1u              /* Enable runtime argument checking                     */
+
+
+/*
+*********************************************************************************************************
+*                                               CAN OS
+*********************************************************************************************************
+*/
+
+#define  CANOS_ARG_CHK_EN                       1u              /* Enable runtime argument checking                     */
+
+
+/*
+*********************************************************************************************************
+*                                          CONFIGURATION END
+*********************************************************************************************************
+*/
+
+#endif  /* #ifndef _CAN_CFG_H_ */

src/APP/Aufgabe2/ps7/core0/cfg/cpu_cfg.h

@@ -0,0 +1,216 @@
+/*
+*********************************************************************************************************
+*                                                uC/CPU
+*                                    CPU CONFIGURATION & PORT LAYER
+*
+*                          (c) Copyright 2004-2015; Micrium, Inc.; Weston, FL
+*
+*               All rights reserved.  Protected by international copyright laws.
+*
+*               uC/CPU is provided in source form to registered licensees ONLY.  It is 
+*               illegal to distribute this source code to any third party unless you receive 
+*               written permission by an authorized Micrium representative.  Knowledge of 
+*               the source code may NOT be used to develop a similar product.
+*
+*               Please help us continue to provide the Embedded community with the finest 
+*               software available.  Your honesty is greatly appreciated.
+*
+*               You can find our product's user manual, API reference, release notes and
+*               more information at https://doc.micrium.com.
+*               You can contact us at www.micrium.com.
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                       CPU CONFIGURATION FILE
+*
+*                                              TEMPLATE
+*
+* Filename      : cpu_cfg.h
+* Version       : V1.30.02
+* Programmer(s) : SR
+*                 ITJ
+*                 JBL
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                               MODULE
+*********************************************************************************************************
+*/
+
+#ifndef  CPU_CFG_MODULE_PRESENT
+#define  CPU_CFG_MODULE_PRESENT
+
+
+/*
+*********************************************************************************************************
+*                                       CPU NAME CONFIGURATION
+*
+* Note(s) : (1) Configure CPU_CFG_NAME_EN to enable/disable CPU host name feature :
+*
+*               (a) CPU host name storage
+*               (b) CPU host name API functions
+*
+*           (2) Configure CPU_CFG_NAME_SIZE with the desired ASCII string size of the CPU host name, 
+*               including the terminating NULL character.
+*
+*               See also 'cpu_core.h  GLOBAL VARIABLES  Note #1'.
+*********************************************************************************************************
+*/
+
+                                                                /* Configure CPU host name feature (see Note #1) :      */
+#define  CPU_CFG_NAME_EN                        DEF_DISABLED
+                                                                /*   DEF_DISABLED  CPU host name DISABLED               */
+                                                                /*   DEF_ENABLED   CPU host name ENABLED                */
+
+                                                                /* Configure CPU host name ASCII string size ...        */
+#define  CPU_CFG_NAME_SIZE                                16
+
+
+/*
+*********************************************************************************************************
+*                                     CPU TIMESTAMP CONFIGURATION
+*
+* Note(s) : (1) Configure CPU_CFG_TS_xx_EN to enable/disable CPU timestamp features :
+*
+*               (a) CPU_CFG_TS_32_EN   enable/disable 32-bit CPU timestamp feature
+*               (b) CPU_CFG_TS_64_EN   enable/disable 64-bit CPU timestamp feature
+*
+*           (2) (a) Configure CPU_CFG_TS_TMR_SIZE with the CPU timestamp timer's word size :
+*
+*                       CPU_WORD_SIZE_08         8-bit word size
+*                       CPU_WORD_SIZE_16        16-bit word size
+*                       CPU_WORD_SIZE_32        32-bit word size
+*                       CPU_WORD_SIZE_64        64-bit word size
+*
+*               (b) If the size of the CPU timestamp timer is not a binary multiple of 8-bit octets 
+*                   (e.g. 20-bits or even 24-bits), then the next lower, binary-multiple octet word 
+*                   size SHOULD be configured (e.g. to 16-bits).  However, the minimum supported word 
+*                   size for CPU timestamp timers is 8-bits.
+*
+*                   See also 'cpu_core.h  FUNCTION PROTOTYPES  CPU_TS_TmrRd()  Note #2a'.
+*********************************************************************************************************
+*/
+
+                                                                /* Configure CPU timestamp features (see Note #1) :     */
+#define  CPU_CFG_TS_32_EN                       DEF_ENABLED
+#define  CPU_CFG_TS_64_EN                       DEF_ENABLED
+                                                                /*   DEF_DISABLED  CPU timestamps DISABLED              */
+                                                                /*   DEF_ENABLED   CPU timestamps ENABLED               */
+
+                                                                /* Configure CPU timestamp timer word size ...          */
+                                                                /* ... (see Note #2) :                                  */
+#define  CPU_CFG_TS_TMR_SIZE                    CPU_WORD_SIZE_64
+
+
+/*
+*********************************************************************************************************
+*                        CPU INTERRUPTS DISABLED TIME MEASUREMENT CONFIGURATION
+*
+* Note(s) : (1) (a) Configure CPU_CFG_INT_DIS_MEAS_EN to enable/disable measuring CPU's interrupts 
+*                   disabled time :
+*
+*                   (a)  Enabled,       if CPU_CFG_INT_DIS_MEAS_EN      #define'd in 'cpu_cfg.h'
+*
+*                   (b) Disabled,       if CPU_CFG_INT_DIS_MEAS_EN  NOT #define'd in 'cpu_cfg.h'
+*
+*                   See also 'cpu_core.h  FUNCTION PROTOTYPES  Note #1'.
+*
+*               (b) Configure CPU_CFG_INT_DIS_MEAS_OVRHD_NBR with the number of times to measure & 
+*                   average the interrupts disabled time measurements overhead.
+*
+*                   See also 'cpu_core.c  CPU_IntDisMeasInit()  Note #3a'.
+*********************************************************************************************************
+*/
+
+#if 0                                                           /* Configure CPU interrupts disabled time ...           */
+#define  CPU_CFG_INT_DIS_MEAS_EN                                /* ... measurements feature (see Note #1a).             */
+#endif
+
+                                                                /* Configure number of interrupts disabled overhead ... */
+#define  CPU_CFG_INT_DIS_MEAS_OVRHD_NBR                    1u   /* ... time measurements (see Note #1b).                */
+
+
+/*
+*********************************************************************************************************
+*                                    CPU COUNT ZEROS CONFIGURATION
+*
+* Note(s) : (1) (a) Configure CPU_CFG_LEAD_ZEROS_ASM_PRESENT  to define count leading  zeros bits 
+*                   function(s) in :
+*
+*                   (1) 'cpu_a.asm',  if CPU_CFG_LEAD_ZEROS_ASM_PRESENT       #define'd in 'cpu.h'/
+*                                         'cpu_cfg.h' to enable assembly-optimized function(s)
+*
+*                   (2) 'cpu_core.c', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT   NOT #define'd in 'cpu.h'/
+*                                         'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
+*
+*               (b) Configure CPU_CFG_TRAIL_ZEROS_ASM_PRESENT to define count trailing zeros bits 
+*                   function(s) in :
+*
+*                   (1) 'cpu_a.asm',  if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT      #define'd in 'cpu.h'/
+*                                         'cpu_cfg.h' to enable assembly-optimized function(s)
+*
+*                   (2) 'cpu_core.c', if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT  NOT #define'd in 'cpu.h'/
+*                                         'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
+*********************************************************************************************************
+*/
+
+#if 0                                                           /* Configure CPU count leading  zeros bits ...          */
+#define  CPU_CFG_LEAD_ZEROS_ASM_PRESENT                         /* ... assembly-version (see Note #1a).                 */
+#endif
+
+#if 0                                                           /* Configure CPU count trailing zeros bits ...          */
+#define  CPU_CFG_TRAIL_ZEROS_ASM_PRESENT                        /* ... assembly-version (see Note #1b).                 */
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                      CPU ENDIAN TYPE OVERRIDE
+*
+* Note(s) : (1) Configure CPU_CFG_ENDIAN_TYPE to override the default CPU endian type defined in cpu.h.
+*
+*               (a) CPU_ENDIAN_TYPE_BIG         Big-   endian word order (CPU words' most  significant
+*                                                                         octet @ lowest memory address)
+*               (b) CPU_ENDIAN_TYPE_LITTLE      Little-endian word order (CPU words' least significant
+*                                                                         octet @ lowest memory address)
+*
+*           (2) Defining CPU_CFG_ENDIAN_TYPE here is only valid for supported bi-endian architectures.
+*               See  'cpu.h  CPU WORD CONFIGURATION  Note #3' for details
+*********************************************************************************************************
+*/
+
+#if 0
+#define  CPU_CFG_ENDIAN_TYPE            CPU_ENDIAN_TYPE_BIG     /* Defines CPU data    word-memory order (see Note #2). */
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                          CACHE MANAGEMENT
+*
+* Note(s) : (1) Configure CPU_CFG_CACHE_MGMT_EN to enable the cache managment API.
+
+*
+*           (2) Defining CPU_CFG_CACHE_MGMT_EN to DEF_ENABLED only enable the cache management function.
+*               Cache are assumed to be configured and enabled by the time CPU_init() is called.
+*********************************************************************************************************
+*/
+
+#define  CPU_CFG_CACHE_MGMT_EN            DEF_DISABLED
+
+
+/*
+*********************************************************************************************************
+*                                             MODULE END
+*********************************************************************************************************
+*/
+
+#endif                                                          /* End of CPU cfg module include.                       */
+
+#define  CPU_CACHE_CFG_L2C310_BASE_ADDR  0xF8F02000

src/APP/Aufgabe2/ps7/core0/cfg/dhcp-c_cfg.h

@@ -0,0 +1,146 @@
+/*
+*********************************************************************************************************
+*                                               uC/DHCPc
+*                              Dynamic Host Configuration Protocol Client
+*
+*                         (c) Copyright 2004-2014; Micrium, Inc.; Weston, FL
+*
+*                  All rights reserved.  Protected by international copyright laws.
+*
+*                  uC/DHCP is provided in source form to registered licensees ONLY.  It is
+*                  illegal to distribute this source code to any third party unless you receive
+*                  written permission by an authorized Micrium representative.  Knowledge of
+*                  the source code may NOT be used to develop a similar product.
+*
+*                  Please help us continue to provide the Embedded community with the finest
+*                  software available.  Your honesty is greatly appreciated.
+*
+*                  You can find our product's user manual, API reference, release notes and
+*                  more information at: https://doc.micrium.com
+*
+*                  You can contact us at: http://www.micrium.com
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                   DHCP CLIENT CONFIGURATION FILE
+*
+*                                              TEMPLATE
+*
+* Filename      : dhcp-c_cfg.h
+* Version       : V2.10.00
+* Programmer(s) : SR
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                           TASKS PRIORITIES
+* Notes: (1) Task priorities configuration values should be used by the DHCPc OS port. The following task priorities
+*            should be defined:
+*
+*                   DHCPc_OS_CFG_TASK_PRIO
+*                   DHCPc_OS_CFG_TMR_TASK_PRIO
+*
+*            Task priorities can be defined either in this configuration file 'dhcp-c_cfg.h' or in a global
+*            OS tasks priorities configuration header file which must be included in 'dhcp-c_cfg.h'.
+*********************************************************************************************************
+*/
+
+                                                                /* See Note #1.                                         */
+#define  DHCPc_OS_CFG_TASK_PRIO                           13
+#define  DHCPc_OS_CFG_TMR_TASK_PRIO                       14
+
+
+/*
+*********************************************************************************************************
+*                                              STACK SIZES
+*            Size (depth) of the task stacks (See the definition of CPU_STK for stack width)
+*********************************************************************************************************
+*/
+
+#define  DHCPc_OS_CFG_TASK_STK_SIZE                      512
+#define  DHCPc_OS_CFG_TMR_TASK_STK_SIZE 256
+
+
+/*
+*********************************************************************************************************
+*                                                 DHCPc
+*
+* Note(s) : (1) Default port for DHCP server is 67, and default port for DHCP client is 68.
+*
+*           (3) Configure DHCPc_CFG_MAX_NBR_IF to the maximum number of interface this DHCP client will
+*               be able to manage at a given time.
+*
+*           (4) Once the DHCP server has assigned the client an address, the later may perform a final
+*               check prior to use this address in order to make sure it is not being used by another
+*               host on the network.
+*********************************************************************************************************
+*/
+
+#define  DHCPc_CFG_IP_PORT_SERVER                         67
+#define  DHCPc_CFG_IP_PORT_CLIENT                         68
+
+#define  DHCPc_CFG_MAX_RX_TIMEOUT_MS                    1000
+
+#define  DHCPc_CFG_PARAM_REQ_TBL_SIZE                      5
+
+#define  DHCPc_CFG_MAX_NBR_IF                              1
+
+#define  DHCPc_CFG_ADDR_VALIDATE_EN              DEF_ENABLED
+                                                                /* ... (see Note #4) :                                  */
+                                                                /*   DEF_DISABLED  Validation NOT performed             */
+                                                                /*   DEF_ENABLED   Validation     performed             */
+
+#define  DHCPc_CFG_DYN_LOCAL_LINK_ADDR_EN        DEF_ENABLED
+                                                                /*   DEF_DISABLED  local-link configuration DISABLED    */
+                                                                /*   DEF_ENABLED   local-link configuration ENABLED     */
+
+#define  DHCPc_CFG_LOCAL_LINK_MAX_RETRY                    3
+                                                                /* link-local address.                                  */
+
+
+/*
+*********************************************************************************************************
+*                                 DHCPc ARGUMENT CHECK CONFIGURATION
+*
+* Note(s) : (1) Configure DHCPc_CFG_ARG_CHK_EXT_EN to enable/disable the DHCP client external argument
+*               check feature :
+*
+*               (a) When ENABLED,  ALL arguments received from any port interface provided by the developer
+*                   or application are checked/validated.
+*
+*               (b) When DISABLED, NO  arguments received from any port interface provided by the developer
+*                   or application are checked/validated.
+*
+*           (2) Configure DHCPc_CFG_ARG_CHK_DBG_EN to enable/disable the DHCP client internal debug
+*               argument check feature :
+*
+*               (a) When ENABLED,     internal arguments are checked/validated to debug the DHCP client.
+*
+*               (b) When DISABLED, NO internal arguments are checked/validated to debug the DHCP client.
+*
+*           (3) Configure DHCPc_DBG_CFG_MEM_CLR_EN to enable/disable the DHCP client from clearing
+*               internal data structure memory buffers; a convenient feature while debugging.
+*********************************************************************************************************
+*/
+                                                                /* Configure external argument check feature ...        */
+                                                                /* ... (see Note #1) :                                  */
+#define  DHCPc_CFG_ARG_CHK_EXT_EN                DEF_ENABLED
+                                                                /*   DEF_DISABLED     Argument check DISABLED           */
+                                                                /*   DEF_ENABLED      Argument check ENABLED            */
+
+                                                                /* Configure internal argument check feature ...        */
+                                                                /* ... (see Note #2) :                                  */
+#define  DHCPc_CFG_ARG_CHK_DBG_EN                DEF_DISABLED
+                                                                /*   DEF_DISABLED     Argument check DISABLED           */
+                                                                /*   DEF_ENABLED      Argument check ENABLED            */
+
+                                                                /* Configure memory clear feature  (see Note #3) :      */
+#define  DHCPc_DBG_CFG_MEM_CLR_EN                DEF_DISABLED
+                                                                /*   DEF_DISABLED     Data structure clears DISABLED    */
+                                                                /*   DEF_ENABLED      Data structure clears ENABLED     */
+

src/APP/Aufgabe2/ps7/core0/cfg/dns-c_cfg.h

@@ -0,0 +1,111 @@
+/*
+*********************************************************************************************************
+*                                               uC/DNSc
+*                                     Domain Name Server (client)
+*
+*                         (c) Copyright 2004-2014; Micrium, Inc.; Weston, FL
+*
+*                  All rights reserved.  Protected by international copyright laws.
+*
+*                  uC/DNSc is provided in source form to registered licensees ONLY.  It is
+*                  illegal to distribute this source code to any third party unless you receive
+*                  written permission by an authorized Micrium representative.  Knowledge of
+*                  the source code may NOT be used to develop a similar product.
+*
+*                  Please help us continue to provide the Embedded community with the finest
+*                  software available.  Your honesty is greatly appreciated.
+*
+*                  You can find our product's user manual, API reference, release notes and
+*                  more information at: https://doc.micrium.com
+*
+*                  You can contact us at: http://www.micrium.com
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                    DNS CLIENT CONFIGURATION FILE
+*
+*                                              TEMPLATE
+*
+* Filename      : dns-c_cfg.h
+* Version       : V2.00.01
+* Programmer(s) : AA
+*********************************************************************************************************
+*/
+
+#ifndef DNSc_CFG_MODULE_PRESENT
+#define DNSc_CFG_MODULE_PRESENT
+
+#include  <Source/dns-c_type.h>
+
+
+/*
+*********************************************************************************************************
+*                                  DNSc ARGUMENT CHECK CONFIGURATION
+*
+* Note(s) : (1) Configure DNSc_CFG_ARG_CHK_EXT_EN to enable/disable the DNS client external argument
+*               check feature :
+*
+*               (a) When ENABLED,  ALL arguments received from any port interface provided by the developer
+*                   are checked/validated.
+*
+*               (b) When DISABLED, NO  arguments received from any port interface provided by the developer
+*                   are checked/validated.
+*********************************************************************************************************
+*/
+                                                                /* Configure external argument check feature ...        */
+                                                                /* See Note 1.                                          */
+#define  DNSc_CFG_ARG_CHK_EXT_EN                    DEF_DISABLED
+                                                                /* DEF_DISABLED     External argument check DISABLED    */
+                                                                /* DEF_ENABLED      External argument check ENABLED     */
+
+/*
+*********************************************************************************************************
+*                                     DNSc FEATURES CONFIGURATION
+*
+* Note(s) : (1) Configure DNSc_CFG_MODE_ASYNC_EN to enable/disable the DNS client asynchronous communication mode:
+*
+*               (a) When ENABLED,  A dedicated task will handle all host resolution request. It will be possible to
+*                   call DNS API to get remote host address without blocking.
+*
+*               (b) When DISABLED, The API to get remote host will always block until the resolution is completed.
+*
+*           (2) Configure DNSc_CFG_MODE_BLOCK_EN to enable/disable the blocking option when the asynchronous
+*               communication is enabled.
+*
+*               (a) When ENABLED,  It will be possible to block when calling the DNS API to get remote host until the
+*                   resolution is completed (via a flag option).
+*
+*               (b) When DISABLED, The API to get remote host will always be non-blocking, must poll DNS client to
+*                   know when the resolution is completed.
+*********************************************************************************************************
+*/
+
+                                                                /* Configure asynchronous mode feature, See Note #1 ... */
+#define  DNSc_CFG_MODE_ASYNC_EN                     DEF_DISABLED
+                                                                /* DEF_DISABLED     Asynchronous mode DISABLED          */
+                                                                /* DEF_ENABLED      Asynchronous mode ENABLED           */
+
+
+                                                                /* Configure blocking option feature, See Note #2 ... */
+#define  DNSc_CFG_MODE_BLOCK_EN                     DEF_DISABLED
+                                                                /* DEF_DISABLED     Blocking option DISABLED            */
+                                                                /* DEF_ENABLED      Blocking option ENABLED             */
+
+/*
+*********************************************************************************************************
+*                                DNSc RUN-TIME STRUCTURE CONFIGURATION
+*
+* Note(s) : (1) These structures should be defined into a 'C' file.
+*********************************************************************************************************
+*/
+
+extern  const  DNSc_CFG       DNSc_Cfg;                         /* Must always be defined.                              */
+
+#if (DNSc_CFG_MODE_ASYNC_EN == DEF_ENABLED)
+extern  const  DNSc_CFG_TASK  DNSc_CfgTask;                     /* Not required when Asynchronous mode is disabled.     */
+#endif
+
+#endif

src/APP/Aufgabe2/ps7/core0/cfg/http-c_cfg.h

@@ -0,0 +1,224 @@
+/*
+*********************************************************************************************************
+*                                               uC/HTTP
+*                                      Hypertext Transfer Protocol
+*
+*                         (c) Copyright 2004-2015; Micrium, Inc.; Weston, FL
+*
+*                  All rights reserved.  Protected by international copyright laws.
+*
+*                  uC/HTTP is provided in source form to registered licensees ONLY.  It is
+*                  illegal to distribute this source code to any third party unless you receive
+*                  written permission by an authorized Micrium representative.  Knowledge of
+*                  the source code may NOT be used to develop a similar product.
+*
+*                  Please help us continue to provide the Embedded community with the finest
+*                  software available.  Your honesty is greatly appreciated.
+*
+*                  You can find our product's user manual, API reference, release notes and
+*                  more information at: https://doc.micrium.com
+*
+*                  You can contact us at: http://www.micrium.com
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                   HTTP CLIENT CONFIGURATION FILE
+*
+*                                              TEMPLATE
+*
+* Filename      : http-c_cfg.h
+* Version       : V3.00.01
+* Programmer(s) : MM
+*                 AL
+*********************************************************************************************************
+* Note(s)       : (1) Assumes the following versions (or more recent) of software modules are included in
+*                     the project build :
+*
+*                       (a) uC/CPU    V1.29.02
+*                       (b) uC/LIB    V1.38.00
+*                       (c) uC/Common V1.00.00
+*                       (d) uC/TCP-IP V3.03.00
+*
+*
+*                 (2) For additional details on the features available with uC/HTTPc, the API, the
+*                     installation, etc. Please refer to the uC/HTTPc documentation available at
+*                     https://doc.micrium.com/HTTPc.
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                           INCLUDE FILES
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#include  <Common/http.h>
+#include  <Client/Source/http-c_type.h>
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                               MODULE
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#ifndef  HTTPc_CFG_MODULE_PRESENT
+#define  HTTPc_CFG_MODULE_PRESENT
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                      COMPILE-TIME CONFIGURATION
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                                   HTTP ARGUMENT CHECK CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_ARG_CHK_EXT_EN to enable/disable the HTTP client external argument
+*               check feature :
+*
+*               (a) When ENABLED,  ALL arguments received from any port interface provided by the developer
+*                   are checked/validated.
+*
+*               (b) When DISABLED, NO  arguments received from any port interface provided by the developer
+*                   are checked/validated.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_ARG_CHK_EXT_EN                 DEF_ENABLED
+
+
+/*
+*********************************************************************************************************
+*                                    HTTP CLIENT TASK CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_MODE_ASYNC_TASK_EN to enable/disable HTTP client task.
+*               (a) DEF_DISABLED : No HTTP client task will be created to process the HTTP requests.
+*                                  The Blocking HTTPc API will be enabled.
+*
+*               (b) DEF_ENABLED  : An HTTP client task will be created to process all the HTTP requests.
+*                                  The Non-Blocking HTTPc API will be enabled. Therefore, multiple
+*                                  connections can be handle by the task simultaneously.
+*
+*           (2) Configure HTTPc_CFG_MODE_BLOCK_EN to enable/disable the blocking option when the
+*               asynchronous HTTPc Task is enabled.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_MODE_ASYNC_TASK_EN           DEF_DISABLED
+
+#define  HTTPc_CFG_MODE_BLOCK_EN                DEF_ENABLED
+
+
+/*
+*********************************************************************************************************
+*                              HTTP CLIENT PERSISTENT CONNECTION CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_PERSISTENT_EN to enable/disable Persistent Connection support.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_PERSISTENT_EN                DEF_ENABLED
+
+
+/*
+*********************************************************************************************************
+*                                HTTP CLIENT CHUNKED TRANSFER CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_CHUNK_TX_EN to enable/disable Chunked Transfer support in Transmission.
+*
+*           (2) Chunked Transfer in Reception is always enabled.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_CHUNK_TX_EN                  DEF_ENABLED
+
+
+/*
+*********************************************************************************************************
+*                                 HTTP CLIENT QUERY STRING CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_QUERY_STR_EN to enable/disable Query String support in URL.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_QUERY_STR_EN                 DEF_ENABLED
+
+
+/*
+*********************************************************************************************************
+*                                HTTP CLIENT HEADER FIELD CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_HDR_RX_EN to enable/disable header field processing in reception
+*               (i.e for headers received in the HTTP response.
+*
+*           (2) Configure HTTPc_CFG_HDR_TX_EN to enable/disable header field processing in transmission
+*               (i.e for headers to include in the HTTP request.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_HDR_RX_EN                    DEF_ENABLED
+
+
+#define  HTTPc_CFG_HDR_TX_EN                    DEF_ENABLED
+
+
+/*
+*********************************************************************************************************
+*                                     HTTP CLIENT FORM CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_FORM_EN to enable/disable HTTP form creation source code.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_FORM_EN                      DEF_ENABLED
+
+
+/*
+*********************************************************************************************************
+*                                   HTTP CLIENT USER DATA CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_USER_DATA_EN         to enable/disable user data pointer in HTTPc_CONN
+*                                                        and HTTPc_REQ structure.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_USER_DATA_EN                 DEF_ENABLED
+
+
+/*
+*********************************************************************************************************
+*                                   HTTP CLIENT WEBSOCKET CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_WEBSOCKET_EN        to enable/disable the Websocket feature.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_WEBSOCKET_EN                 DEF_DISABLED
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                      RUN-TIME CONFIGURATION
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+extern  const  HTTP_TASK_CFG   HTTPc_TaskCfg;
+extern  const  HTTPc_CFG       HTTPc_Cfg;
+
+
+/* =============================================== END =============================================== */
+#endif  /* HTTPc_CFG_MODULE_PRESENT */

src/APP/Aufgabe2/ps7/core0/cfg/lib_cfg.h

@@ -0,0 +1,171 @@
+/*
+*********************************************************************************************************
+*                                            EXAMPLE CODE
+*
+*               This file is provided as an example on how to use Micrium products.
+*
+*               Please feel free to use any application code labeled as 'EXAMPLE CODE' in
+*               your application products.  Example code may be used as is, in whole or in
+*               part, or may be used as a reference only. This file can be modified as
+*               required to meet the end-product requirements.
+*
+*               Please help us continue to provide the Embedded community with the finest
+*               software available.  Your honesty is greatly appreciated.
+*
+*               You can find information about uC/LIB by visiting doc.micrium.com.
+*               You can contact us at: http://www.micrium.com
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                  CUSTOM LIBRARY CONFIGURATION FILE
+*
+*                                              TEMPLATE
+*
+* Filename      : lib_cfg.h
+* Version       : V1.38.01.00
+* Programmer(s) : FBJ
+*                 JFD
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                               MODULE
+*********************************************************************************************************
+*/
+
+#ifndef  LIB_CFG_MODULE_PRESENT
+#define  LIB_CFG_MODULE_PRESENT
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                    MEMORY LIBRARY CONFIGURATION
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                             MEMORY LIBRARY ARGUMENT CHECK CONFIGURATION
+*
+* Note(s) : (1) Configure LIB_MEM_CFG_ARG_CHK_EXT_EN to enable/disable the memory library suite external
+*               argument check feature :
+*
+*               (a) When ENABLED,     arguments received from any port interface provided by the developer
+*                   or application are checked/validated.
+*
+*               (b) When DISABLED, NO arguments received from any port interface provided by the developer
+*                   or application are checked/validated.
+*********************************************************************************************************
+*/
+
+                                                                /* External argument check.                             */
+                                                                /* Indicates if arguments received from any port ...    */
+                                                                /* ... interface provided by the developer or ...       */
+                                                                /* ... application are checked/validated.               */
+#define  LIB_MEM_CFG_ARG_CHK_EXT_EN     DEF_DISABLED
+
+
+/*
+*********************************************************************************************************
+*                         MEMORY LIBRARY ASSEMBLY OPTIMIZATION CONFIGURATION
+*
+* Note(s) : (1) Configure LIB_MEM_CFG_OPTIMIZE_ASM_EN to enable/disable assembly-optimized memory function(s).
+*********************************************************************************************************
+*/
+
+                                                                /* Assembly-optimized function(s).                      */
+                                                                /* Enable/disable assembly-optimized memory ...         */
+                                                                /* ... function(s). [see Note #1]                       */
+#define  LIB_MEM_CFG_OPTIMIZE_ASM_EN    DEF_DISABLED
+
+
+/*
+*********************************************************************************************************
+*                                   MEMORY ALLOCATION CONFIGURATION
+*
+* Note(s) : (1) Configure LIB_MEM_CFG_DBG_INFO_EN to enable/disable memory allocation usage tracking
+*               that associates a name with each segment or dynamic pool allocated.
+*
+*           (2) (a) Configure LIB_MEM_CFG_HEAP_SIZE with the desired size of heap memory (in octets).
+*
+*               (b) Configure LIB_MEM_CFG_HEAP_BASE_ADDR to specify a base address for heap memory :
+*
+*                   (1) Heap initialized to specified application memory, if LIB_MEM_CFG_HEAP_BASE_ADDR
+*                                                                                #define'd in 'lib_cfg.h';
+*                                                                         CANNOT #define to address 0x0
+*
+*                   (2) Heap declared to Mem_Heap[] in 'lib_mem.c',       if LIB_MEM_CFG_HEAP_BASE_ADDR
+*                                                                            NOT #define'd in 'lib_cfg.h'
+*********************************************************************************************************
+*/
+
+                                                                /* Allocation debugging information.                    */
+                                                                /* Enable/disable allocation of debug information ...   */
+                                                                /* ... associated to each memory allocation.            */
+#define  LIB_MEM_CFG_DBG_INFO_EN        DEF_DISABLED
+
+
+                                                                /* Heap memory size (in bytes).                         */
+                                                                /* Configure the desired size of the heap memory. ...   */
+                                                                /* ... Set to 0 to disable heap allocation features.    */
+#define  LIB_MEM_CFG_HEAP_SIZE                  64*1024
+
+
+                                                                /* Heap memory padding alignment (in bytes).            */
+                                                                /* Configure the desired size of padding alignment ...  */
+                                                                /* ... of each buffer allocated from the heap.          */
+#define  LIB_MEM_CFG_HEAP_PADDING_ALIGN    LIB_MEM_PADDING_ALIGN_NONE
+
+#if 0                                                           /* Remove this to have heap alloc at specified addr.    */
+#define  LIB_MEM_CFG_HEAP_BASE_ADDR       0
+#endif
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                    STRING LIBRARY CONFIGURATION
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                                 STRING FLOATING POINT CONFIGURATION
+*
+* Note(s) : (1) Configure LIB_STR_CFG_FP_EN to enable/disable floating point string function(s).
+*
+*           (2) Configure LIB_STR_CFG_FP_MAX_NBR_DIG_SIG to configure the maximum number of significant
+*               digits to calculate &/or display for floating point string function(s).
+*
+*               See also 'lib_str.h  STRING FLOATING POINT DEFINES  Note #1'.
+*********************************************************************************************************
+*/
+
+                                                                /* Floating point feature(s).                           */
+                                                                /* Enable/disable floating point to string functions.   */
+#define  LIB_STR_CFG_FP_EN                      DEF_DISABLED
+
+
+                                                                /* Floating point number of significant digits.         */
+                                                                /* Configure the maximum number of significant ...      */
+                                                                /* ... digits to calculate &/or display for ...         */
+                                                                /* ... floating point string function(s).               */
+#define  LIB_STR_CFG_FP_MAX_NBR_DIG_SIG         LIB_STR_FP_MAX_NBR_DIG_SIG_DFLT
+
+
+/*
+*********************************************************************************************************
+*                                             MODULE END
+*********************************************************************************************************
+*/
+
+#endif                                                          /* End of lib cfg module include.                       */
+

src/APP/Aufgabe2/ps7/core0/cfg/mmu_cfg.h

@@ -0,0 +1,42 @@
+/*
+ * mmu_cfg.h
+ *
+ *  Created on: 25.04.2018
+ *      Author: kaige
+ */
+
+#ifndef SRC_APP_LWIPREWORK_PS7_CORE0_CFG_MMU_CFG_H_
+#define SRC_APP_LWIPREWORK_PS7_CORE0_CFG_MMU_CFG_H_
+
+#include "mmu.h"
+
+/*------------------------------------------------------------------------------------------------*/
+/*!
+* \brief    FIRST LEVEL TRANSLATION TABLE (FTT)
+*
+* \ingroup  PAR_CPU_MMU
+*
+*           This variable represents the first level translation table. Each entry within
+*           the table represents the configuration of a 1MB memory segment. If a memory
+*           portion below 1MB must be accessed, the entry represents a pointer to the
+*           linked coarse page table, which contains the information of that 1MB in detail.
+*
+* \note     This table MUST be aligned at 16kB boundary.
+*/
+/*------------------------------------------------------------------------------------------------*/
+
+const PAR_MEM_REGION_T PARMemTbl_Core[]  = {
+/*   +-------------------------------------------------------------------------------------------+
+*    | virtual   | physical  |     size      |   owner          |  permissions    |    HID Field |
+*    +-----------+-----------+---------------+------------------+-----------------+--------------+*/
+	// First 1MB is marked as non-cacheable/non-bufferable (contains 3x 64KB SRAM @ address 0x00000000
+	{ 0x00000000, 0x00000000, MMU_SIZE_1MB,   PAR_AP_PRW__URW_, PAR_HID_TEX_CB_CACHED_MEMORY | PAR_HID_CACHE_INNER_CB | PAR_HID_CACHE_OUTER_CB },
+    // DDR Memory is marked as normal (only 512MB for now)
+	{ 0x00100000, 0x00100000, MMU_SIZE_16MB, PAR_AP_PRW__URW_, PAR_HID_TEX_CB_CACHED_MEMORY | PAR_HID_CACHE_INNER___ | PAR_HID_CACHE_OUTER___ },
+    // Device section
+	{ 0xE0000000, 0xE0000000, MMU_SIZE_512MB-MMU_SIZE_1MB, PAR_AP_PRW__URW_, PAR_HID_EXCLUSIVE_SYS_DEVICE },
+	// Upper 1MB section contains 1x 64KB SRAM @ address 0xFFFF0000
+	{ 0xFFF00000, 0xFFF00000, MMU_SIZE_1MB,   PAR_AP_PRW__URW_, PAR_HID_TEX_CB_OUT_IN_NON_CACHABLE }
+};
+
+#endif /* SRC_APP_LWIPREWORK_PS7_CORE0_CFG_MMU_CFG_H_ */

src/APP/Aufgabe2/ps7/core0/cfg/net_cfg.h

@@ -0,0 +1,676 @@
+/*
+*********************************************************************************************************
+*                                             uC/TCP-IP
+*                                      The Embedded TCP/IP Suite
+*
+*                         (c) Copyright 2004-2015; Micrium, Inc.; Weston, FL
+*
+*                  All rights reserved.  Protected by international copyright laws.
+*
+*                  uC/TCP-IP is provided in source form to registered licensees ONLY.  It is
+*                  illegal to distribute this source code to any third party unless you receive
+*                  written permission by an authorized Micrium representative.  Knowledge of
+*                  the source code may NOT be used to develop a similar product.
+*
+*                  Please help us continue to provide the Embedded community with the finest
+*                  software available.  Your honesty is greatly appreciated.
+*
+*                  You can find our product's user manual, API reference, release notes and
+*                  more information at: https://doc.micrium.com
+*
+*                  You can contact us at: http://www.micrium.com
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                     NETWORK CONFIGURATION FILE
+*
+*                                              TEMPLATE
+*
+* Filename : net_cfg.h
+* Version  : V3.03.01
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                            INCLUDE FILES
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#include  <net_def.h>
+#include  <net_type.h>
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                               MODULE
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#ifndef  NET_CFG_MODULE_PRESENT
+#define  NET_CFG_MODULE_PRESENT
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                             NETWORK EXTERNAL APPLICATION CONFIGURATION
+*
+* Note(s) : (1) When uC/DNS-Client is present in the project some high level functions can resolve hostname.
+*               So uC/TCPIP should know that uC/DNS-Client is present to call the proper API.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+                                                                /* Configure DNS Client feature  (see Note #1) :        */
+#define  NET_EXT_MODULE_CFG_DNS_EN                                 DEF_ENABLED
+                                                                /*   DEF_DISABLED       DNS Client is DISABLED          */
+                                                                /*   DEF_ENABLED        DNS Client is  ENABLED          */
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                        TASKS CONFIGURATION
+*
+* Note(s) : (1) (a) Each network task maps to a unique, developer-configured task configuration that
+*                   MUST be defined in application files, typically 'net_cfg.c', & SHOULD be forward-
+*                   declared with the exact same name & type in order to be used by the application during
+*                   calls to Net_Init().
+*
+*               (b) Since these task configuration structures are referenced ONLY by application files,
+*                   there is NO required naming convention for these configuration structures.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+extern  const  NET_TASK_CFG  NetRxTaskCfg;
+extern  const  NET_TASK_CFG  NetTxDeallocTaskCfg;
+extern  const  NET_TASK_CFG  NetTmrTaskCfg;
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                        TASKS Q CONFIGURATION
+*
+* Note(s) : (1) Rx queue size should be configured such that it reflects the total number of DMA receive descriptors on all
+*               devices. If DMA is not available, or a combination of DMA and I/O based interfaces are configured then this
+*               number reflects the maximum number of packets that can be acknowledged and signalled during a single receive
+*               interrupt event for all interfaces.
+*
+*           (2) Tx queue size should be defined to be the total number of small and large transmit buffers declared for
+*               all interfaces.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#define  NET_CFG_IF_RX_Q_SIZE                   100
+#define  NET_CFG_IF_TX_DEALLOC_Q_SIZE           100
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                        NETWORK CONFIGURATION
+*
+* Note(s) : (1) uC/TCP-IP code may call optimized assembly functions. Optimized assembly files/functions must be included
+*               in the project to be enabled. Optimized functions are located in files under folders:
+*
+*                   $uC-TCPIP/Ports/<processor>/<compiler>
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+                                                                /* Configure network protocol suite's assembly ...      */
+                                                                /* ... optimization (see Note #1) :                     */
+#define  NET_CFG_OPTIMIZE_ASM_EN                DEF_DISABLED
+                                                                /*   DEF_DISABLED       Assembly optimization DISABLED  */
+                                                                /*   DEF_ENABLED        Assembly optimization ENABLED   */
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                     NETWORK DEBUG CONFIGURATION
+*
+* Note(s) : (1) Configure NET_DBG_CFG_MEM_CLR_EN to enable/disable the network protocol suite from clearing
+*               internal data structure memory buffers; a convenient feature while debugging.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+                                                                /* Configure memory clear feature  (see Note #1) :      */
+#define  NET_DBG_CFG_MEM_CLR_EN                 DEF_DISABLED
+                                                                /*   DEF_DISABLED  Data structure clears DISABLED       */
+                                                                /*   DEF_ENABLED   Data structure clears ENABLED        */
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                NETWORK ARGUMENT CHECK CONFIGURATION
+*
+* Note(s) : (1) Configure NET_ERR_CFG_ARG_CHK_EXT_EN to enable/disable the network protocol suite external
+*               argument check feature :
+*
+*               (a) When ENABLED,  ALL arguments received from any port interface provided by the developer
+*                   or application are checked/validated.
+*
+*               (b) When DISABLED, NO  arguments received from any port interface provided by the developer
+*                   or application are checked/validated.
+*
+*           (2) Configure NET_ERR_CFG_ARG_CHK_DBG_EN to enable/disable the network protocol suite internal,
+*               debug argument check feature :
+*
+*               (a) When ENABLED,     internal arguments are checked/validated to debug the network protocol
+*                   suite.
+*
+*               (b) When DISABLED, NO internal arguments are checked/validated to debug the network protocol
+*                   suite.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+                                                                /* Configure external argument check feature ...        */
+                                                                /* ... (see Note #1) :                                  */
+#define  NET_ERR_CFG_ARG_CHK_EXT_EN             DEF_ENABLED
+                                                                /*   DEF_DISABLED     Argument check DISABLED           */
+                                                                /*   DEF_ENABLED      Argument check ENABLED            */
+
+                                                                /* Configure internal argument check feature ...        */
+                                                                /* ... (see Note #2) :                                  */
+#define  NET_ERR_CFG_ARG_CHK_DBG_EN             DEF_DISABLED
+                                                                /*   DEF_DISABLED     Argument check DISABLED           */
+                                                                /*   DEF_ENABLED      Argument check ENABLED            */
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                               NETWORK COUNTER MANAGEMENT CONFIGURATION
+*
+* Note(s) : (1) Configure NET_CTR_CFG_STAT_EN to enable/disable network protocol suite statistics counters.
+*
+*           (2) Configure NET_CTR_CFG_ERR_EN  to enable/disable network protocol suite error      counters.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+                                                                /* Configure statistics counter feature (see Note #1) : */
+#define  NET_CTR_CFG_STAT_EN                    DEF_DISABLED
+                                                                /*   DEF_DISABLED     Stat  counters DISABLED           */
+                                                                /*   DEF_ENABLED      Stat  counters ENABLED            */
+
+                                                                /* Configure error      counter feature (see Note #2) : */
+#define  NET_CTR_CFG_ERR_EN                     DEF_DISABLED
+                                                                /*   DEF_DISABLED     Error counters DISABLED           */
+                                                                /*   DEF_ENABLED      Error counters ENABLED            */
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                               NETWORK TIMER MANAGEMENT CONFIGURATION
+*
+* Note(s) : (1) Configure NET_TMR_CFG_NBR_TMR with the desired number of network TIMER objects.
+*
+*               Timers are required for :
+*
+*               (a) ARP & NDP cache entries
+*               (b) IP        fragment reassembly
+*               (c) TCP       state machine connections
+*               (d) IF        Link status check-up
+*
+*           (2) Configure NET_TMR_CFG_TASK_FREQ to schedule the execution frequency of the network timer
+*               task -- how often NetTmr_TaskHandler() is scheduled to run per second as implemented in
+*               NetTmr_Task().
+*
+*               (a) NET_TMR_CFG_TASK_FREQ  MUST NOT be configured as a floating-point frequency.
+*
+*               See also 'net_tmr.h  NETWORK TIMER TASK TIME DEFINES  Notes #1 & #2'
+*                      & 'net_tmr.c  NetTmr_Task()  Notes #1 & #2'.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#define  NET_TMR_CFG_NBR_TMR                    100
+#define  NET_TMR_CFG_TASK_FREQ                  10
+
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                NETWORK INTERFACE LAYER CONFIGURATION
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#define  NET_IF_CFG_MAX_NBR_IF                  1
+
+                                                                /* Configure specific interface(s) :                    */
+#define  NET_IF_CFG_LOOPBACK_EN                 DEF_DISABLED
+
+#define  NET_IF_CFG_ETHER_EN                    DEF_ENABLED
+
+#define  NET_IF_CFG_WIFI_EN                     DEF_DISABLED
+                                                                /*   DEF_DISABLED      Interface type DISABLED          */
+                                                                /*   DEF_ENABLED       interface type ENABLED           */
+
+#define  NET_IF_CFG_TX_SUSPEND_TIMEOUT_MS       1
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                           ADDRESS RESOLUTION PROTOCOL LAYER CONFIGURATION
+*
+* Note(s) : (1) Address resolution protocol ONLY required for IPv4.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#define  NET_ARP_CFG_CACHE_NBR                  3
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                           NEIGHBOR DISCOVERY PROTOCOL LAYER CONFIGURATION
+*
+* Note(s) : (1) Neighbor Discovery Protocol ONLY required for IPv6.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#define  NET_NDP_CFG_CACHE_NBR                  5
+#define  NET_NDP_CFG_DEST_NBR                   5
+#define  NET_NDP_CFG_PREFIX_NBR                 5
+#define  NET_NDP_CFG_ROUTER_NBR                 1
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                            INTERNET PROTOCOL LAYER VERSION CONFIGURATION
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                                                IPv4
+*********************************************************************************************************
+*/
+                                                                /* Configure IPv4.                                      */
+#define  NET_IPv4_CFG_EN                        DEF_ENABLED
+                                                                /*   DEF_DISABLED    IPv4 disabled.                     */
+                                                                /*   DEF_ENABLED     IPv4 enabled.                      */
+
+
+#define  NET_IPv4_CFG_IF_MAX_NBR_ADDR           1
+
+/*
+*********************************************************************************************************
+*                                                IPv6
+*********************************************************************************************************
+*/
+
+                                                                /* Configure IPv6.                                      */
+#define  NET_IPv6_CFG_EN                        DEF_DISABLED
+                                                                /*   DEF_DISABLED    IPv6 disabled.                     */
+                                                                /*   DEF_ENABLED     IPv6 enabled.                      */
+
+                                                                /* Configure IPv6 Stateless Address Auto-Configuration. */
+#define  NET_IPv6_CFG_ADDR_AUTO_CFG_EN          DEF_ENABLED
+                                                                /*   DEF_DISABLED    IPv6 Auto-Cfg disabled.            */
+                                                                /*   DEF_ENABLED     IPv6 Auto-Cfg enabled.             */
+
+                                                                /* Configure IPv6 Duplication Address Detection (DAD).  */
+#define  NET_IPv6_CFG_DAD_EN                    DEF_ENABLED
+                                                                /*   DEF_DISABLED    IPv6 DAD disabled.                 */
+                                                                /*   DEF_ENABLED     IPv6 DAD enabled.                  */
+
+#define  NET_IPv6_CFG_IF_MAX_NBR_ADDR           2
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                  INTERNET GROUP MANAGEMENT PROTOCOL(MULTICAST) LAYER CONFIGURATION
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+                                                                /* Configure IPv4 multicast support :                   */
+#define  NET_MCAST_CFG_IPv4_RX_EN               DEF_ENABLED
+#define  NET_MCAST_CFG_IPv4_TX_EN               DEF_ENABLED
+                                                                /*   DEF_DISABLED    Multicast rx or tx disabled.       */
+                                                                /*   DEF_ENABLED     Multicast rx or tx enabled.        */
+
+#define  NET_MCAST_CFG_HOST_GRP_NBR_MAX         2
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                 NETWORK SOCKET LAYER CONFIGURATION
+*
+* Note(s) : (1) The maximum accept queue size represents the number of connection that can be queued by
+*               the stack before being accepted. For a TCP server when a connection is queued, it means
+*               that the SYN, ACK packet has been sent back, so the remote host can start transmitting
+*               data once the connection is queued and the stack will queue up all data received until
+*               the connection is accepted and the data is read.
+*
+*           (2) Receive and transmit queue size MUST be properly configured to optimize performance.
+*
+*               (a) It represents the number of bytes that can be queued by one socket. It's important
+*                   that all socket are not able to queue more data than what the device can hold in its
+*                   buffers.
+*
+*               (b) The size should be also a multiple of the maximum segment size (MSS) to optimize
+*                   performance. UDP MSS is 1470 and TCP MSS is 1460.
+*
+*               (c) RX and TX queue size can be reduce at runtime using socket option API.
+*
+*               (d) Window calculation example:
+*
+*                       Number of TCP connection  : 2
+*                       Number of UDP connection  : 0
+*                       Number of RX large buffer : 10
+*                       Number of TX Large buffer : 6
+*                       Number of TX small buffer : 2
+*                       Size of RX large buffer   : 1518
+*                       Size of TX large buffer   : 1518
+*                       Size of TX small buffer   : 60
+*
+*                       TCP MSS RX                = 1460
+*                       TCP MSS TX large buffer   = 1460
+*                       TCP MSS TX small buffer   = 0
+*
+*                       Maximum receive  window   = (10 * 1460)           = 14600 bytes
+*                       Maximum transmit window   = (6  * 1460) + (2 * 0) = 8760  bytes
+*
+*                       RX window size per socket = (14600 / 2)           =  7300 bytes
+*                       TX window size per socket = (8760  / 2)           =  4380 bytes
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#define  NET_SOCK_CFG_SOCK_NBR_TCP              2
+#define  NET_SOCK_CFG_SOCK_NBR_UDP              1
+
+                                                                /* Configure socket select functionality :              */
+#define  NET_SOCK_CFG_SEL_EN                    DEF_ENABLED
+                                                                /*   DEF_DISABLED  Socket select  DISABLED              */
+                                                                /*   DEF_ENABLED   Socket select  ENABLED               */
+
+                                                                /* Configure stream-type sockets' accept queue          */
+#define  NET_SOCK_CFG_CONN_ACCEPT_Q_SIZE_MAX    2
+
+
+                                                                /* Configure sockets' buffer sizes in number of octets  */
+                                                                /* (see Note #2):                                       */
+#define  NET_SOCK_CFG_RX_Q_SIZE_OCTET           4096
+#define  NET_SOCK_CFG_TX_Q_SIZE_OCTET           4096
+
+
+/* ==================================  ADVANCED SOCKET CONFIGURATION: DEFAULT VALUES ================================== */
+/* By default sockets are set to block. Add the following define to set all sockets as non-blocking. Note that it's     */
+/* possible to change socket's blocking mode at runtime using socket option API.                                        */
+/*                                                                                                                      */
+/*     #define  NET_SOCK_DFLT_NO_BLOCK_EN                     DEF_ENABLED                                               */
+/*                                                                                                                      */
+/* By default random port start at 65000, redefine the following define to modify where random port start:              */
+/*                                                                                                                      */
+/*     #define  NET_SOCK_DFLT_PORT_NBR_RANDOM_BASE            65000u                                                    */
+/*                                                                                                                      */
+/* When a socket is set as blocking the following default timeout values are used. Redefine the following defines to    */
+/* change default timeouts. Timeout values may also be configured with network time constant, NET_TMR_TIME_INFINITE,    */
+/* to never time out. Note that it's possible to change at runtime any timeout values using Socket option API.          */
+/*                                                                                                                      */
+/*     #define  NET_SOCK_DFLT_TIMEOUT_RX_Q_MS                 10000u                                                    */
+/*     #define  NET_SOCK_DFLT_TIMEOUT_CONN_REQ_MS             10000u                                                    */
+/*     #define  NET_SOCK_DFLT_TIMEOUT_CONN_ACCEPT_MS          10000u                                                    */
+/*     #define  NET_SOCK_DFLT_TIMEOUT_CONN_CLOSE_MS           10000u                                                    */
+/* ==================================================================================================================== */
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                          TRANSMISSION CONTROL PROTOCOL LAYER CONFIGURATION
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+                                                                /* Configure TCP support :                              */
+#define  NET_TCP_CFG_EN                         DEF_ENABLED
+                                                                /*   DEF_DISABLED  TCP layer  DISABLED                  */
+                                                                /*   DEF_ENABLED   TCP layer  ENABLED                   */
+
+/* ========================================= ADVANCED TCP LAYER CONFIGURATION ========================================= */
+/* By default TCP RX and TX windows are set to equal the socket RX and TX queue sizes. Default values can be changed by */
+/* redefining the following defines. TCP windows must be properly configured to optimize performance (see note about    */
+/* Socket TX and RX windows). Note that it's possible to decrease window size at run time using Socket option API.      */
+/*                                                                                                                      */
+/*     #define  NET_TCP_DFLT_RX_WIN_SIZE_OCTET      NET_SOCK_CFG_RX_Q_SIZE_OCTET                                        */
+/*     #define  NET_TCP_DFLT_TX_WIN_SIZE_OCTET      NET_SOCK_CFG_TX_Q_SIZE_OCTET                                        */
+/*                                                                                                                      */
+/* As shown in the TCP state diagram (see RFC #793), before moving from 'TIME-WAIT' state to 'CLOSED' state a timeout   */
+/* (2MSL) must expire. This means that the TCP connection cannot be made available for subsequent TCP connections until */
+/* this timeout. It can be a problem for embedded systems with low resources especially when many TCP connections are   */
+/* made in a small period of time since it is possible to run out of free TCP connections quickly. Therefore this       */
+/* timeout is set to 0 by default to avoid this kind of problem and the connection is made available as soon as the     */
+/* 'TIME-WAIT' state is reached. However, it's possible to set the default MSL timeout to something else by redefining  */
+/* the following define. Note that it is possible to change the MSL timeout for a specific TCP connection using Socket  */
+/* option API.                                                                                                          */
+/*                                                                                                                      */
+/*     #define  NET_TCP_DFLT_TIMEOUT_CONN_MAX_SEG_SEC       0u                                                          */
+/*                                                                                                                      */
+/* To avoid leaving a connection in the FIN_WAIT_2 state forever when a connection moves from the 'FIN_WAIT_1' state to */
+/* the FIN_WAIT_2, the TCP connection's timer is set to 15 second, and when it expires the connection is dropped. Thus, */
+/* if the other host doesn't response to the close request, the connection will still be closed after the timeout.      */
+/* This default timeout can be change by redefining the following define.                                               */
+/*                                                                                                                      */
+/*     #define  NET_TCP_DFLT_TIMEOUT_CONN_FIN_WAIT_2_SEC    15u                                                         */
+/*                                                                                                                      */
+/* The number of TCP connections is configured following the number of TCP sockets and the accept queue size when the   */
+/* MSL is set to 0 ms. However, since the default MSL can be modified, it might be needed to increase the number of TCP */
+/* connections to establish more connections when waiting for the MSL expiration. It is possible to add more TCP        */
+/* connections by defining the following define.                                                                        */
+/*                                                                                                                      */
+/*     #define  NET_TCP_CFG_NBR_CONN                        0u                                                          */
+/*                                                                                                                      */
+/* By default an 'ACK' is generated within 500 ms of the arrival of the first unacknowledged packet, as specified in    */
+/* RFC #2581, Section 4.2. However it's possible to modify this value by defining the following define.                 */
+/*                                                                                                                      */
+/*     #define  NET_TCP_DFLT_TIMEOUT_CONN_ACK_DLY_MS        500u                                                        */
+/*                                                                                                                      */
+/* When a socket is set as blocking the following default timeout values are used. Redefine the following defines to    */
+/* change default timeout. Timeout values may also be configured with network time constant, NET_TMR_TIME_INFINITE,     */
+/* to never time out. Note that it's possible to change at runtime any timeout values using Socket option API.          */
+/*     #define  NET_TCP_DFLT_TIMEOUT_CONN_RX_Q_MS           1000u                                                       */
+/*     #define  NET_TCP_DFLT_TIMEOUT_CONN_TX_Q_MS           1000u                                                       */
+/* ==================================================================================================================== */
+
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                             USER DATAGRAM PROTOCOL LAYER CONFIGURATION
+*
+* Note(s) : (1) Configure NET_UDP_CFG_APP_API_SEL with the desired configuration for demultiplexing
+*               UDP datagrams to application connections :
+*
+*                   NET_UDP_APP_API_SEL_SOCK        Demultiplex UDP datagrams to BSD sockets ONLY.
+*                   NET_UDP_APP_API_SEL_APP         Demultiplex UDP datagrams to application-specific
+*                                                       connections ONLY.
+*                   NET_UDP_APP_API_SEL_SOCK_APP    Demultiplex UDP datagrams to BSD sockets first;
+*                                                       if NO socket connection found to demultiplex
+*                                                       a UDP datagram, demultiplex to application-
+*                                                       specific connection.
+*
+*               See also 'net_udp.c  NetUDP_RxPktDemuxDatagram()  Note #1'
+*                      & 'net_udp.c  NetUDP_RxPktDemuxAppData()   Note #1'.
+*
+*           (2) (a) RFC #1122, Section 4.1.3.4 states that "an application MAY optionally ... discard
+*                   ... [or allow] ... received ... UDP datagrams without checksums".
+*
+*               (b) Configure NET_UDP_CFG_RX_CHK_SUM_DISCARD_EN to enable/disable discarding of UDP
+*                   datagrams received with NO computed check-sum :
+*
+*                   (1) When ENABLED,  ALL UDP datagrams received without a check-sum are discarded.
+*
+*                   (2) When DISABLED, ALL UDP datagrams received without a check-sum are flagged so
+*                       that application(s) may handle &/or discard.
+*
+*               See also 'net_udp.c  NetUDP_RxPktValidate()  Note #4d3A'.
+*
+*           (3) (a) RFC #1122, Section 4.1.3.4 states that "an application MAY optionally be able to
+*                   control whether a UDP checksum will be generated".
+*
+*               (b) Configure NET_UDP_CFG_TX_CHK_SUM_EN to enable/disable transmitting UDP datagrams
+*                   with check-sums :
+*
+*                   (1) When ENABLED,  ALL UDP datagrams are transmitted with    a computed check-sum.
+*
+*                   (2) When DISABLED, ALL UDP datagrams are transmitted without a computed check-sum.
+*
+*               See also 'net_udp.c  NetUDP_TxPktPrepareHdr()  Note #3b'.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+                                                                /* Configure UDP Receive Check-Sum Discard feature ...  */
+                                                                /* ... (see Note #2b) :                                 */
+#define  NET_UDP_CFG_RX_CHK_SUM_DISCARD_EN      DEF_DISABLED
+                                                                /*   DEF_DISABLED  UDP Check-Sums  Received without ... */
+                                                                /*                     Check-Sums Validated             */
+                                                                /*   DEF_ENABLED   UDP Datagrams  Received without ...  */
+                                                                /*                     Check-Sums Discarded             */
+
+                                                                /* Configure UDP Transmit Check-Sum feature ...         */
+                                                                /* ... (see Note #3b) :                                 */
+#define  NET_UDP_CFG_TX_CHK_SUM_EN              DEF_DISABLED
+                                                                /*   DEF_DISABLED  Transmit Check-Sums  DISABLED        */
+                                                                /*   DEF_ENABLED   Transmit Check-Sums  ENABLED         */
+
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                               NETWORK SECURITY MANAGER CONFIGURATION
+*
+* Note(s): (1) The network security layer can be enabled ONLY if the application project contains a secure module
+*              supported by uC/TCPIP such as:
+*
+*              (a) NanoSSL provided by Mocana.
+*              (b) CyaSSL  provided by YaSSL.
+*
+*          (2) The network security port must be also added to the project. Security port can be found under the folder:
+*
+*                 $uC-TCPIP/Secure/<module>
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+                                                                /* Configure network security layer (See Note #1 & #2): */
+#define  NET_SECURE_CFG_EN                      DEF_DISABLED
+                                                                /*   DEF_DISABLED  Security layer  DISABLED             */
+                                                                /*   DEF_ENABLED   Security layer  ENABLED              */
+
+#define  NET_SECURE_CFG_MAX_NBR_SOCK_SERVER     2u              /* Configure total number of server secure sockets.     */
+#define  NET_SECURE_CFG_MAX_NBR_SOCK_CLIENT     2u              /* Configure total number of client secure sockets.     */
+
+#define  NET_SECURE_CFG_MAX_CERT_LEN            1500u           /* Configure servers certificate maximum length (bytes) */
+#define  NET_SECURE_CFG_MAX_KEY_LEN             1500u           /* Configure servers key maximum length (bytes)         */
+
+                                                                /* Configure maximum number of certificate authorities  */
+#define  NET_SECURE_CFG_MAX_NBR_CA              1u              /* that can be installed.                               */
+
+#define  NET_SECURE_CFG_MAX_CA_CERT_LEN         1500u           /* Configure CA certificate maximum length (bytes)      */
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                               INTERFACE CHECKSUM OFFLOAD CONFIGURATION
+*
+* Note(s): (1) These configuration can be enabled only if all your interfaces support specific checksum offload
+*              option.
+*
+*          (2) By default a driver should enabled the all checksum offload option.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+/* ========================================== ADVANCED OFFLOAD CONFIGURATION ========================================== */
+/* By default all checksum are validated by the stack however it is possible to enable or disable specific checksum     */
+/* validate and calculation if the interface controller is able to achieve it. You can add the following define in this */
+/* file to change the default behavior.                                                                                 */
+/*                                                                                                                      */
+/* -------------------------------------------------- IPv4 CHECKSUM --------------------------------------------------- */
+/*                                                  Configure validation in reception.                                  */
+/* #define  NET_IPV4_CFG_CHK_SUM_OFFLOAD_RX_EN  DEF_DISABLED                                                            */
+/*                                                                                                                      */
+/*                                                  Configure calculation in transmission.                              */
+/* #define  NET_IPV4_CFG_CHK_SUM_OFFLOAD_TX_EN  DEF_DISABLED                                                            */
+/*                                                                                                                      */
+/*                                                                                                                      */
+/* -------------------------------------------------- ICMP CHECKSUM --------------------------------------------------- */
+/*                                                  Configure validation in reception.                                  */
+/* #define  NET_ICMP_CFG_CHK_SUM_OFFLOAD_RX_EN  DEF_DISABLED                                                            */
+/*                                                                                                                      */
+/*                                                  Configure calculation in transmission.                              */
+/* #define  NET_ICMP_CFG_CHK_SUM_OFFLOAD_TX_EN  DEF_DISABLED                                                            */
+/*                                                                                                                      */
+/*                                                                                                                      */
+/* --------------------------------------------------- UDP CHECKSUM --------------------------------------------------- */
+/*                                                  Configure validation in reception.                                  */
+/* #define  NET_UDP_CFG_CHK_SUM_OFFLOAD_RX_EN   DEF_DISABLED                                                            */
+/*                                                                                                                      */
+/*                                                  Configure calculation in transmission.                              */
+/* #define  NET_UDP_CFG_CHK_SUM_OFFLOAD_TX_EN   DEF_DISABLED                                                            */
+/*                                                                                                                      */
+/*                                                                                                                      */
+/* --------------------------------------------------- TCP CHECKSUM --------------------------------------------------- */
+/*                                                  Configure validation in reception.                                  */
+/* #define  NET_TCP_CFG_CHK_SUM_OFFLOAD_RX_EN   DEF_DISABLED                                                            */
+/*                                                                                                                      */
+/*                                                  Configure calculation in transmission.                              */
+/* #define  NET_TCP_CFG_CHK_SUM_OFFLOAD_TX_EN   DEF_DISABLED                                                            */
+/* ==================================================================================================================== */
+
+
+/* ======================================================= END ======================================================== */
+#endif  /* NET_CFG_MODULE_PRESENT */
+
+#define  NET_IPV4_CFG_CHK_SUM_OFFLOAD_RX_EN  DEF_DISABLED
+#define  NET_IPV4_CFG_CHK_SUM_OFFLOAD_TX_EN  DEF_DISABLED
+#define  NET_ICMP_CFG_CHK_SUM_OFFLOAD_RX_EN  DEF_DISABLED
+#define  NET_ICMP_CFG_CHK_SUM_OFFLOAD_TX_EN  DEF_DISABLED
+#define  NET_UDP_CFG_CHK_SUM_OFFLOAD_RX_EN  DEF_DISABLED
+#define  NET_UDP_CFG_CHK_SUM_OFFLOAD_TX_EN  DEF_DISABLED
+#define  NET_TCP_CFG_CHK_SUM_OFFLOAD_RX_EN  DEF_DISABLED
+#define  NET_TCP_CFG_CHK_SUM_OFFLOAD_TX_EN  DEF_DISABLED

src/APP/Aufgabe2/ps7/core0/cfg/net_xil_ether_lite_dev_cfg.h

@@ -0,0 +1,115 @@
+/*
+*********************************************************************************************************
+*                                             uC/TCP-IP
+*                                      The Embedded TCP/IP Suite
+*
+*                         (c) Copyright 2004-2015; Micrium, Inc.; Weston, FL
+*
+*                  All rights reserved.  Protected by international copyright laws.
+*
+*                  uC/TCP-IP is provided in source form to registered licensees ONLY.  It is
+*                  illegal to distribute this source code to any third party unless you receive
+*                  written permission by an authorized Micrium representative.  Knowledge of
+*                  the source code may NOT be used to develop a similar product.
+*
+*                  Please help us continue to provide the Embedded community with the finest
+*                  software available.  Your honesty is greatly appreciated.
+*
+*                  You can find our product's user manual, API reference, release notes and
+*                  more information at: https://doc.micrium.com
+*
+*                  You can contact us at: http://www.micrium.com
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                  NETWORK DEVICE CONFIGURATION FILE
+*
+*                                              TEMPLATE
+*
+* Filename : net_dev_cfg.h
+* Version  : V3.00.00
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                               MODULE
+*
+* Note(s) : (1) This network device configuration header file is protected from multiple pre-processor
+*               inclusion through use of the network module present pre-processor macro definition.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#ifndef  NET_DEV_CFG_MODULE_PRESENT                             /* See Note #1.                                         */
+#define  NET_DEV_CFG_MODULE_PRESENT
+
+#include   <Source/net_cfg_net.h>
+
+#ifdef  NET_IF_ETHER_MODULE_EN
+#include   <IF/net_if_ether.h>
+#endif
+
+#ifdef  NET_IF_WIFI_MODULE_EN
+#include   <IF/net_if_wifi.h>
+#endif
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                    NETWORK DEVICE CONFIGURATION
+*
+* Note(s) : (1) (a) Each network device maps to a unique, developer-configured device configuration that
+*                   MUST be defined in application files, typically 'net_dev_cfg.c', & SHOULD be forward-
+*                   declared with the exact same name & type in order to be used by the application during
+*                   calls to NetIF_Add().
+*
+*               (b) Since these device configuration structures are referenced ONLY by application files,
+*                   there is NO required naming convention for these configuration structures.  However,
+*                   the following naming convention is suggested for all developer-configured network
+*                   device configuration structures :
+*
+*                       NetDev_Cfg_<Device>[_Number]
+*
+*                           where
+*                                   <Device>        Name of device or device driver
+*                                   [Number]        Network device number for each specific instance of
+*                                                       device (optional if the development board does NOT
+*                                                       support multiple instances of the specific device)
+*
+*                       Examples :
+*
+*                           NET_DEV_CFG_ETHER  NetDev_Cfg_MACB;         Ethernet configuration for MACB
+*
+*                           NET_DEV_CFG_ETHER  NetDev_Cfg_FEC_0;        Ethernet configuration for FEC #0
+*                           NET_DEV_CFG_ETHER  NetDev_Cfg_FEC_1;        Ethernet configuration for FEC #1
+*
+*                           NET_DEV_CFG_WIFI   NetDev_Cfg_RS9110N21_0;  Wireless configuration for RS9110-N-21
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#ifdef  NET_IF_ETHER_MODULE_EN
+
+extern  NET_DEV_CFG_ETHER  NetDev_AXIEthernetLite_0;
+extern  NET_PHY_CFG_ETHER  NetPhy_Cfg_Ether_0;
+
+#endif  /* NET_IF_ETHER_MODULE_EN */
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                             MODULE END
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#endif  /* NET_DEV_CFG_MODULE_PRESENT */
+

src/APP/Aufgabe2/ps7/core0/cfg/os_cfg.h

@@ -0,0 +1,145 @@
+/*
+*********************************************************************************************************
+*                                                uC/OS-II
+*                                          The Real-Time Kernel
+*                                  uC/OS-II Configuration File for V2.9x
+*
+*                               (c) Copyright 2005-2014, Micrium, Weston, FL
+*                                          All Rights Reserved
+*
+*
+* File    : OS_CFG.H
+* By      : Jean J. Labrosse
+* Version : V2.92.11
+*
+* LICENSING TERMS:
+* ---------------
+*   uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research.
+* If you plan on using  uC/OS-II  in a commercial product you need to contact Micrium to properly license
+* its use in your product. We provide ALL the source code for your convenience and to help you experience
+* uC/OS-II.   The fact that the  source is provided does  NOT  mean that you can use it without  paying a
+* licensing fee.
+*********************************************************************************************************
+*/
+
+#ifndef OS_CFG_H
+#define OS_CFG_H
+
+
+                                       /* ---------------------- MISCELLANEOUS ----------------------- */
+#define OS_APP_HOOKS_EN           1u   /* Application-defined hooks are called from the uC/OS-II hooks */
+#define OS_ARG_CHK_EN             0u   /* Enable (1) or Disable (0) argument checking                  */
+#define OS_CPU_HOOKS_EN           1u   /* uC/OS-II hooks are found in the processor port files         */
+
+#define OS_DEBUG_EN               1u   /* Enable(1) debug variables                                    */
+
+#define OS_EVENT_MULTI_EN         1u   /* Include code for OSEventPendMulti()                          */
+#define OS_EVENT_NAME_EN          1u   /* Enable names for Sem, Mutex, Mbox and Q                      */
+
+#define OS_LOWEST_PRIO           63u   /* Defines the lowest priority that can be assigned ...         */
+                                       /* ... MUST NEVER be higher than 254!                           */
+
+#define OS_MAX_EVENTS            20u   /* Max. number of event control blocks in your application      */
+#define OS_MAX_FLAGS              5u   /* Max. number of Event Flag Groups    in your application      */
+#define OS_MAX_MEM_PART           5u   /* Max. number of memory partitions                             */
+#define OS_MAX_QS                 6u   /* Max. number of queue control blocks in your application      */
+#define OS_MAX_TASKS             20u   /* Max. number of tasks in your application, MUST be >= 2       */
+
+#define OS_SCHED_LOCK_EN          1u   /* Include code for OSSchedLock() and OSSchedUnlock()           */
+
+#define OS_TICK_STEP_EN           1u   /* Enable tick stepping feature for uC/OS-View                  */
+#define OS_TICKS_PER_SEC       1000u   /* Set the number of ticks in one second                        */
+
+#define OS_TLS_TBL_SIZE           0u   /* Size of Thread-Local Storage Table                           */
+
+
+                                       /* --------------------- TASK STACK SIZE ---------------------- */
+#define OS_TASK_TMR_STK_SIZE    128u   /* Timer      task stack size (# of OS_STK wide entries)        */
+#define OS_TASK_STAT_STK_SIZE   128u   /* Statistics task stack size (# of OS_STK wide entries)        */
+#define OS_TASK_IDLE_STK_SIZE   128u   /* Idle       task stack size (# of OS_STK wide entries)        */
+
+
+                                       /* --------------------- TASK MANAGEMENT ---------------------- */
+#define OS_TASK_CHANGE_PRIO_EN    1u   /*     Include code for OSTaskChangePrio()                      */
+#define OS_TASK_CREATE_EN         1u   /*     Include code for OSTaskCreate()                          */
+#define OS_TASK_CREATE_EXT_EN     1u   /*     Include code for OSTaskCreateExt()                       */
+#define OS_TASK_DEL_EN            1u   /*     Include code for OSTaskDel()                             */
+#define OS_TASK_NAME_EN           1u   /*     Enable task names                                        */
+#define OS_TASK_PROFILE_EN        1u   /*     Include variables in OS_TCB for profiling                */
+#define OS_TASK_QUERY_EN          1u   /*     Include code for OSTaskQuery()                           */
+#define OS_TASK_REG_TBL_SIZE      1u   /*     Size of task variables array (#of INT32U entries)        */
+#define OS_TASK_STAT_EN           1u   /*     Enable (1) or Disable(0) the statistics task             */
+#define OS_TASK_STAT_STK_CHK_EN   1u   /*     Check task stacks from statistic task                    */
+#define OS_TASK_SUSPEND_EN        1u   /*     Include code for OSTaskSuspend() and OSTaskResume()      */
+#define OS_TASK_SW_HOOK_EN        1u   /*     Include code for OSTaskSwHook()                          */
+
+
+                                       /* ----------------------- EVENT FLAGS ------------------------ */
+#define OS_FLAG_EN                1u   /* Enable (1) or Disable (0) code generation for EVENT FLAGS    */
+#define OS_FLAG_ACCEPT_EN         1u   /*     Include code for OSFlagAccept()                          */
+#define OS_FLAG_DEL_EN            1u   /*     Include code for OSFlagDel()                             */
+#define OS_FLAG_NAME_EN           1u   /*     Enable names for event flag group                        */
+#define OS_FLAG_QUERY_EN          1u   /*     Include code for OSFlagQuery()                           */
+#define OS_FLAG_WAIT_CLR_EN       1u   /* Include code for Wait on Clear EVENT FLAGS                   */
+#define OS_FLAGS_NBITS           16u   /* Size in #bits of OS_FLAGS data type (8, 16 or 32)            */
+
+
+                                       /* -------------------- MESSAGE MAILBOXES --------------------- */
+#define OS_MBOX_EN                1u   /* Enable (1) or Disable (0) code generation for MAILBOXES      */
+#define OS_MBOX_ACCEPT_EN         1u   /*     Include code for OSMboxAccept()                          */
+#define OS_MBOX_DEL_EN            1u   /*     Include code for OSMboxDel()                             */
+#define OS_MBOX_PEND_ABORT_EN     1u   /*     Include code for OSMboxPendAbort()                       */
+#define OS_MBOX_POST_EN           1u   /*     Include code for OSMboxPost()                            */
+#define OS_MBOX_POST_OPT_EN       1u   /*     Include code for OSMboxPostOpt()                         */
+#define OS_MBOX_QUERY_EN          1u   /*     Include code for OSMboxQuery()                           */
+
+
+                                       /* --------------------- MEMORY MANAGEMENT -------------------- */
+#define OS_MEM_EN                 1u   /* Enable (1) or Disable (0) code generation for MEMORY MANAGER */
+#define OS_MEM_NAME_EN            1u   /*     Enable memory partition names                            */
+#define OS_MEM_QUERY_EN           1u   /*     Include code for OSMemQuery()                            */
+
+
+                                       /* ---------------- MUTUAL EXCLUSION SEMAPHORES --------------- */
+#define OS_MUTEX_EN               1u   /* Enable (1) or Disable (0) code generation for MUTEX          */
+#define OS_MUTEX_ACCEPT_EN        1u   /*     Include code for OSMutexAccept()                         */
+#define OS_MUTEX_DEL_EN           1u   /*     Include code for OSMutexDel()                            */
+#define OS_MUTEX_QUERY_EN         1u   /*     Include code for OSMutexQuery()                          */
+
+
+                                       /* ---------------------- MESSAGE QUEUES ---------------------- */
+#define OS_Q_EN                   1u   /* Enable (1) or Disable (0) code generation for QUEUES         */
+#define OS_Q_ACCEPT_EN            1u   /*     Include code for OSQAccept()                             */
+#define OS_Q_DEL_EN               1u   /*     Include code for OSQDel()                                */
+#define OS_Q_FLUSH_EN             1u   /*     Include code for OSQFlush()                              */
+#define OS_Q_PEND_ABORT_EN        1u   /*     Include code for OSQPendAbort()                          */
+#define OS_Q_POST_EN              1u   /*     Include code for OSQPost()                               */
+#define OS_Q_POST_FRONT_EN        1u   /*     Include code for OSQPostFront()                          */
+#define OS_Q_POST_OPT_EN          1u   /*     Include code for OSQPostOpt()                            */
+#define OS_Q_QUERY_EN             1u   /*     Include code for OSQQuery()                              */
+
+
+                                       /* ------------------------ SEMAPHORES ------------------------ */
+#define OS_SEM_EN                 1u   /* Enable (1) or Disable (0) code generation for SEMAPHORES     */
+#define OS_SEM_ACCEPT_EN          1u   /*    Include code for OSSemAccept()                            */
+#define OS_SEM_DEL_EN             1u   /*    Include code for OSSemDel()                               */
+#define OS_SEM_PEND_ABORT_EN      1u   /*    Include code for OSSemPendAbort()                         */
+#define OS_SEM_QUERY_EN           1u   /*    Include code for OSSemQuery()                             */
+#define OS_SEM_SET_EN             1u   /*    Include code for OSSemSet()                               */
+
+
+                                       /* --------------------- TIME MANAGEMENT ---------------------- */
+#define OS_TIME_DLY_HMSM_EN       1u   /*     Include code for OSTimeDlyHMSM()                         */
+#define OS_TIME_DLY_RESUME_EN     1u   /*     Include code for OSTimeDlyResume()                       */
+#define OS_TIME_GET_SET_EN        1u   /*     Include code for OSTimeGet() and OSTimeSet()             */
+#define OS_TIME_TICK_HOOK_EN      1u   /*     Include code for OSTimeTickHook()                        */
+
+
+                                       /* --------------------- TIMER MANAGEMENT --------------------- */
+#define OS_TMR_EN                 0u   /* Enable (1) or Disable (0) code generation for TIMERS         */
+#define OS_TMR_CFG_MAX           16u   /*     Maximum number of timers                                 */
+#define OS_TMR_CFG_NAME_EN        1u   /*     Determine timer names                                    */
+#define OS_TMR_CFG_WHEEL_SIZE     7u   /*     Size of timer wheel (#Spokes)                            */
+#define OS_TMR_CFG_TICKS_PER_SEC 10u   /*     Rate at which timer management task runs (Hz)            */
+
+#endif

src/APP/Aufgabe2/ps7/core0/cfg/shell_cfg.h

@@ -0,0 +1,96 @@
+/*
+*********************************************************************************************************
+*                                              uC/Shell
+*                                            Shell Utility
+*
+*                          (c) Copyright 2007-2013; Micrium, Inc.; Weston, FL
+*
+*               All rights reserved.  Protected by international copyright laws.
+*
+*               uC/Shell is provided in source form to registered licensees ONLY.  It is
+*               illegal to distribute this source code to any third party unless you receive
+*               written permission by an authorized Micrium representative.  Knowledge of
+*               the source code may NOT be used to develop a similar product.
+*
+*               Please help us continue to provide the Embedded community with the finest
+*               software available.  Your honesty is greatly appreciated.
+*
+*               You can contact us at www.micrium.com.
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                  SHELL UTILITY CONFIGURATION FILE
+*
+*                                              TEMPLATE
+*
+* Filename      : shell_cfg.h
+* Version       : V1.03.01
+* Programmer(s) : SR
+*                 FBJ
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                                 MODULE
+*********************************************************************************************************
+*/
+
+#ifndef  SHELL_CFG_H
+#define  SHELL_CFG_H
+
+
+/*
+*********************************************************************************************************
+*                                                 SHELL
+*
+* Note(s) : (1) Defines the size of the table used to hold the various modules' command tables.  Command
+*               tables are added using the Shell_CmdTblAdd() function.  Once the table is full, it is not
+*               possible to add any more unless Shell_CmdTblRem() is first called.
+*
+*           (2) Defines the maximum number or argument(s) a command may pass on the string holding the
+*               complete command.  The minimum value is 1.
+*
+*           (3) Defines the maximum length for module command name, including the NULL character.
+*********************************************************************************************************
+*/
+
+#define  SHELL_CFG_CMD_TBL_SIZE                            3    /* Cfg Shell cmd tbl size  (see Note #1).               */
+#define  SHELL_CFG_CMD_ARG_NBR_MAX                         5    /* Cfg cmd max nbr of arg  (see Note #2).               */
+
+#define  SHELL_CFG_MODULE_CMD_NAME_LEN_MAX                 6    /* Cfg module cmd name len (See Note #3).               */
+
+
+/*
+*********************************************************************************************************
+*                                                TRACING
+*********************************************************************************************************
+*/
+
+#ifndef  TRACE_LEVEL_OFF
+#define  TRACE_LEVEL_OFF                                  0u
+#endif
+
+#ifndef  TRACE_LEVEL_INFO
+#define  TRACE_LEVEL_INFO                                 1u
+#endif
+
+#ifndef  TRACE_LEVEL_DBG
+#define  TRACE_LEVEL_DBG                                  2u
+#endif
+
+#define  SHELL_TRACE_LEVEL                   TRACE_LEVEL_OFF
+#define  SHELL_TRACE                                  printf
+
+
+/*
+*********************************************************************************************************
+*                                          MODULE END
+*********************************************************************************************************
+*/
+
+#endif

src/APP/Aufgabe2/ps7/core0/cfg/terminal_cfg.h

@@ -0,0 +1,70 @@
+/*
+*********************************************************************************************************
+*                                               uC/Shell
+*                                            Shell utility
+*
+*                             (c) Copyright 2007-2013; Micrium, Inc.; Weston, FL
+*
+*                   All rights reserved.  Protected by international copyright laws.
+*                   Knowledge of the source code may not be used to write a similar
+*                   product.  This file may only be used in accordance with a license
+*                   and should not be redistributed in any way.
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                               TERMINAL
+*
+*                                      CONFIGURATION TEMPLATE FILE
+*
+* Filename      : terminal_cfg.h
+* Version       : V1.03.01
+* Programmer(s) : BAN
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                                           TASKS PRIORITIES
+*********************************************************************************************************
+*/
+
+#define  TERMINAL_OS_CFG_TASK_PRIO                        16u
+
+
+/*
+*********************************************************************************************************
+*                                              STACK SIZES
+*                             Size of the task stacks (# of OS_STK entries)
+*********************************************************************************************************
+*/
+
+#define  TERMINAL_OS_CFG_TASK_STK_SIZE                  1024u
+
+
+/*
+*********************************************************************************************************
+*                                               TERMINAL
+*
+* Note(s) : (1) Defines the maximum length of a command entered on the terminal, in characters.
+*
+*           (2) Defines the maximum path length of the Current Working Directory (CWD).
+*
+*           (3) Enables/disables command history.
+*
+*           (4) Defines the number of items to hold in the command history.
+*
+*           (5) Defines the length of a item in the command history.  If a command is entered into the
+*               terminal that exceeds this length, then only the first characters, up to this number of
+*               characters, will be copied into the command history.
+*********************************************************************************************************
+*/
+
+#define  TERMINAL_CFG_MAX_CMD_LEN                        260u   /* Cfg max cmd  len         (see Note #1).              */
+#define  TERMINAL_CFG_MAX_PATH_LEN                       260u   /* Cfg max path len         (see Note #2).              */
+
+#define  TERMINAL_CFG_HISTORY_EN                 DEF_ENABLED    /* En/dis history           (see Note #3).              */
+#define  TERMINAL_CFG_HISTORY_ITEMS_NBR                   16u   /* Cfg nbr history items    (see Note #4).              */
+#define  TERMINAL_CFG_HISTORY_ITEM_LEN                    64u   /* Cfg history item len     (see Note #5).              */

src/APP/Aufgabe2/ps7/core0/cfg/xparameters.h

@@ -0,0 +1,704 @@
+/******************************************************************/
+
+/* Definition for CPU ID */
+#define XPAR_CPU_ID 0
+
+/* Definitions for peripheral PS7_CORTEXA9_0 */
+#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
+#define XPAR_PS7_CORTEXA9_1_CPU_CLK_FREQ_HZ XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_CORTEXA9_0 */
+#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
+#define XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+
+/******************************************************************/
+
+#undef DEF_DISABLED
+#undef DEF_ENABLED
+#define DEF_ENABLED 1
+#define DEF_DISABLED 0
+
+#include "xparameters_ps.h"
+
+
+
+/******************************************************************/
+
+/* Definitions for driver BRAM */
+#define XPAR_XBRAM_NUM_INSTANCES 1
+
+/* Definitions for peripheral AXI_BRAM_CTRL_0 */
+#define XPAR_AXI_BRAM_CTRL_0_DEVICE_ID 0
+#define XPAR_AXI_BRAM_CTRL_0_DATA_WIDTH 32
+#define XPAR_AXI_BRAM_CTRL_0_ECC 0
+#define XPAR_AXI_BRAM_CTRL_0_FAULT_INJECT 0
+#define XPAR_AXI_BRAM_CTRL_0_CE_FAILING_REGISTERS 0
+#define XPAR_AXI_BRAM_CTRL_0_UE_FAILING_REGISTERS 0
+#define XPAR_AXI_BRAM_CTRL_0_ECC_STATUS_REGISTERS 0
+#define XPAR_AXI_BRAM_CTRL_0_CE_COUNTER_WIDTH 0
+#define XPAR_AXI_BRAM_CTRL_0_ECC_ONOFF_REGISTER 0
+#define XPAR_AXI_BRAM_CTRL_0_ECC_ONOFF_RESET_VALUE 0
+#define XPAR_AXI_BRAM_CTRL_0_WRITE_ACCESS 0
+#define XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR 0x40000000
+#define XPAR_AXI_BRAM_CTRL_0_S_AXI_HIGHADDR 0x40001FFF
+#define XPAR_AXI_BRAM_CTRL_0_S_AXI_CTRL_BASEADDR 0xFFFFFFFF
+#define XPAR_AXI_BRAM_CTRL_0_S_AXI_CTRL_HIGHADDR 0xFFFFFFFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral AXI_BRAM_CTRL_0 */
+#define XPAR_BRAM_0_DEVICE_ID XPAR_AXI_BRAM_CTRL_0_DEVICE_ID
+#define XPAR_BRAM_0_DATA_WIDTH 32
+#define XPAR_BRAM_0_ECC 0
+#define XPAR_BRAM_0_FAULT_INJECT 0
+#define XPAR_BRAM_0_CE_FAILING_REGISTERS 0
+#define XPAR_BRAM_0_UE_FAILING_REGISTERS 0
+#define XPAR_BRAM_0_ECC_STATUS_REGISTERS 0
+#define XPAR_BRAM_0_CE_COUNTER_WIDTH 0
+#define XPAR_BRAM_0_ECC_ONOFF_REGISTER 0
+#define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 0
+#define XPAR_BRAM_0_WRITE_ACCESS 0
+#define XPAR_BRAM_0_BASEADDR 0x40000000
+#define XPAR_BRAM_0_HIGHADDR 0x40001FFF
+
+
+/******************************************************************/
+
+
+/* Definitions for peripheral PS7_DDR_0 */
+#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
+#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver DEVCFG */
+#define XPAR_XDCFG_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_DEV_CFG_0 */
+#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0
+#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000
+#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_DEV_CFG_0 */
+#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
+#define XPAR_XDCFG_0_BASEADDR 0xF8007000
+#define XPAR_XDCFG_0_HIGHADDR 0xF80070FF
+
+
+/******************************************************************/
+
+/* Definitions for driver DMAPS */
+#define XPAR_XDMAPS_NUM_INSTANCES 2
+
+/* Definitions for peripheral PS7_DMA_NS */
+#define XPAR_PS7_DMA_NS_DEVICE_ID 0
+#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
+#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF
+
+
+/* Definitions for peripheral PS7_DMA_S */
+#define XPAR_PS7_DMA_S_DEVICE_ID 1
+#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
+#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_DMA_NS */
+#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
+#define XPAR_XDMAPS_0_BASEADDR 0xF8004000
+#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF
+
+/* Canonical definitions for peripheral PS7_DMA_S */
+#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
+#define XPAR_XDMAPS_1_BASEADDR 0xF8003000
+#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF
+
+
+/******************************************************************/
+
+
+/* Definitions for peripheral PS7_AFI_0 */
+#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
+#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
+
+
+/* Definitions for peripheral PS7_AFI_1 */
+#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000
+#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF
+
+
+/* Definitions for peripheral PS7_AFI_2 */
+#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000
+#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF
+
+
+/* Definitions for peripheral PS7_AFI_3 */
+#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000
+#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
+
+
+/* Definitions for peripheral PS7_DDRC_0 */
+#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
+#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
+
+
+/* Definitions for peripheral PS7_GLOBALTIMER_0 */
+#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200
+#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF
+
+
+/* Definitions for peripheral PS7_GPV_0 */
+#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000
+#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF
+
+
+/* Definitions for peripheral PS7_INTC_DIST_0 */
+#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000
+#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF
+
+
+/* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
+#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
+#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
+
+
+/* Definitions for peripheral PS7_OCMC_0 */
+#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000
+#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF
+
+
+/* Definitions for peripheral PS7_PL310_0 */
+#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000
+#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF
+
+
+/* Definitions for peripheral PS7_PMU_0 */
+#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000
+#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF
+#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000
+#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF
+
+
+/* Definitions for peripheral PS7_QSPI_LINEAR_0 */
+#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
+#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFDFFFFFF
+
+
+/* Definitions for peripheral PS7_RAM_0 */
+#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
+#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
+
+
+/* Definitions for peripheral PS7_RAM_1 */
+#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000
+#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
+
+
+/* Definitions for peripheral PS7_SLCR_0 */
+#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
+#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF
+
+
+/******************************************************************/
+
+/* Definitions for driver GPIO */
+#define XPAR_XGPIO_NUM_INSTANCES 1
+
+/* Definitions for peripheral AXI_GPIO_0 */
+#define XPAR_AXI_GPIO_0_BASEADDR 0x41200000
+#define XPAR_AXI_GPIO_0_HIGHADDR 0x4120FFFF
+#define XPAR_AXI_GPIO_0_DEVICE_ID 0
+#define XPAR_AXI_GPIO_0_INTERRUPT_PRESENT 0
+#define XPAR_AXI_GPIO_0_IS_DUAL 0
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral AXI_GPIO_0 */
+#define XPAR_GPIO_0_BASEADDR 0x41200000
+#define XPAR_GPIO_0_HIGHADDR 0x4120FFFF
+#define XPAR_GPIO_0_DEVICE_ID XPAR_AXI_GPIO_0_DEVICE_ID
+#define XPAR_GPIO_0_INTERRUPT_PRESENT 0
+#define XPAR_GPIO_0_IS_DUAL 0
+
+
+/******************************************************************/
+
+/* Definitions for driver GPIOPS */
+#define XPAR_XGPIOPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_GPIO_0 */
+#define XPAR_PS7_GPIO_0_DEVICE_ID 0
+#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
+#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_GPIO_0 */
+#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
+#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
+#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
+
+
+/******************************************************************/
+
+///* Definitions for driver IICPS */
+//#define XPAR_XIICPS_NUM_INSTANCES 1
+//
+///* Definitions for peripheral PS7_I2C_0 */
+//#define XPAR_PS7_I2C_0_DEVICE_ID 0
+//#define XPAR_PS7_I2C_0_BASEADDR 0xE0004000
+//#define XPAR_PS7_I2C_0_HIGHADDR 0xE0004FFF
+//#define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 111111115
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_I2C_0 */
+#define XPAR_XIICPS_0_DEVICE_ID XPAR_PS7_I2C_0_DEVICE_ID
+#define XPAR_XIICPS_0_BASEADDR 0xE0004000
+#define XPAR_XIICPS_0_HIGHADDR 0xE0004FFF
+#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 111111115
+
+
+/******************************************************************/
+
+/* Definitions for driver QSPIPS */
+#define XPAR_XQSPIPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_QSPI_0 */
+#define XPAR_PS7_QSPI_0_DEVICE_ID 0
+#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000
+#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
+#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000
+#define XPAR_PS7_QSPI_0_QSPI_MODE 2
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_QSPI_0 */
+#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID
+#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000
+#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
+#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000
+#define XPAR_XQSPIPS_0_QSPI_MODE 2
+
+
+/******************************************************************/
+
+/* Definitions for driver SCUWDT */
+#define XPAR_XSCUWDT_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SCUWDT_0 */
+#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
+#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
+#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_SCUWDT_0 */
+#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
+#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
+#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
+
+
+/******************************************************************/
+
+/* Definitions for driver UCOS_EMACPS */
+#define XPAR_UCOS_EMACPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_ETHERNET_0 */
+#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0
+#define XPAR_PS7_ETHERNET_0_BASEADDR 0x00000000
+#define XPAR_PS7_ETHERNET_0_HIGHADDR 0x00000000
+#define XPAR_PS7_ETHERNET_0_CLOCK_FREQ_HZ 0
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_ETHERNET_0 */
+#define XPAR_UCOS_EMACPS_0_NUM_INSTANCES 0
+#define XPAR_UCOS_EMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID
+#define XPAR_UCOS_EMACPS_0_BASEADDR 0x00000000
+#define XPAR_UCOS_EMACPS_0_HIGHADDR 0x00000000
+#define XPAR_UCOS_EMACPS_0_CLOCK_FREQ_HZ 0
+
+
+/******************************************************************/
+
+/* Definitions for driver UCOS_L2CACHEC */
+#define XPAR_UCOS_L2CACHEC_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_L2CACHEC_0 */
+#define XPAR_PS7_L2CACHEC_0_DEVICE_ID 0
+#define XPAR_PS7_L2CACHEC_0_BASEADDR 0xF8F02000
+#define XPAR_PS7_L2CACHEC_0_HIGHADDR 0xF8F02FFF
+
+
+/******************************************************************/
+
+/* Definitions for driver UCOS_SCUC */
+#define XPAR_UCOS_L2CACHEC_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SCUC_0 */
+#define XPAR_PS7_SCUC_0_DEVICE_ID 0
+#define XPAR_PS7_SCUC_0_BASEADDR 0xF8F00000
+#define XPAR_PS7_SCUC_0_HIGHADDR 0xF8F000FC
+
+
+/******************************************************************/
+
+
+/***Definitions for Core_nIRQ/nFIQ interrupts ****/
+/* Definitions for driver UCOS_SCUGIC */
+#define XPAR_XSCUGIC_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SCUGIC_0 */
+#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0
+#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100
+#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FF
+#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_SCUGIC_0 */
+#define XPAR_SCUGIC_0_DEVICE_ID 0
+#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100
+#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FF
+#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000
+
+
+/******************************************************************/
+
+/* Definitions for driver UCOS_SCUTIMER */
+#define XPAR_UCOS_SCUC_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SCUTIMER_0 */
+#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
+#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
+#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F
+
+
+/******************************************************************/
+
+/* Definitions for driver UCOS_SDPS */
+#define XPAR_UCOS_SDPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SD_0 */
+#define XPAR_PS7_SD_0_DEVICE_ID 0
+#define XPAR_PS7_SD_0_BASEADDR 0xE0100000
+#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
+#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_SD_0 */
+#define XPAR_UCOS_SDPS_0_NUM_INSTANCES 0
+#define XPAR_UCOS_SDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID
+#define XPAR_UCOS_SDPS_0_BASEADDR 0xE0100000
+#define XPAR_UCOS_SDPS_0_HIGHADDR 0xE0100FFF
+#define XPAR_UCOS_SDPS_0_SDIO_CLK_FREQ_HZ 50000000
+
+
+/******************************************************************/
+
+///* Definitions for driver UCOS_TTCPS */
+//#define XPAR_UCOS_TTCPS_NUM_INSTANCES 3
+//
+///* Definitions for peripheral PS7_TTC_0 */
+//#define XPAR_PS7_TTC_0_DEVICE_ID 0
+//#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000
+//#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115
+//#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0
+//#define XPAR_PS7_TTC_1_DEVICE_ID 1
+//#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004
+//#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115
+//#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0
+//#define XPAR_PS7_TTC_2_DEVICE_ID 2
+//#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008
+//#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115
+//#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0
+
+
+/******************************************************************/
+
+/* Definitions for driver UCOS_UARTPS */
+#define XPAR_UCOS_UARTPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_UART_1 */
+#define XPAR_PS7_UART_1_DEVICE_ID 0
+#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
+#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
+#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 50000000
+#define XPAR_PS7_UART_1_HAS_MODEM 0
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_UART_1 */
+#define XPAR_UCOS_UARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
+#define XPAR_UCOS_UARTPS_0_BASEADDR 0xE0001000
+#define XPAR_UCOS_UARTPS_0_HIGHADDR 0xE0001FFF
+#define XPAR_UCOS_UARTPS_0_UART_CLK_FREQ_HZ 50000000
+#define XPAR_UCOS_UARTPS_0_HAS_MODEM 0
+
+
+/******************************************************************/
+
+/* Definitions for driver UCOS_USBPS */
+#define XPAR_UCOS_USBPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_USB_0 */
+#define XPAR_PS7_USB_0_DEVICE_ID 0
+#define XPAR_PS7_USB_0_BASEADDR 0xE0002000
+#define XPAR_PS7_USB_0_HIGHADDR 0xE0002FFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_USB_0 */
+#define XPAR_UCOS_USBPS_0_DEVICE_ID XPAR_PS7_USB_0_DEVICE_ID
+#define XPAR_UCOS_USBPS_0_BASEADDR 0xE0002000
+#define XPAR_UCOS_USBPS_0_HIGHADDR 0xE0002FFF
+
+
+/******************************************************************/
+
+/* Definitions for driver XADCPS */
+#define XPAR_XADCPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_XADC_0 */
+#define XPAR_PS7_XADC_0_DEVICE_ID 0
+#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100
+#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_XADC_0 */
+#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
+#define XPAR_XADCPS_0_BASEADDR 0xF8007100
+#define XPAR_XADCPS_0_HIGHADDR 0xF8007120
+
+
+/******************************************************************/
+
+
+//UCOS STDOUT
+#define UCOS_STDOUT_DRIVER UCOS_UART_PS7_UART
+#define UCOS_STDOUT_DEVICE_ID 0
+#define STDOUT_BASEADDRESS
+
+//UCOS Ethernet
+#define UCOS_ETHERNET_DRIVER UCOS_ETHERNET_EMACPS
+
+//UCOS TASK PARAMETERS
+#define UCOS_START_TASK_PRIO 5
+#define UCOS_START_TASK_STACK_SIZE 784
+#define UCOS_START_DEBUG_TRACE DEF_ENABLED
+#define NET_TASK_CFG_RX_PRIO 30
+#define NET_TASK_CFG_RX_STACK_SIZE 3072
+#define NET_TASK_CFG_TXDEALLOC_PRIO 6
+#define NET_TASK_CFG_TXDEALLOC_STACK_SIZE 2048
+#define NET_TASK_CFG_TMR_PRIO 18
+#define NET_TASK_CFG_TMR_STACK_SIZE 2048
+#define HTTPc_OS_CFG_TASK_PRIO 20
+#define HTTPc_OS_CFG_TASK_STK_SIZE 2048
+#define UCOS_HTTPc_OS_CFG_TASK_DELAY 1
+#define UCOS_HTTPc_OS_CFG_MSG_Q_SIZE 5
+#define UCOS_HTTPc_OS_CFG_TIMEOUT 2000
+#define UCOS_HTTPc_OS_CFG_INACTIVITY_TIMEOUT 30
+
+#define UCOS_AMP_MASTER DEF_ENABLED
+
+
+#define UCOS_CFG_INIT_CAN DEF_ENABLED
+#define UCOS_CFG_INIT_NET DEF_ENABLED
+#define UCOS_CFG_INIT_FS DEF_DISABLED
+#define UCOS_CFG_INIT_OPENAMP DEF_DISABLED
+#define UCOS_CFG_INIT_USBD DEF_DISABLED
+#define UCOS_CFG_INIT_USBH DEF_DISABLED
+
+
+#define UCOS_ETHERNET_ADDRESS "10.10.110.2"
+#define UCOS_ETHERNET_GATEWAY "10.10.110.1"
+#define UCOS_ETHERNET_SUBMASK "255.255.255.0"
+#define UCOS_ETHERNET_DHCP DEF_ENABLED
+
+
+#define UCOS_IF_RX_BUF_NBR 12
+#define UCOS_IF_TX_LARGE_BUF_NBR 8
+#define UCOS_IF_TX_SMALL_BUF_NBR 8
+#define UCOS_IF_RX_DESC_NBR 0
+#define UCOS_IF_TX_DESC_NBR 0
+#define UCOS_IF_DEDIC_MEM_ADDR 0
+#define UCOS_IF_DEDIC_MEM_SIZE 0
+#define UCOS_IF_HW_ADDR "50:E5:49:E6:8D:28"
+
+
+#define UCOS_PHY_BUS_ADDR 255
+#define UCOS_PHY_BUS_MODE UCOS_NET_PHY_BUS_MODE_GMII
+#define UCOS_PHY_TYPE UCOS_NET_PHY_TYPE_INT
+#define UCOS_PHY_SPEED UCOS_NET_PHY_SPD_AUTO
+#define UCOS_PHY_DUPLEX UCOS_NET_PHY_DUPLEX_AUTO
+
+
+#define UCOS_USB_DRIVER UCOS_USB_NONE
+#define UCOS_USB_DEVICE_ID 0
+#define UCOS_USB_TYPE UCOS_USB_TYPE_DEVICE
+
+
+#define UCOS_RAMDISK_EN DEF_DISABLED
+#define UCOS_RAMDISK_SIZE 128
+#define UCOS_RAMDISK_SECTOR_SIZE 512
+#define UCOS_RAMDISK_BASE_ADDRESS 0
+
+
+#define UCOS_SDCARD_EN DEF_DISABLED
+
+
+#define XPAR_PS7_ETHERNET_0_INT_SOURCE 54
+#define XPAR_PS7_SD_0_INT_SOURCE 56
+#define XPAR_PS7_UART_1_INT_SOURCE 82
+#define XPAR_PS7_USB_0_INT_SOURCE 53
+
+#define UCOS_ZYNQ_CONFIG_MMU DEF_DISABLED
+#define UCOS_ZYNQ_ENABLE_MMU DEF_DISABLED
+#define UCOS_ZYNQ_CONFIG_CACHES DEF_DISABLED
+#define UCOS_ZYNQ_ENABLE_CACHES DEF_DISABLED
+#define UCOS_ZYNQ_ENABLE_OPTIMS DEF_DISABLED
+#define ZYNQ_ENABLE_EARLY_L1_I_EN DEF_DISABLED
+#define ZYNQ_ENABLE_EARLY_L1_D_EN DEF_DISABLED
+#define UCOS_CPU_TYPE UCOS_CPU_TYPE_PS7
+
+//Parameters added by Kai Gemlau
+#define UCOS_SMP_ENABLE DEF_DISABLED
+
+/******************************************************************/
+
+/* Definitions for driver TTCPS */
+#define XPAR_XTTCPS_NUM_INSTANCES 3U
+
+/* Definitions for peripheral PS7_TTC_0 */
+#define XPAR_PS7_TTC_0_DEVICE_ID 0U
+#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000U
+#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115U
+#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0U
+#define XPAR_PS7_TTC_1_DEVICE_ID 1U
+#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004U
+#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115U
+#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0U
+#define XPAR_PS7_TTC_2_DEVICE_ID 2U
+#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008U
+#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115U
+#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0U
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_TTC_0 */
+#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PS7_TTC_0_DEVICE_ID
+#define XPAR_XTTCPS_0_BASEADDR 0xF8001000U
+#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 111111115U
+#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0U
+
+#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PS7_TTC_1_DEVICE_ID
+#define XPAR_XTTCPS_1_BASEADDR 0xF8001004U
+#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 111111115U
+#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0U
+
+#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PS7_TTC_2_DEVICE_ID
+#define XPAR_XTTCPS_2_BASEADDR 0xF8001008U
+#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 111111115U
+#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0U
+
+
+/******************************************************************/
+/* Definitions for driver GPIOPS */
+#define XPAR_XGPIOPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_GPIO_0 */
+#define XPAR_PS7_GPIO_0_DEVICE_ID 0
+#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
+#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_GPIO_0 */
+#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
+#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
+#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver IICPS */
+#define XPAR_XIICPS_NUM_INSTANCES 2
+
+/* Definitions for peripheral PS7_I2C_0 */
+#define XPAR_PS7_I2C_0_DEVICE_ID 0
+#define XPAR_PS7_I2C_0_BASEADDR 0xE0004000
+#define XPAR_PS7_I2C_0_HIGHADDR 0xE0004FFF
+#define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 111111115
+
+
+/* Definitions for peripheral PS7_I2C_1 */
+#define XPAR_PS7_I2C_1_DEVICE_ID 1
+#define XPAR_PS7_I2C_1_BASEADDR 0xE0005000
+#define XPAR_PS7_I2C_1_HIGHADDR 0xE0005FFF
+#define XPAR_PS7_I2C_1_I2C_CLK_FREQ_HZ 111111115
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_I2C_0 */
+#define XPAR_XIICPS_0_DEVICE_ID XPAR_PS7_I2C_0_DEVICE_ID
+#define XPAR_XIICPS_0_BASEADDR 0xE0004000
+#define XPAR_XIICPS_0_HIGHADDR 0xE0004FFF
+#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 111111115
+
+/* Canonical definitions for peripheral PS7_I2C_1 */
+#define XPAR_XIICPS_1_DEVICE_ID XPAR_PS7_I2C_1_DEVICE_ID
+#define XPAR_XIICPS_1_BASEADDR 0xE0005000
+#define XPAR_XIICPS_1_HIGHADDR 0xE0005FFF
+#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 111111115
+
+
+/******************************************************************/
+
+/* Definitions for driver UARTPS */
+#define XPAR_XUARTPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_UART_1 */
+#define XPAR_PS7_UART_1_DEVICE_ID 2
+#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
+#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
+#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 9600
+#define XPAR_PS7_UART_1_HAS_MODEM 0
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_UART_1 */
+#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
+#define XPAR_XUARTPS_0_BASEADDR 0xE0001000
+#define XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF
+#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 50000000
+#define XPAR_XUARTPS_0_HAS_MODEM 0
+
+
+/******************************************************************/

src/APP/Aufgabe2/ps7/core0/cfg/xparameters_ps.h

@@ -0,0 +1,325 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xparameters_ps.h
+*
+* This file contains the address definitions for the hard peripherals
+* attached to the ARM Cortex A9 core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 02/01/10 Initial version
+* 3.04a sdm     02/02/12 Removed some of the defines as they are being generated through
+*                        driver tcl
+* 5.0	pkp		01/16/15 Added interrupt ID definition of ttc for TEST APP
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XPARAMETERS_PS_H_
+#define _XPARAMETERS_PS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock
+ */
+
+/* Canonical definitions for DDR MEMORY */
+#define XPAR_DDR_MEM_BASEADDR		0x00000000U
+#define XPAR_DDR_MEM_HIGHADDR		0x3FFFFFFFU
+
+/* Canonical definitions for Interrupts  */
+#define XPAR_XUARTPS_0_INTR		XPS_UART0_INT_ID
+#define XPAR_XUARTPS_1_INTR		XPS_UART1_INT_ID
+#define XPAR_XUSBPS_0_INTR		XPS_USB0_INT_ID
+#define XPAR_XUSBPS_1_INTR		XPS_USB1_INT_ID
+#define XPAR_XIICPS_0_INTR		XPS_I2C0_INT_ID
+#define XPAR_XIICPS_1_INTR		XPS_I2C1_INT_ID
+#define XPAR_XSPIPS_0_INTR		XPS_SPI0_INT_ID
+#define XPAR_XSPIPS_1_INTR		XPS_SPI1_INT_ID
+#define XPAR_XCANPS_0_INTR		XPS_CAN0_INT_ID
+#define XPAR_XCANPS_1_INTR		XPS_CAN1_INT_ID
+#define XPAR_XGPIOPS_0_INTR		XPS_GPIO_INT_ID
+#define XPAR_XEMACPS_0_INTR		XPS_GEM0_INT_ID
+#define XPAR_XEMACPS_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
+#define XPAR_XEMACPS_1_INTR		XPS_GEM1_INT_ID
+#define XPAR_XEMACPS_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
+#define XPAR_XSDIOPS_0_INTR		XPS_SDIO0_INT_ID
+#define XPAR_XQSPIPS_0_INTR		XPS_QSPI_INT_ID
+#define XPAR_XSDIOPS_1_INTR		XPS_SDIO1_INT_ID
+#define XPAR_XWDTPS_0_INTR		XPS_WDT_INT_ID
+#define XPAR_XDCFG_0_INTR		XPS_DVC_INT_ID
+#define XPAR_SCUTIMER_INTR		XPS_SCU_TMR_INT_ID
+#define XPAR_SCUWDT_INTR		XPS_SCU_WDT_INT_ID
+#define XPAR_XTTCPS_0_INTR		XPS_TTC0_0_INT_ID
+#define XPAR_XTTCPS_1_INTR		XPS_TTC0_1_INT_ID
+#define XPAR_XTTCPS_2_INTR		XPS_TTC0_2_INT_ID
+#define XPAR_XTTCPS_3_INTR		XPS_TTC1_0_INT_ID
+#define XPAR_XTTCPS_4_INTR		XPS_TTC1_1_INT_ID
+#define XPAR_XTTCPS_5_INTR		XPS_TTC1_2_INT_ID
+#define XPAR_XDMAPS_0_FAULT_INTR	XPS_DMA0_ABORT_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_0	XPS_DMA0_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_1	XPS_DMA1_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_2	XPS_DMA2_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_3	XPS_DMA3_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_4	XPS_DMA4_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_5	XPS_DMA5_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_6	XPS_DMA6_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_7	XPS_DMA7_INT_ID
+
+
+#define XPAR_XQSPIPS_0_LINEAR_BASEADDR	XPS_QSPI_LINEAR_BASEADDR
+#define XPAR_XPARPORTPS_CTRL_BASEADDR	XPS_PARPORT_CRTL_BASEADDR
+
+
+
+/* Canonical definitions for DMAC */
+
+
+/* Canonical definitions for WDT */
+
+/* Canonical definitions for SLCR */
+#define XPAR_XSLCR_NUM_INSTANCES	1U
+#define XPAR_XSLCR_0_DEVICE_ID		0U
+#define XPAR_XSLCR_0_BASEADDR		XPS_SYS_CTRL_BASEADDR
+
+/* Canonical definitions for SCU GIC */
+#define XPAR_SCUGIC_NUM_INSTANCES	1U
+#define XPAR_SCUGIC_SINGLE_DEVICE_ID	0U
+#define XPAR_SCUGIC_CPU_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00000100U)
+#define XPAR_SCUGIC_DIST_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00001000U)
+#define XPAR_SCUGIC_ACK_BEFORE		0U
+
+/* Canonical definitions for Global Timer */
+#define XPAR_GLOBAL_TMR_NUM_INSTANCES	1U
+#define XPAR_GLOBAL_TMR_DEVICE_ID	0U
+#define XPAR_GLOBAL_TMR_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00000200U)
+#define XPAR_GLOBAL_TMR_INTR		XPS_GLOBAL_TMR_INT_ID
+
+
+/* Xilinx Parallel Flash Library (XilFlash) User Settings */
+#define XPAR_AXI_EMC
+
+
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock. These have been put for bacwards compatibilty
+ */
+
+#define XPS_PERIPHERAL_BASEADDR		0xE0000000U
+#define XPS_UART0_BASEADDR		0xE0000000U
+#define XPS_UART1_BASEADDR		0xE0001000U
+#define XPS_USB0_BASEADDR		0xE0002000U
+#define XPS_USB1_BASEADDR		0xE0003000U
+#define XPS_I2C0_BASEADDR		0xE0004000U
+#define XPS_I2C1_BASEADDR		0xE0005000U
+#define XPS_SPI0_BASEADDR		0xE0006000U
+#define XPS_SPI1_BASEADDR		0xE0007000U
+#define XPS_CAN0_BASEADDR		0xE0008000U
+#define XPS_CAN1_BASEADDR		0xE0009000U
+#define XPS_GPIO_BASEADDR		0xE000A000U
+#define XPS_GEM0_BASEADDR		0xE000B000U
+#define XPS_GEM1_BASEADDR		0xE000C000U
+#define XPS_QSPI_BASEADDR		0xE000D000U
+#define XPS_PARPORT_CRTL_BASEADDR	0xE000E000U
+#define XPS_SDIO0_BASEADDR		0xE0100000U
+#define XPS_SDIO1_BASEADDR		0xE0101000U
+#define XPS_IOU_BUS_CFG_BASEADDR	0xE0200000U
+#define XPS_NAND_BASEADDR		0xE1000000U
+#define XPS_PARPORT0_BASEADDR		0xE2000000U
+#define XPS_PARPORT1_BASEADDR		0xE4000000U
+#define XPS_QSPI_LINEAR_BASEADDR	0xFC000000U
+#define XPS_SYS_CTRL_BASEADDR		0xF8000000U	/* AKA SLCR */
+#define XPS_TTC0_BASEADDR		0xF8001000U
+#define XPS_TTC1_BASEADDR		0xF8002000U
+#define XPS_DMAC0_SEC_BASEADDR		0xF8003000U
+#define XPS_DMAC0_NON_SEC_BASEADDR	0xF8004000U
+#define XPS_WDT_BASEADDR		0xF8005000U
+#define XPS_DDR_CTRL_BASEADDR		0xF8006000U
+#define XPS_DEV_CFG_APB_BASEADDR	0xF8007000U
+#define XPS_AFI0_BASEADDR		0xF8008000U
+#define XPS_AFI1_BASEADDR		0xF8009000U
+#define XPS_AFI2_BASEADDR		0xF800A000U
+#define XPS_AFI3_BASEADDR		0xF800B000U
+#define XPS_OCM_BASEADDR		0xF800C000U
+#define XPS_EFUSE_BASEADDR		0xF800D000U
+#define XPS_CORESIGHT_BASEADDR		0xF8800000U
+#define XPS_TOP_BUS_CFG_BASEADDR	0xF8900000U
+#define XPS_SCU_PERIPH_BASE		0xF8F00000U
+#define XPS_L2CC_BASEADDR		0xF8F02000U
+#define XPS_SAM_RAM_BASEADDR		0xFFFC0000U
+#define XPS_FPGA_AXI_S0_BASEADDR	0x40000000U
+#define XPS_FPGA_AXI_S1_BASEADDR	0x80000000U
+#define XPS_IOU_S_SWITCH_BASEADDR	0xE0000000U
+#define XPS_PERIPH_APB_BASEADDR		0xF8000000U
+
+/* Shared Peripheral Interrupts (SPI) */
+#define XPS_CORE_PARITY0_INT_ID		32U
+#define XPS_CORE_PARITY1_INT_ID		33U
+#define XPS_L2CC_INT_ID			34U
+#define XPS_OCMINTR_INT_ID		35U
+#define XPS_ECC_INT_ID			36U
+#define XPS_PMU0_INT_ID			37U
+#define XPS_PMU1_INT_ID			38U
+#define XPS_SYSMON_INT_ID		39U
+#define XPS_DVC_INT_ID			40U
+#define XPS_WDT_INT_ID			41U
+#define XPS_TTC0_0_INT_ID		42U
+#define XPS_TTC0_1_INT_ID		43U
+#define XPS_TTC0_2_INT_ID 		44U
+#define XPS_DMA0_ABORT_INT_ID		45U
+#define XPS_DMA0_INT_ID			46U
+#define XPS_DMA1_INT_ID			47U
+#define XPS_DMA2_INT_ID			48U
+#define XPS_DMA3_INT_ID			49U
+#define XPS_SMC_INT_ID			50U
+#define XPS_QSPI_INT_ID			51U
+#define XPS_GPIO_INT_ID			52U
+#define XPS_USB0_INT_ID			53U
+#define XPS_GEM0_INT_ID			54U
+#define XPS_GEM0_WAKE_INT_ID		55U
+#define XPS_SDIO0_INT_ID		56U
+#define XPS_I2C0_INT_ID			57U
+#define XPS_SPI0_INT_ID			58U
+#define XPS_UART0_INT_ID		59U
+#define XPS_CAN0_INT_ID			60U
+#define XPS_FPGA0_INT_ID		61U
+#define XPS_FPGA1_INT_ID		62U
+#define XPS_FPGA2_INT_ID		63U
+#define XPS_FPGA3_INT_ID		64U
+#define XPS_FPGA4_INT_ID		65U
+#define XPS_FPGA5_INT_ID		66U
+#define XPS_FPGA6_INT_ID		67U
+#define XPS_FPGA7_INT_ID		68U
+#define XPS_TTC1_0_INT_ID		69U
+#define XPS_TTC1_1_INT_ID		70U
+#define XPS_TTC1_2_INT_ID		71U
+#define XPS_DMA4_INT_ID			72U
+#define XPS_DMA5_INT_ID			73U
+#define XPS_DMA6_INT_ID			74U
+#define XPS_DMA7_INT_ID			75U
+#define XPS_USB1_INT_ID			76U
+#define XPS_GEM1_INT_ID			77U
+#define XPS_GEM1_WAKE_INT_ID		78U
+#define XPS_SDIO1_INT_ID		79U
+#define XPS_I2C1_INT_ID			80U
+#define XPS_SPI1_INT_ID			81U
+#define XPS_UART1_INT_ID		82U
+#define XPS_CAN1_INT_ID			83U
+#define XPS_FPGA8_INT_ID		84U
+#define XPS_FPGA9_INT_ID		85U
+#define XPS_FPGA10_INT_ID		86U
+#define XPS_FPGA11_INT_ID		87U
+#define XPS_FPGA12_INT_ID		88U
+#define XPS_FPGA13_INT_ID		89U
+#define XPS_FPGA14_INT_ID		90U
+#define XPS_FPGA15_INT_ID		91U
+
+/* Private Peripheral Interrupts (PPI) */
+#define XPS_GLOBAL_TMR_INT_ID		27U	/* SCU Global Timer interrupt */
+#define XPS_FIQ_INT_ID			28U	/* FIQ from FPGA fabric */
+#define XPS_SCU_TMR_INT_ID		29U	/* SCU Private Timer interrupt */
+#define XPS_SCU_WDT_INT_ID		30U	/* SCU Private WDT interrupt */
+#define XPS_IRQ_INT_ID			31U	/* IRQ from FPGA fabric */
+
+
+/* REDEFINES for TEST APP */
+/* Definitions for UART */
+#define XPAR_PS7_UART_0_INTR		XPS_UART0_INT_ID
+#define XPAR_PS7_UART_1_INTR		XPS_UART1_INT_ID
+#define XPAR_PS7_USB_0_INTR		XPS_USB0_INT_ID
+#define XPAR_PS7_USB_1_INTR		XPS_USB1_INT_ID
+#define XPAR_PS7_I2C_0_INTR		XPS_I2C0_INT_ID
+#define XPAR_PS7_I2C_1_INTR		XPS_I2C1_INT_ID
+#define XPAR_PS7_SPI_0_INTR		XPS_SPI0_INT_ID
+#define XPAR_PS7_SPI_1_INTR		XPS_SPI1_INT_ID
+#define XPAR_PS7_CAN_0_INTR		XPS_CAN0_INT_ID
+#define XPAR_PS7_CAN_1_INTR		XPS_CAN1_INT_ID
+#define XPAR_PS7_GPIO_0_INTR		XPS_GPIO_INT_ID
+#define XPAR_PS7_ETHERNET_0_INTR	XPS_GEM0_INT_ID
+#define XPAR_PS7_ETHERNET_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_1_INTR	XPS_GEM1_INT_ID
+#define XPAR_PS7_ETHERNET_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
+#define XPAR_PS7_QSPI_0_INTR		XPS_QSPI_INT_ID
+#define XPAR_PS7_WDT_0_INTR		XPS_WDT_INT_ID
+#define XPAR_PS7_SCUWDT_0_INTR		XPS_SCU_WDT_INT_ID
+#define XPAR_PS7_SCUTIMER_0_INTR	XPS_SCU_TMR_INT_ID
+#define XPAR_PS7_XADC_0_INTR		XPS_SYSMON_INT_ID
+#define XPAR_PS7_TTC_0_INTR         XPS_TTC0_0_INT_ID
+#define XPAR_PS7_TTC_1_INTR         XPS_TTC0_1_INT_ID
+#define XPAR_PS7_TTC_2_INTR         XPS_TTC0_2_INT_ID
+#define XPAR_PS7_TTC_3_INTR         XPS_TTC1_0_INT_ID
+#define XPAR_PS7_TTC_4_INTR         XPS_TTC1_1_INT_ID
+#define XPAR_PS7_TTC_5_INTR         XPS_TTC1_2_INT_ID
+
+#define XPAR_XADCPS_INT_ID		XPS_SYSMON_INT_ID
+
+/* For backwards compatibilty */
+#define XPAR_XUARTPS_0_CLOCK_HZ		XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
+#define XPAR_XUARTPS_1_CLOCK_HZ		XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
+#define XPAR_XTTCPS_0_CLOCK_HZ		XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_1_CLOCK_HZ		XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_2_CLOCK_HZ		XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_3_CLOCK_HZ		XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_4_CLOCK_HZ		XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_5_CLOCK_HZ		XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
+#define XPAR_XIICPS_0_CLOCK_HZ		XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
+#define XPAR_XIICPS_1_CLOCK_HZ		XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
+
+#define XPAR_XQSPIPS_0_CLOCK_HZ		XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
+
+#define XPAR_SCUTIMER_DEVICE_ID		0U
+#define XPAR_SCUWDT_DEVICE_ID		0U
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */

src/APP/Aufgabe2/ps7/core0/linker/lscript.ld

@@ -0,0 +1,291 @@
+/*******************************************************************/
+/*                                                                 */
+/* This file is automatically generated by linker script generator.*/
+/*                                                                 */
+/* Version:                                 */
+/*                                                                 */
+/* Copyright (c) 2010-2016 Xilinx, Inc.  All rights reserved.      */
+/*                                                                 */
+/* Description : Cortex-A9 Linker Script                          */
+/*                                                                 */
+/*******************************************************************/
+
+_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
+_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
+
+_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
+_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
+_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
+_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
+_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
+
+/* Define Memories in the system */
+
+MEMORY
+{
+   axi_bram_ctrl_0_Mem0 : ORIGIN = 0x40000000, LENGTH = 0x2000
+   ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x3FF00000
+   ps7_qspi_linear_0 : ORIGIN = 0xFC000000, LENGTH = 0x2000000
+   ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000
+   ps7_ram_1 : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00
+   ps7_ddr_core_0 : ORIGIN = 0x100000, LENGTH = 0x700000
+   ps7_ddr_core_1 : ORIGIN = 0x800000, LENGTH = 0x800000
+}
+
+/* Specify the default entry point to the program */
+
+ENTRY(_vector_table)
+
+/* Define the sections, and where they are mapped in memory */
+
+SECTIONS
+{
+.text : {
+   KEEP (*(.vectors))
+   *(.boot)
+   *(.text)
+   *(.text.*)
+   *(.gnu.linkonce.t.*)
+   *(.plt)
+   *(.gnu_warning)
+   *(.gcc_execpt_table)
+   *(.glue_7)
+   *(.glue_7t)
+   *(.vfp11_veneer)
+   *(.ARM.extab)
+   *(.gnu.linkonce.armextab.*)
+} > ps7_ddr_core_0
+
+.init : {
+   KEEP (*(.init))
+} > ps7_ddr_core_0
+
+.fini : {
+   KEEP (*(.fini))
+} > ps7_ddr_core_0
+
+.rodata : {
+   __rodata_start = .;
+   *(.rodata)
+   *(.rodata.*)
+   *(.gnu.linkonce.r.*)
+   __rodata_end = .;
+} > ps7_ddr_core_0
+
+.rodata1 : {
+   __rodata1_start = .;
+   *(.rodata1)
+   *(.rodata1.*)
+   __rodata1_end = .;
+} > ps7_ddr_core_0
+
+.sdata2 : {
+   __sdata2_start = .;
+   *(.sdata2)
+   *(.sdata2.*)
+   *(.gnu.linkonce.s2.*)
+   __sdata2_end = .;
+} > ps7_ddr_core_0
+
+.sbss2 : {
+   __sbss2_start = .;
+   *(.sbss2)
+   *(.sbss2.*)
+   *(.gnu.linkonce.sb2.*)
+   __sbss2_end = .;
+} > ps7_ddr_core_0
+
+.data : {
+   __data_start = .;
+   *(.data)
+   *(.data.*)
+   *(.gnu.linkonce.d.*)
+   *(.jcr)
+   *(.got)
+   *(.got.plt)
+   __data_end = .;
+} > ps7_ddr_core_0
+
+.data1 : {
+   __data1_start = .;
+   *(.data1)
+   *(.data1.*)
+   __data1_end = .;
+} > ps7_ddr_core_0
+
+.got : {
+   *(.got)
+} > ps7_ddr_core_0
+
+.ctors : {
+   __CTOR_LIST__ = .;
+   ___CTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.ctors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
+   KEEP (*(SORT(.ctors.*)))
+   KEEP (*(.ctors))
+   __CTOR_END__ = .;
+   ___CTORS_END___ = .;
+} > ps7_ddr_core_0
+
+.dtors : {
+   __DTOR_LIST__ = .;
+   ___DTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.dtors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
+   KEEP (*(SORT(.dtors.*)))
+   KEEP (*(.dtors))
+   __DTOR_END__ = .;
+   ___DTORS_END___ = .;
+} > ps7_ddr_core_0
+
+.fixup : {
+   __fixup_start = .;
+   *(.fixup)
+   __fixup_end = .;
+} > ps7_ddr_core_0
+
+.eh_frame : {
+   *(.eh_frame)
+} > ps7_ddr_core_0
+
+.eh_framehdr : {
+   __eh_framehdr_start = .;
+   *(.eh_framehdr)
+   __eh_framehdr_end = .;
+} > ps7_ddr_core_0
+
+.gcc_except_table : {
+   *(.gcc_except_table)
+} > ps7_ddr_core_0
+
+.mmu_tbl (ALIGN(16384)) : {
+   __mmu_tbl_start = .;
+   *(.mmu_tbl)
+   __mmu_tbl_end = .;
+} > ps7_ddr_core_0
+
+.ARM.exidx : {
+   __exidx_start = .;
+   *(.ARM.exidx*)
+   *(.gnu.linkonce.armexidix.*.*)
+   __exidx_end = .;
+} > ps7_ddr_core_0
+
+.preinit_array : {
+   __preinit_array_start = .;
+   KEEP (*(SORT(.preinit_array.*)))
+   KEEP (*(.preinit_array))
+   __preinit_array_end = .;
+} > ps7_ddr_core_0
+
+.init_array : {
+   __init_array_start = .;
+   KEEP (*(SORT(.init_array.*)))
+   KEEP (*(.init_array))
+   __init_array_end = .;
+} > ps7_ddr_core_0
+
+.fini_array : {
+   __fini_array_start = .;
+   KEEP (*(SORT(.fini_array.*)))
+   KEEP (*(.fini_array))
+   __fini_array_end = .;
+} > ps7_ddr_core_0
+
+.ARM.attributes : {
+   __ARM.attributes_start = .;
+   *(.ARM.attributes)
+   __ARM.attributes_end = .;
+} > ps7_ddr_core_0
+
+.sdata : {
+   __sdata_start = .;
+   *(.sdata)
+   *(.sdata.*)
+   *(.gnu.linkonce.s.*)
+   __sdata_end = .;
+} > ps7_ddr_core_0
+
+.sbss (NOLOAD) : {
+   __sbss_start = .;
+   *(.sbss)
+   *(.sbss.*)
+   *(.gnu.linkonce.sb.*)
+   __sbss_end = .;
+} > ps7_ddr_core_0
+
+.tdata : {
+   __tdata_start = .;
+   *(.tdata)
+   *(.tdata.*)
+   *(.gnu.linkonce.td.*)
+   __tdata_end = .;
+} > ps7_ddr_core_0
+
+.tbss : {
+   __tbss_start = .;
+   *(.tbss)
+   *(.tbss.*)
+   *(.gnu.linkonce.tb.*)
+   __tbss_end = .;
+} > ps7_ddr_core_0
+
+.bss (NOLOAD) : {
+   __bss_start = .;
+   *(.bss)
+   *(.bss.*)
+   *(.gnu.linkonce.b.*)
+   *(COMMON)
+   __bss_end = .;
+} > ps7_ddr_core_0
+
+_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
+
+_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
+
+/* Generate Stack and Heap definitions */
+
+.heap (NOLOAD) : {
+   . = ALIGN(16);
+   _heap = .;
+   HeapBase = .;
+   _heap_start = .;
+   . += _HEAP_SIZE;
+   _heap_end = .;
+   HeapLimit = .;
+} > ps7_ddr_core_0
+
+.stack (NOLOAD) : {
+   . = ALIGN(16);
+   _stack_end = .;
+   . += _STACK_SIZE;
+   . = ALIGN(16);
+   _stack = .;
+   __stack = _stack;
+   . = ALIGN(16);
+   _irq_stack_end = .;
+   . += _IRQ_STACK_SIZE;
+   . = ALIGN(16);
+   __irq_stack = .;
+   _supervisor_stack_end = .;
+   . += _SUPERVISOR_STACK_SIZE;
+   . = ALIGN(16);
+   __supervisor_stack = .;
+   _abort_stack_end = .;
+   . += _ABORT_STACK_SIZE;
+   . = ALIGN(16);
+   __abort_stack = .;
+   _fiq_stack_end = .;
+   . += _FIQ_STACK_SIZE;
+   . = ALIGN(16);
+   __fiq_stack = .;
+   _undef_stack_end = .;
+   . += _UNDEF_STACK_SIZE;
+   . = ALIGN(16);
+   __undef_stack = .;
+} > ps7_ddr_core_0
+
+_end = .;
+}
+

src/APP/Aufgabe2/ps7/core0/main.c

@@ -0,0 +1,83 @@
+/*
+ ============================================================================
+ Name        : main.c
+ Author      : Laurenz Borchers
+ Version     :
+ Copyright   : Copyright belongs to the authors
+ Description : Hello World in C, Praktikum Aufgabe 2
+ ============================================================================
+ */
+
+#include <mmu.h>
+#include <stdio.h>
+#include "ucos_uartps.h"
+#include "ucos_ii.h"
+#include "ucos_bsp.h"
+#include "xil_testmem.h"
+#include "xil_printf.h"
+
+#define HELLO_WORLD_TASK_PRIO 64
+#define CALC_TASK_PRIO 64
+
+#define HELLO_WORLD_TASK_STK_SIZE 16
+#define CALC_TASK_STK_SIZE 32
+
+static  OS_STK       HelloWorldTaskStk[HELLO_WORLD_TASK_STK_SIZE];
+static  OS_STK       CalcTaskStk[HELLO_WORLD_TASK_STK_SIZE];
+
+
+int f(int n)
+{
+  if (n == 1)
+    return n;
+  else
+    return (f(n-1) + f(n-3));
+}
+
+void HelloWorldTask (void *pdata)
+{
+	while(1){
+		UCOS_Printf("Hello World!");
+		OSTimeDly(OS_TICKS_PER_SEC*50);
+	}
+}
+
+void CalcTask (void *pdata)
+{
+	uint8_t n=50;
+	for (uint8_t i = 1; i <= n; i)
+	 {
+	  UCOS_Printf("%u", f(i));
+	 }
+}
+
+void InitDoneCallback(void * p_arg){
+	(void) p_arg;
+	UCOS_Print("OS started!\r\n");
+	
+	OSTaskCreateExt(HelloWorldTask,
+					0,
+					&HelloWorldTaskStk[0],
+					HELLO_WORLD_TASK_PRIO,
+					&HelloWorldTaskStk[0],
+					0,
+					0);
+
+	OSTaskCreateExt(CalcTask,
+					0,
+					CALC_TASK_PRIO,
+					CALC_TASK_PRIO,
+					&CalcTaskStk[0],
+					CALC_TASK_STK_SIZE,
+					0
+					);
+
+	while(1){
+		OSTimeDly();
+	}
+}
+
+int main(void) {
+	MMUInit();
+	while (1);;
+}

src/APP/Aufgabe2/ps7/core0/src/app_hooks.c

@@ -0,0 +1,259 @@
+/*
+*********************************************************************************************************
+*                                            EXAMPLE CODE
+*
+*               This file is provided as an example on how to use Micrium products.
+*
+*               Please feel free to use any application code labeled as 'EXAMPLE CODE' in
+*               your application products.  Example code may be used as is, in whole or in
+*               part, or may be used as a reference only. This file can be modified as
+*               required to meet the end-product requirements.
+*
+*               Please help us continue to provide the Embedded community with the finest
+*               software available.  Your honesty is greatly appreciated.
+*
+*               You can find our product's user manual, API reference, release notes and
+*               more information at https://doc.micrium.com.
+*               You can contact us at www.micrium.com.
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                             uC/OS-II
+*                                         Application Hooks
+*
+* Filename      : app_hooks.c
+* Version       : V1.00
+* Programmer(s) : FT
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                                             INCLUDE FILES
+*********************************************************************************************************
+*/
+
+#include  <ucos_ii.h>
+
+
+/*
+*********************************************************************************************************
+*                                       EXTERN  GLOBAL VARIABLES
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                           LOCAL CONSTANTS
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                          LOCAL DATA TYPES
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                                            LOCAL TABLES
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                       LOCAL GLOBAL VARIABLES
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                      LOCAL FUNCTION PROTOTYPES
+*********************************************************************************************************
+*/
+
+
+
+/*
+**********************************************************************************************************
+**********************************************************************************************************
+**                                        GLOBAL FUNCTIONS
+**********************************************************************************************************
+**********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+**                                         uC/OS-II APP HOOKS
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#if (OS_APP_HOOKS_EN > 0)
+
+/*
+*********************************************************************************************************
+*                                      TASK CREATION HOOK (APPLICATION)
+*
+* Description : This function is called when a task is created.
+*
+* Argument(s) : ptcb   is a pointer to the task control block of the task being created.
+*
+* Note(s)     : (1) Interrupts are disabled during this call.
+*********************************************************************************************************
+*/
+
+void  App_TaskCreateHook (OS_TCB *ptcb)
+{
+#if (APP_CFG_PROBE_OS_PLUGIN_EN == DEF_ENABLED) && (OS_PROBE_HOOKS_EN > 0)
+    OSProbe_TaskCreateHook(ptcb);
+#endif
+}
+
+/*
+*********************************************************************************************************
+*                                    TASK DELETION HOOK (APPLICATION)
+*
+* Description : This function is called when a task is deleted.
+*
+* Argument(s) : ptcb   is a pointer to the task control block of the task being deleted.
+*
+* Note(s)     : (1) Interrupts are disabled during this call.
+*********************************************************************************************************
+*/
+
+void  App_TaskDelHook (OS_TCB *ptcb)
+{
+    (void)ptcb;
+}
+
+/*
+*********************************************************************************************************
+*                                      IDLE TASK HOOK (APPLICATION)
+*
+* Description : This function is called by OSTaskIdleHook(), which is called by the idle task.  This hook
+*               has been added to allow you to do such things as STOP the CPU to conserve power.
+*
+* Argument(s) : none.
+*
+* Note(s)     : (1) Interrupts are enabled during this call.
+*********************************************************************************************************
+*/
+
+#if OS_VERSION >= 251
+void  App_TaskIdleHook (void)
+{
+}
+#endif
+
+/*
+*********************************************************************************************************
+*                                        STATISTIC TASK HOOK (APPLICATION)
+*
+* Description : This function is called by OSTaskStatHook(), which is called every second by uC/OS-II's
+*               statistics task.  This allows your application to add functionality to the statistics task.
+*
+* Argument(s) : none.
+*********************************************************************************************************
+*/
+
+void  App_TaskStatHook (void)
+{
+}
+
+/*
+*********************************************************************************************************
+*                                            TASK RETURN HOOK (APPLICATION)
+*
+* Description: This function is called if a task accidentally returns.  In other words, a task should
+*              either be an infinite loop or delete itself when done.
+*
+* Arguments  : ptcb      is a pointer to the task control block of the task that is returning.
+*
+* Note(s)    : none
+*********************************************************************************************************
+*/
+
+
+#if OS_VERSION >= 289
+void  App_TaskReturnHook (OS_TCB  *ptcb)
+{
+    (void)ptcb;
+}
+#endif
+
+/*
+*********************************************************************************************************
+*                                        TASK SWITCH HOOK (APPLICATION)
+*
+* Description : This function is called when a task switch is performed.  This allows you to perform other
+*               operations during a context switch.
+*
+* Argument(s) : none.
+*
+* Note(s)     : (1) Interrupts are disabled during this call.
+*
+*               (2) It is assumed that the global pointer 'OSTCBHighRdy' points to the TCB of the task that
+*                   will be 'switched in' (i.e. the highest priority task) and, 'OSTCBCur' points to the
+*                  task being switched out (i.e. the preempted task).
+*********************************************************************************************************
+*/
+
+#if OS_TASK_SW_HOOK_EN > 0
+void  App_TaskSwHook (void)
+{
+#if (APP_CFG_PROBE_OS_PLUGIN_EN > 0) && (OS_PROBE_HOOKS_EN > 0)
+    OSProbe_TaskSwHook();
+#endif
+}
+#endif
+
+/*
+*********************************************************************************************************
+*                                     OS_TCBInit() HOOK (APPLICATION)
+*
+* Description : This function is called by OSTCBInitHook(), which is called by OS_TCBInit() after setting
+*               up most of the TCB.
+*
+* Argument(s) : ptcb    is a pointer to the TCB of the task being created.
+*
+* Note(s)     : (1) Interrupts may or may not be ENABLED during this call.
+*********************************************************************************************************
+*/
+
+#if OS_VERSION >= 204
+void  App_TCBInitHook (OS_TCB *ptcb)
+{
+    (void)ptcb;
+}
+#endif
+
+/*
+*********************************************************************************************************
+*                                        TICK HOOK (APPLICATION)
+*
+* Description : This function is called every tick.
+*
+* Argument(s) : none.
+*
+* Note(s)     : (1) Interrupts may or may not be ENABLED during this call.
+*********************************************************************************************************
+*/
+
+#if OS_TIME_TICK_HOOK_EN > 0
+void  App_TimeTickHook (void)
+{
+#if (APP_CFG_PROBE_OS_PLUGIN_EN == DEF_ENABLED) && (OS_PROBE_HOOKS_EN > 0)
+    OSProbe_TickHook();
+#endif
+}
+#endif
+#endif

src/APP/Aufgabe2/ps7/core0/src/uartps_cfg.c

@@ -0,0 +1,17 @@
+
+#include "ucos_uartps.h"
+#include "xparameters.h"
+#include "xparameters_ps.h"
+
+/*
+ * The uart configuration table for devices
+ */
+UCOS_UARTPS_Config UCOS_UARTPS_ConfigTable[] = {
+		{
+			XPAR_PS7_UART_1_DEVICE_ID,
+			XPAR_PS7_UART_1_BASEADDR,
+			XPAR_PS7_UART_1_UART_CLK_FREQ_HZ,
+			XPAR_PS7_UART_1_HAS_MODEM,
+			XPAR_PS7_UART_1_INT_SOURCE
+		}
+};

src/APP/Aufgabe3/ps7/core0/build/config.mk

@@ -0,0 +1,11 @@
+#µController dependent flags
+MCFLAGS =-mcpu=cortex-a9 -march=armv7-a -mthumb -mthumb-interwork -mfloat-abi=softfp -mfpu=neon
+
+#Optimization
+OPTIMIZE=-O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections
+
+#Debug Level
+DEBUG   =-g3
+
+#Linker flags
+LDFLAGS  = -nostartfiles -Xlinker --gc-sections -lm

src/APP/Aufgabe3/ps7/core0/build/includes.mk

@@ -0,0 +1,48 @@
+
+INC += -I"$(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/cfg/"
+
+INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Ports/ARM-Cortex-A/Generic/GNU/"
+INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/ARM-Cortex-A/GNU/"
+INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/"
+INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-Common" 
+INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II" 
+INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Source" 
+INC += -I"$(SRC_DIR)/ucos_v1_42/micrium_source/uC-LIB" 
+
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/bsp/src/ipi"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/bsp/src/"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/bsp/src/$(ARCH)/"
+
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_cpu_cortexa9/src"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_scugic/src"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_l2cachec/src"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_uartps/src"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_emacps/src"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_scuc/src"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_ttcps/src"
+
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/cortexa9"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/cortexa9/gcc"
+INC += -I"$(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/common"
+
+INC += -I"$(SRC_DIR)/Xilinx/libsrc/ipipsu_v2_3/src/" 
+INC += -I"$(SRC_DIR)/Modules/MMU" 
+
+
+INC += -I"$(SRC_DIR)/Xilinx/libsrc/ipipsu_v2_3/src/" 
+
+#scugic.h fix
+INC += -I"$(SRC_DIR)/Xilinx/libsrc/scugic_v3_9/src/"
+
+#uart includes
+INC += -I"$(SRC_DIR)/Xilinx/libsrc/uartps_v3_6/src/"
+
+#xttcps includes
+INC += -I"$(SRC_DIR)/Xilinx/libsrc/ttcps_v3_5/src/"
+
+ 
+#gpio includes
+INC += -I"$(SRC_DIR)/Xilinx/libsrc/gpiops_v3_3/src/"
+
+
+

src/APP/Aufgabe3/ps7/core0/build/sources.mk

@@ -0,0 +1,66 @@
+#Startup file
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/bsp/src/$(ARCH)/asm_vectors.S
+-include $(SRC_DIR)/ucos_v1_42/ucos/bsp/src/$(ARCH)/subdir.mk
+-include $(SRC_DIR)/ucos_v1_42/ucos/bsp/src/subdir.mk
+
+-include $(SRC_DIR)/ucos_v1_42/micrium_source/uC-LIB/subdir.mk
+
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/components/ucos_osii/src/bsp/$(ARCH)/ucos_osii_bsp.c
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/components/ucos_common/src/$(ARCH)/cpu_bsp.c
+
+
+
+SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/main.c
+SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/app_hooks.c
+SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/uartps_cfg.c
+SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/ttc_timer.c
+SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/xttcps_g.c
+SRC += $(SRC_DIR)/APP/$(APP)/$(ARCH)/core$(CORE)/src/xgpiops_g.c
+
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Ports/ARM-Cortex-A/Generic/GNU/os_cpu_a_vfp-none.S
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Ports/ARM-Cortex-A/Generic/GNU/os_cpu_c.c
+
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/Cache/ARM/armv7_generic_l1/GNU/cpu_cache_armv7_generic_l1_a.S
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/Cache/ARM/armv7_generic_l1/cpu_cache_armv7_generic_l1.c
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/ARM-Cortex-A/GNU/cpu_a.S
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-CPU/cpu_core.c
+#SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-LIB/lib_ascii.c
+#SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-LIB/lib_math.c
+
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_uartps/src/ucos_uartps.c
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_scutimer/src/ucos_scutimer.c
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_scugic/src/ucos_scugic.c
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_scuc/src/ucos_scuc.c
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_l2cachec/src/ucos_l2cachec.c
+SRC += $(SRC_DIR)/ucos_v1_42/ucos/drivers/ucos_emacps/src/ucos_emacps.c
+
+-include $(SRC_DIR)/ucos_v1_42/ucos/components/ucos_standalone/src/cortexa9/subdir.mk
+
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-Common/KAL/uCOS-II/kal.c
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-Common/Collections/slist.c
+SRC += $(SRC_DIR)/ucos_v1_42/micrium_source/uC-Common/Auth/auth.c
+
+-include $(SRC_DIR)/ucos_v1_42/micrium_source/uCOS-II/Source/subdir.mk
+
+#mmu
+SRC += $(SRC_DIR)/Modules/MMU/mmu.c
+
+
+#src for triple timer counter
+SRC +=$(SRC_DIR)/Xilinx/libsrc/ttcps_v3_5/src/xttcps.c
+#SRC +=$(SRC_DIR)/Xilinx/libsrc/ttcps_v3_5/src/xttcps_g.c
+SRC +=$(SRC_DIR)/Xilinx/libsrc/ttcps_v3_5/src/xttcps_options.c
+SRC +=$(SRC_DIR)/Xilinx/libsrc/ttcps_v3_5/src/xttcps_selftest.c
+SRC +=$(SRC_DIR)/Xilinx/libsrc/ttcps_v3_5/src/xttcps_sinit.c
+
+#src for GPIO
+SRC +=$(SRC_DIR)/Xilinx/libsrc/gpiops_v3_3/src/xgpiops.c
+#SRC +=$(SRC_DIR)/Xilinx/libsrc/gpiops_v3_3/src/xgpiops_g.c
+SRC +=$(SRC_DIR)/Xilinx/libsrc/gpiops_v3_3/src/xgpiops_hw.c
+SRC +=$(SRC_DIR)/Xilinx/libsrc/gpiops_v3_3/src/xgpiops_intr.c
+SRC +=$(SRC_DIR)/Xilinx/libsrc/gpiops_v3_3/src/xgpiops_selftest.c
+SRC +=$(SRC_DIR)/Xilinx/libsrc/gpiops_v3_3/src/xgpiops_sinit.c
+
+
+
+

src/APP/Aufgabe3/ps7/core0/cfg/app_cfg.h

@@ -0,0 +1,82 @@
+/*
+*********************************************************************************************************
+*
+*                                    MICRIUM BOARD SUPPORT PACKAGE
+*
+*                        (c) Copyright 2014-2015; Micrium, Inc.; Weston, FL
+*
+*               All rights reserved.  Protected by international copyright laws.
+*
+*               This BSP is provided in source form to registered licensees ONLY.  It is
+*               illegal to distribute this source code to any third party unless you receive
+*               written permission by an authorized Micrium representative.  Knowledge of
+*               the source code may NOT be used to develop a similar product.
+*
+*               Please help us continue to provide the Embedded community with the finest
+*               software available.  Your honesty is greatly appreciated.
+*
+*               You can contact us at www.micrium.com.
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                    MICRIUM BOARD SUPPORT PACKAGE
+*
+* Filename      : app_cfg.h
+* Version       : V1.42
+* Programmer(s) : JBL
+*********************************************************************************************************
+*/
+
+#ifndef  UCOS_APP_CFG_PRESENT
+#define  UCOS_APP_CFG_PRESENT
+
+#include  <lib_def.h>
+
+#include "../../../../Aufgabe3/ps7/core0/cfg/xparameters.h"
+
+#define  APP_CPU_ENABLED DEF_ENABLED
+
+#define  APP_LIB_ENABLED DEF_ENABLED
+
+#define  APP_COMMON_ENABLED DEF_ENABLED
+
+#define  APP_SHELL_ENABLED DEF_DISABLED
+
+#define  APP_CLK_ENABLED DEF_DISABLED
+
+#define  APP_OSIII_ENABLED DEF_DISABLED
+
+#define  APP_OSII_ENABLED  DEF_ENABLED
+
+#define  APP_TCPIP_ENABLED  DEF_DISABLED
+
+#define  APP_TCPIP_EXP_ENABLED  DEF_DISABLED
+
+#define  APP_DHCPC_ENABLED  DEF_DISABLED
+
+#define  APP_DNSC_ENABLED  DEF_DISABLED
+
+#define  APP_HTTPC_ENABLED  DEF_DISABLED
+
+#define  APP_MQTTC_ENABLED  DEF_DISABLED
+
+#define  APP_TELNETS_ENABLED  DEF_DISABLED
+
+#define  APP_IPERF_ENABLED  DEF_DISABLED
+
+#define  APP_FS_ENABLED  DEF_DISABLED
+
+#define  APP_USBD_ENABLED  DEF_DISABLED
+
+#define  APP_USBH_ENABLED  DEF_DISABLED
+
+#define  APP_OPENAMP_ENABLED  DEF_DISABLED
+
+#define OS_TASK_TMR_PRIO 3
+
+
+#endif /* #ifndef  UCOS_APP_CFG_PRESENT */
+

src/APP/Aufgabe3/ps7/core0/cfg/can_cfg.h

@@ -0,0 +1,202 @@
+/*
+*********************************************************************************************************
+*                                               uC/CAN
+*                                       The Embedded CAN suite
+*
+*                          (c) Copyright 2003-2014; Micrium, Inc.; Weston, FL
+*
+*               All rights reserved.  Protected by international copyright laws.
+*
+*               uC/CAN is provided in source form to registered licensees ONLY.  It is
+*               illegal to distribute this source code to any third party unless you receive
+*               written permission by an authorized Micrium representative.  Knowledge of
+*               the source code may NOT be used to develop a similar product.
+*
+*               Please help us continue to provide the Embedded community with the finest
+*               software available.  Your honesty is greatly appreciated.
+*
+*               You can contact us at www.micrium.com.
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                                        uC/CAN CONFIGURATION
+*
+*                                         ZYNQ ZC7000 Series
+*                                             CAN DRIVER
+* Filename      : can_cfg.h
+* Version       : V2.41.00
+* Programmer(s) : E0
+*                 DC
+*********************************************************************************************************
+*/
+
+#ifndef _CAN_CFG_H_
+#define _CAN_CFG_H_
+
+#include  "lib_def.h"
+
+
+/*
+*********************************************************************************************************
+*                                    COMMON DEFINES & ENUMERATIONS
+*********************************************************************************************************
+*/
+
+                                                                /* Definiton for CANSIG_GRANULARITY, Options:           */
+#define  CAN_CFG_BIT                            0u              /*      BIT                                             */
+#define  CAN_CFG_BYTE                           1u              /*      BYTE                                            */
+
+#ifndef  CAN_FALSE
+#define  CAN_FALSE                              0u
+#endif
+
+#ifndef  CAN_TRUE
+#define  CAN_TRUE                               1u
+#endif
+
+#ifndef  NULL_PTR
+#define  NULL_PTR                              (void *)0
+#endif
+      
+                                                                /* ------------ APPLICATION ENUMERATIONS -------------- */
+enum {
+   S_NODESTATUS = 0, 
+   S_CPULOAD, 
+   S_COUNTER, 
+   S_MAX,
+};
+
+enum {
+   M_STATUS = 0, 
+   M_COMMAND, 
+   M_MAX
+};
+
+
+/*
+*********************************************************************************************************
+*                                      MULTIPLE CAN CONTROLLERS
+*********************************************************************************************************
+*/
+
+#define  CAN_MODULE_CHANNEL_0                   DEF_ENABLED
+#define  CAN_MODULE_CHANNEL_1                   DEF_DISABLED
+
+
+/*
+*********************************************************************************************************
+*                                       DRIVER SPECIFIC DEFINES
+*********************************************************************************************************
+*/
+                                                                /* ---------------- BAUDRATE SETTINGS ----------------- */
+#define  CAN_DEFAULT_BAUDRATE             1000000u              /* Default Baudrate                                     */
+#define  CAN_DEFAULT_SP                       750u              /* Default Bit Sample Point in 1/10 %                   */
+#define  CAN_DEFAULT_RJW                      125u              /* Default Re-Synch Jump Width in 1/10 %                */
+
+                                                                /* ---------------- TIMEOUT SETTINGS ------------------ */
+#define  CAN_TIMEOUT_ERR_VAL               100000uL             /* Timeout Value for While Loop Error Checks            */
+
+
+/* ==================================  ADVANCED DRIVER CONFIGURATION: DEFAULT VALUES ================================== */
+/*  By Default, the following Driver specific settings for the ZYNQ ZC7xxx Driver are set to their default values       */
+/*  unless they are modified by customer needs.                                                                         */
+/*                                                                                                                      */
+/*  By Default, the Watermark level is configured to Maximum Watermark Value in the Driver, based on the reset value    */
+/*  presented by the Reference Manual. Redefine the following define to modify the Watermark Level for the following.   */
+/*      Tx FIFO Empty & Rx FIFO Full Watermark Level(s):                                                                */
+/*          NOTE : The VALID range is between 1 & 63.                                                                   */
+/*                                                                                                                      */
+/*          #define  CAN_WATERMARK_Rx_Tx_SIZE              63u                                                          */
+/*                                                                                                                      */
+/*  By Default, the Operating Mode of the CAN controller is configured to "NORMAL" Mode. For diagnostic checking,       */
+/*  additional operating modes have been included in the driver. Redefine the following define to modify the Operating  */
+/*  Mode to either "LOOP BACK" or "SNOOP" Mode(s).                                                                      */
+/*      NOTE that only one operating mode can be selected at once at Initialization. Once CAN has been Initialized it   */
+/*           is possible to change between Operating Modes at run-time using the xxx_CAN_IoCtl() API Function call.     */
+/*                                                                                                                      */
+/*          #define  CAN_DIAGNOSTIC_OFF                     0u                                                          */
+/*          #define  CAN_DIAGNOSTIC_LOOPBACK                1u                                                          */
+/*          #define  CAN_DIAGNOSTIC_SNOOP                   2u                                                          */
+/*                                                                                                                      */
+/*          #define  CAN_DIAGNOSTIC_SELECT                  CAN_DIAGNOSTIC_LOOPBACK                                     */
+/*                                                                                                                      */
+/* ==================================================================================================================== */
+
+
+/*
+*********************************************************************************************************
+*                                               CAN BUS
+*********************************************************************************************************
+*/
+
+#define  CANBUS_EN                              1u              /* Enable CAN Bus Management                            */
+#define  CANBUS_N                               3u              /*   Number of busses                                   */
+#define  CANBUS_ARG_CHK_EN                      1u              /*   Enable runtime argument checking                   */
+#define  CANBUS_TX_HANDLER_EN                   1u              /*   Enable usage of CanBusTxHandler                    */
+#define  CANBUS_RX_HANDLER_EN                   1u              /*   Enable usage of CanBusRxHandler                    */
+#define  CANBUS_NS_HANDLER_EN                   1u              /*   Enable usage of CanBusNsHandler                    */
+												  
+#define  CANBUS_STAT_EN                         1u              /*   Enable Bus Statistics                              */
+#define  CANBUS_TX_QSIZE                 (2u * CANBUS_N)        /*   Transmit Queue Size in CAN Frames for each CAN Bus */
+#define  CANBUS_RX_QSIZE                 (2u * CANBUS_N)        /*   Receive Queue Size in CAN Frames for each CAN Bus  */
+
+#define  CANBUS_HOOK_NS_EN                      1u              /*   Enable Node Status Handler Hook Function           */
+#define  CANBUS_HOOK_RX_EN                      1u              /*   Enable Rx Handler Hook Function                    */
+#define  CANBUS_RX_READ_ALWAYS_EN               1u              /*   If enabled the Rx Handler executes a read even..   */
+                                                                /*   .. when frames can't be allocated                  */
+
+
+/*
+*********************************************************************************************************
+*                                             CAN MESSAGE
+*********************************************************************************************************
+*/
+
+#define  CANMSG_EN                              1u              /* Enable CAN Message Support                           */
+#define  CANMSG_N                               2u              /*   Number of messages                                 */
+#define  CANMSG_ARG_CHK_EN                      1u              /*   Enable runtime argument checking                   */
+
+
+/*
+*********************************************************************************************************
+*                                             CAN SIGNAL
+*********************************************************************************************************
+*/
+
+#define  CANSIG_EN                              1u              /* Enable CAN Signal Database                           */
+#define  CANSIG_N                               3u              /*   Number of signals                                  */
+#define  CANSIG_ARG_CHK_EN                      1u              /*   Enable runtime argument checking                   */
+#define  CANSIG_MAX_WIDTH                       4u              /*   Maximal signal width in byte                       */
+#define  CANSIG_GRANULARITY               CAN_CFG_BYTE          /*   Set signal resolution to byte                      */
+#define  CANSIG_STATIC_CONFIG                   1u              /* To reduce memory usage, declare static signal table  */
+#define  CANSIG_USE_DELETE                      0u              /* To reduce memory usage don't use delete functions    */
+#define  CANSIG_CALLBACK_EN                     0u              /* Enable callback functions                            */
+
+
+/*
+*********************************************************************************************************
+*                                              CAN FRAME
+*********************************************************************************************************
+*/
+
+#define  CANFRM_ARG_CHK_EN                      1u              /* Enable runtime argument checking                     */
+
+
+/*
+*********************************************************************************************************
+*                                               CAN OS
+*********************************************************************************************************
+*/
+
+#define  CANOS_ARG_CHK_EN                       1u              /* Enable runtime argument checking                     */
+
+
+/*
+*********************************************************************************************************
+*                                          CONFIGURATION END
+*********************************************************************************************************
+*/
+
+#endif  /* #ifndef _CAN_CFG_H_ */

src/APP/Aufgabe3/ps7/core0/cfg/cpu_cfg.h

@@ -0,0 +1,216 @@
+/*
+*********************************************************************************************************
+*                                                uC/CPU
+*                                    CPU CONFIGURATION & PORT LAYER
+*
+*                          (c) Copyright 2004-2015; Micrium, Inc.; Weston, FL
+*
+*               All rights reserved.  Protected by international copyright laws.
+*
+*               uC/CPU is provided in source form to registered licensees ONLY.  It is 
+*               illegal to distribute this source code to any third party unless you receive 
+*               written permission by an authorized Micrium representative.  Knowledge of 
+*               the source code may NOT be used to develop a similar product.
+*
+*               Please help us continue to provide the Embedded community with the finest 
+*               software available.  Your honesty is greatly appreciated.
+*
+*               You can find our product's user manual, API reference, release notes and
+*               more information at https://doc.micrium.com.
+*               You can contact us at www.micrium.com.
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                       CPU CONFIGURATION FILE
+*
+*                                              TEMPLATE
+*
+* Filename      : cpu_cfg.h
+* Version       : V1.30.02
+* Programmer(s) : SR
+*                 ITJ
+*                 JBL
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                               MODULE
+*********************************************************************************************************
+*/
+
+#ifndef  CPU_CFG_MODULE_PRESENT
+#define  CPU_CFG_MODULE_PRESENT
+
+
+/*
+*********************************************************************************************************
+*                                       CPU NAME CONFIGURATION
+*
+* Note(s) : (1) Configure CPU_CFG_NAME_EN to enable/disable CPU host name feature :
+*
+*               (a) CPU host name storage
+*               (b) CPU host name API functions
+*
+*           (2) Configure CPU_CFG_NAME_SIZE with the desired ASCII string size of the CPU host name, 
+*               including the terminating NULL character.
+*
+*               See also 'cpu_core.h  GLOBAL VARIABLES  Note #1'.
+*********************************************************************************************************
+*/
+
+                                                                /* Configure CPU host name feature (see Note #1) :      */
+#define  CPU_CFG_NAME_EN                        DEF_DISABLED
+                                                                /*   DEF_DISABLED  CPU host name DISABLED               */
+                                                                /*   DEF_ENABLED   CPU host name ENABLED                */
+
+                                                                /* Configure CPU host name ASCII string size ...        */
+#define  CPU_CFG_NAME_SIZE                                16
+
+
+/*
+*********************************************************************************************************
+*                                     CPU TIMESTAMP CONFIGURATION
+*
+* Note(s) : (1) Configure CPU_CFG_TS_xx_EN to enable/disable CPU timestamp features :
+*
+*               (a) CPU_CFG_TS_32_EN   enable/disable 32-bit CPU timestamp feature
+*               (b) CPU_CFG_TS_64_EN   enable/disable 64-bit CPU timestamp feature
+*
+*           (2) (a) Configure CPU_CFG_TS_TMR_SIZE with the CPU timestamp timer's word size :
+*
+*                       CPU_WORD_SIZE_08         8-bit word size
+*                       CPU_WORD_SIZE_16        16-bit word size
+*                       CPU_WORD_SIZE_32        32-bit word size
+*                       CPU_WORD_SIZE_64        64-bit word size
+*
+*               (b) If the size of the CPU timestamp timer is not a binary multiple of 8-bit octets 
+*                   (e.g. 20-bits or even 24-bits), then the next lower, binary-multiple octet word 
+*                   size SHOULD be configured (e.g. to 16-bits).  However, the minimum supported word 
+*                   size for CPU timestamp timers is 8-bits.
+*
+*                   See also 'cpu_core.h  FUNCTION PROTOTYPES  CPU_TS_TmrRd()  Note #2a'.
+*********************************************************************************************************
+*/
+
+                                                                /* Configure CPU timestamp features (see Note #1) :     */
+#define  CPU_CFG_TS_32_EN                       DEF_ENABLED
+#define  CPU_CFG_TS_64_EN                       DEF_ENABLED
+                                                                /*   DEF_DISABLED  CPU timestamps DISABLED              */
+                                                                /*   DEF_ENABLED   CPU timestamps ENABLED               */
+
+                                                                /* Configure CPU timestamp timer word size ...          */
+                                                                /* ... (see Note #2) :                                  */
+#define  CPU_CFG_TS_TMR_SIZE                    CPU_WORD_SIZE_64
+
+
+/*
+*********************************************************************************************************
+*                        CPU INTERRUPTS DISABLED TIME MEASUREMENT CONFIGURATION
+*
+* Note(s) : (1) (a) Configure CPU_CFG_INT_DIS_MEAS_EN to enable/disable measuring CPU's interrupts 
+*                   disabled time :
+*
+*                   (a)  Enabled,       if CPU_CFG_INT_DIS_MEAS_EN      #define'd in 'cpu_cfg.h'
+*
+*                   (b) Disabled,       if CPU_CFG_INT_DIS_MEAS_EN  NOT #define'd in 'cpu_cfg.h'
+*
+*                   See also 'cpu_core.h  FUNCTION PROTOTYPES  Note #1'.
+*
+*               (b) Configure CPU_CFG_INT_DIS_MEAS_OVRHD_NBR with the number of times to measure & 
+*                   average the interrupts disabled time measurements overhead.
+*
+*                   See also 'cpu_core.c  CPU_IntDisMeasInit()  Note #3a'.
+*********************************************************************************************************
+*/
+
+#if 0                                                           /* Configure CPU interrupts disabled time ...           */
+#define  CPU_CFG_INT_DIS_MEAS_EN                                /* ... measurements feature (see Note #1a).             */
+#endif
+
+                                                                /* Configure number of interrupts disabled overhead ... */
+#define  CPU_CFG_INT_DIS_MEAS_OVRHD_NBR                    1u   /* ... time measurements (see Note #1b).                */
+
+
+/*
+*********************************************************************************************************
+*                                    CPU COUNT ZEROS CONFIGURATION
+*
+* Note(s) : (1) (a) Configure CPU_CFG_LEAD_ZEROS_ASM_PRESENT  to define count leading  zeros bits 
+*                   function(s) in :
+*
+*                   (1) 'cpu_a.asm',  if CPU_CFG_LEAD_ZEROS_ASM_PRESENT       #define'd in 'cpu.h'/
+*                                         'cpu_cfg.h' to enable assembly-optimized function(s)
+*
+*                   (2) 'cpu_core.c', if CPU_CFG_LEAD_ZEROS_ASM_PRESENT   NOT #define'd in 'cpu.h'/
+*                                         'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
+*
+*               (b) Configure CPU_CFG_TRAIL_ZEROS_ASM_PRESENT to define count trailing zeros bits 
+*                   function(s) in :
+*
+*                   (1) 'cpu_a.asm',  if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT      #define'd in 'cpu.h'/
+*                                         'cpu_cfg.h' to enable assembly-optimized function(s)
+*
+*                   (2) 'cpu_core.c', if CPU_CFG_TRAIL_ZEROS_ASM_PRESENT  NOT #define'd in 'cpu.h'/
+*                                         'cpu_cfg.h' to enable C-source-optimized function(s) otherwise
+*********************************************************************************************************
+*/
+
+#if 0                                                           /* Configure CPU count leading  zeros bits ...          */
+#define  CPU_CFG_LEAD_ZEROS_ASM_PRESENT                         /* ... assembly-version (see Note #1a).                 */
+#endif
+
+#if 0                                                           /* Configure CPU count trailing zeros bits ...          */
+#define  CPU_CFG_TRAIL_ZEROS_ASM_PRESENT                        /* ... assembly-version (see Note #1b).                 */
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                      CPU ENDIAN TYPE OVERRIDE
+*
+* Note(s) : (1) Configure CPU_CFG_ENDIAN_TYPE to override the default CPU endian type defined in cpu.h.
+*
+*               (a) CPU_ENDIAN_TYPE_BIG         Big-   endian word order (CPU words' most  significant
+*                                                                         octet @ lowest memory address)
+*               (b) CPU_ENDIAN_TYPE_LITTLE      Little-endian word order (CPU words' least significant
+*                                                                         octet @ lowest memory address)
+*
+*           (2) Defining CPU_CFG_ENDIAN_TYPE here is only valid for supported bi-endian architectures.
+*               See  'cpu.h  CPU WORD CONFIGURATION  Note #3' for details
+*********************************************************************************************************
+*/
+
+#if 0
+#define  CPU_CFG_ENDIAN_TYPE            CPU_ENDIAN_TYPE_BIG     /* Defines CPU data    word-memory order (see Note #2). */
+#endif
+
+
+/*
+*********************************************************************************************************
+*                                          CACHE MANAGEMENT
+*
+* Note(s) : (1) Configure CPU_CFG_CACHE_MGMT_EN to enable the cache managment API.
+
+*
+*           (2) Defining CPU_CFG_CACHE_MGMT_EN to DEF_ENABLED only enable the cache management function.
+*               Cache are assumed to be configured and enabled by the time CPU_init() is called.
+*********************************************************************************************************
+*/
+
+#define  CPU_CFG_CACHE_MGMT_EN            DEF_DISABLED
+
+
+/*
+*********************************************************************************************************
+*                                             MODULE END
+*********************************************************************************************************
+*/
+
+#endif                                                          /* End of CPU cfg module include.                       */
+
+#define  CPU_CACHE_CFG_L2C310_BASE_ADDR  0xF8F02000

src/APP/Aufgabe3/ps7/core0/cfg/dhcp-c_cfg.h

@@ -0,0 +1,146 @@
+/*
+*********************************************************************************************************
+*                                               uC/DHCPc
+*                              Dynamic Host Configuration Protocol Client
+*
+*                         (c) Copyright 2004-2014; Micrium, Inc.; Weston, FL
+*
+*                  All rights reserved.  Protected by international copyright laws.
+*
+*                  uC/DHCP is provided in source form to registered licensees ONLY.  It is
+*                  illegal to distribute this source code to any third party unless you receive
+*                  written permission by an authorized Micrium representative.  Knowledge of
+*                  the source code may NOT be used to develop a similar product.
+*
+*                  Please help us continue to provide the Embedded community with the finest
+*                  software available.  Your honesty is greatly appreciated.
+*
+*                  You can find our product's user manual, API reference, release notes and
+*                  more information at: https://doc.micrium.com
+*
+*                  You can contact us at: http://www.micrium.com
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                   DHCP CLIENT CONFIGURATION FILE
+*
+*                                              TEMPLATE
+*
+* Filename      : dhcp-c_cfg.h
+* Version       : V2.10.00
+* Programmer(s) : SR
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                           TASKS PRIORITIES
+* Notes: (1) Task priorities configuration values should be used by the DHCPc OS port. The following task priorities
+*            should be defined:
+*
+*                   DHCPc_OS_CFG_TASK_PRIO
+*                   DHCPc_OS_CFG_TMR_TASK_PRIO
+*
+*            Task priorities can be defined either in this configuration file 'dhcp-c_cfg.h' or in a global
+*            OS tasks priorities configuration header file which must be included in 'dhcp-c_cfg.h'.
+*********************************************************************************************************
+*/
+
+                                                                /* See Note #1.                                         */
+#define  DHCPc_OS_CFG_TASK_PRIO                           13
+#define  DHCPc_OS_CFG_TMR_TASK_PRIO                       14
+
+
+/*
+*********************************************************************************************************
+*                                              STACK SIZES
+*            Size (depth) of the task stacks (See the definition of CPU_STK for stack width)
+*********************************************************************************************************
+*/
+
+#define  DHCPc_OS_CFG_TASK_STK_SIZE                      512
+#define  DHCPc_OS_CFG_TMR_TASK_STK_SIZE 256
+
+
+/*
+*********************************************************************************************************
+*                                                 DHCPc
+*
+* Note(s) : (1) Default port for DHCP server is 67, and default port for DHCP client is 68.
+*
+*           (3) Configure DHCPc_CFG_MAX_NBR_IF to the maximum number of interface this DHCP client will
+*               be able to manage at a given time.
+*
+*           (4) Once the DHCP server has assigned the client an address, the later may perform a final
+*               check prior to use this address in order to make sure it is not being used by another
+*               host on the network.
+*********************************************************************************************************
+*/
+
+#define  DHCPc_CFG_IP_PORT_SERVER                         67
+#define  DHCPc_CFG_IP_PORT_CLIENT                         68
+
+#define  DHCPc_CFG_MAX_RX_TIMEOUT_MS                    1000
+
+#define  DHCPc_CFG_PARAM_REQ_TBL_SIZE                      5
+
+#define  DHCPc_CFG_MAX_NBR_IF                              1
+
+#define  DHCPc_CFG_ADDR_VALIDATE_EN              DEF_ENABLED
+                                                                /* ... (see Note #4) :                                  */
+                                                                /*   DEF_DISABLED  Validation NOT performed             */
+                                                                /*   DEF_ENABLED   Validation     performed             */
+
+#define  DHCPc_CFG_DYN_LOCAL_LINK_ADDR_EN        DEF_ENABLED
+                                                                /*   DEF_DISABLED  local-link configuration DISABLED    */
+                                                                /*   DEF_ENABLED   local-link configuration ENABLED     */
+
+#define  DHCPc_CFG_LOCAL_LINK_MAX_RETRY                    3
+                                                                /* link-local address.                                  */
+
+
+/*
+*********************************************************************************************************
+*                                 DHCPc ARGUMENT CHECK CONFIGURATION
+*
+* Note(s) : (1) Configure DHCPc_CFG_ARG_CHK_EXT_EN to enable/disable the DHCP client external argument
+*               check feature :
+*
+*               (a) When ENABLED,  ALL arguments received from any port interface provided by the developer
+*                   or application are checked/validated.
+*
+*               (b) When DISABLED, NO  arguments received from any port interface provided by the developer
+*                   or application are checked/validated.
+*
+*           (2) Configure DHCPc_CFG_ARG_CHK_DBG_EN to enable/disable the DHCP client internal debug
+*               argument check feature :
+*
+*               (a) When ENABLED,     internal arguments are checked/validated to debug the DHCP client.
+*
+*               (b) When DISABLED, NO internal arguments are checked/validated to debug the DHCP client.
+*
+*           (3) Configure DHCPc_DBG_CFG_MEM_CLR_EN to enable/disable the DHCP client from clearing
+*               internal data structure memory buffers; a convenient feature while debugging.
+*********************************************************************************************************
+*/
+                                                                /* Configure external argument check feature ...        */
+                                                                /* ... (see Note #1) :                                  */
+#define  DHCPc_CFG_ARG_CHK_EXT_EN                DEF_ENABLED
+                                                                /*   DEF_DISABLED     Argument check DISABLED           */
+                                                                /*   DEF_ENABLED      Argument check ENABLED            */
+
+                                                                /* Configure internal argument check feature ...        */
+                                                                /* ... (see Note #2) :                                  */
+#define  DHCPc_CFG_ARG_CHK_DBG_EN                DEF_DISABLED
+                                                                /*   DEF_DISABLED     Argument check DISABLED           */
+                                                                /*   DEF_ENABLED      Argument check ENABLED            */
+
+                                                                /* Configure memory clear feature  (see Note #3) :      */
+#define  DHCPc_DBG_CFG_MEM_CLR_EN                DEF_DISABLED
+                                                                /*   DEF_DISABLED     Data structure clears DISABLED    */
+                                                                /*   DEF_ENABLED      Data structure clears ENABLED     */
+

src/APP/Aufgabe3/ps7/core0/cfg/dns-c_cfg.h

@@ -0,0 +1,111 @@
+/*
+*********************************************************************************************************
+*                                               uC/DNSc
+*                                     Domain Name Server (client)
+*
+*                         (c) Copyright 2004-2014; Micrium, Inc.; Weston, FL
+*
+*                  All rights reserved.  Protected by international copyright laws.
+*
+*                  uC/DNSc is provided in source form to registered licensees ONLY.  It is
+*                  illegal to distribute this source code to any third party unless you receive
+*                  written permission by an authorized Micrium representative.  Knowledge of
+*                  the source code may NOT be used to develop a similar product.
+*
+*                  Please help us continue to provide the Embedded community with the finest
+*                  software available.  Your honesty is greatly appreciated.
+*
+*                  You can find our product's user manual, API reference, release notes and
+*                  more information at: https://doc.micrium.com
+*
+*                  You can contact us at: http://www.micrium.com
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                    DNS CLIENT CONFIGURATION FILE
+*
+*                                              TEMPLATE
+*
+* Filename      : dns-c_cfg.h
+* Version       : V2.00.01
+* Programmer(s) : AA
+*********************************************************************************************************
+*/
+
+#ifndef DNSc_CFG_MODULE_PRESENT
+#define DNSc_CFG_MODULE_PRESENT
+
+#include  <Source/dns-c_type.h>
+
+
+/*
+*********************************************************************************************************
+*                                  DNSc ARGUMENT CHECK CONFIGURATION
+*
+* Note(s) : (1) Configure DNSc_CFG_ARG_CHK_EXT_EN to enable/disable the DNS client external argument
+*               check feature :
+*
+*               (a) When ENABLED,  ALL arguments received from any port interface provided by the developer
+*                   are checked/validated.
+*
+*               (b) When DISABLED, NO  arguments received from any port interface provided by the developer
+*                   are checked/validated.
+*********************************************************************************************************
+*/
+                                                                /* Configure external argument check feature ...        */
+                                                                /* See Note 1.                                          */
+#define  DNSc_CFG_ARG_CHK_EXT_EN                    DEF_DISABLED
+                                                                /* DEF_DISABLED     External argument check DISABLED    */
+                                                                /* DEF_ENABLED      External argument check ENABLED     */
+
+/*
+*********************************************************************************************************
+*                                     DNSc FEATURES CONFIGURATION
+*
+* Note(s) : (1) Configure DNSc_CFG_MODE_ASYNC_EN to enable/disable the DNS client asynchronous communication mode:
+*
+*               (a) When ENABLED,  A dedicated task will handle all host resolution request. It will be possible to
+*                   call DNS API to get remote host address without blocking.
+*
+*               (b) When DISABLED, The API to get remote host will always block until the resolution is completed.
+*
+*           (2) Configure DNSc_CFG_MODE_BLOCK_EN to enable/disable the blocking option when the asynchronous
+*               communication is enabled.
+*
+*               (a) When ENABLED,  It will be possible to block when calling the DNS API to get remote host until the
+*                   resolution is completed (via a flag option).
+*
+*               (b) When DISABLED, The API to get remote host will always be non-blocking, must poll DNS client to
+*                   know when the resolution is completed.
+*********************************************************************************************************
+*/
+
+                                                                /* Configure asynchronous mode feature, See Note #1 ... */
+#define  DNSc_CFG_MODE_ASYNC_EN                     DEF_DISABLED
+                                                                /* DEF_DISABLED     Asynchronous mode DISABLED          */
+                                                                /* DEF_ENABLED      Asynchronous mode ENABLED           */
+
+
+                                                                /* Configure blocking option feature, See Note #2 ... */
+#define  DNSc_CFG_MODE_BLOCK_EN                     DEF_DISABLED
+                                                                /* DEF_DISABLED     Blocking option DISABLED            */
+                                                                /* DEF_ENABLED      Blocking option ENABLED             */
+
+/*
+*********************************************************************************************************
+*                                DNSc RUN-TIME STRUCTURE CONFIGURATION
+*
+* Note(s) : (1) These structures should be defined into a 'C' file.
+*********************************************************************************************************
+*/
+
+extern  const  DNSc_CFG       DNSc_Cfg;                         /* Must always be defined.                              */
+
+#if (DNSc_CFG_MODE_ASYNC_EN == DEF_ENABLED)
+extern  const  DNSc_CFG_TASK  DNSc_CfgTask;                     /* Not required when Asynchronous mode is disabled.     */
+#endif
+
+#endif

src/APP/Aufgabe3/ps7/core0/cfg/gt_cfg.h

@@ -0,0 +1,23 @@
+/*
+ * gt_cfg.h
+ *
+ *  Created on: Aug 19, 2014
+ *      Author: matthiasb
+ */
+
+#ifndef GT_CFG_H_
+#define GT_CFG_H_
+
+#define GT_USE_NP_REGIONS	1
+#define GT_USE_NP_MEAS		1
+#define GT_NUM_OF_TASKS		3
+#define GT_REPORT_CONSOLE	0
+#define GT_REPORT_SVC		0
+
+#define GT_TTC_DEVICE_ID	    XPAR_PS7_TTC_2_DEVICE_ID
+#define GT_TTC_PWM_INTR_ID		XPAR_XTTCPS_2_INTR
+#define GT_TIMER_TICKS_PER_SEC		10000
+
+#include "../../../../Aufgabe3/ps7/core0/cfg/gt_core_cfg.h"
+
+#endif /* GT_CFG_H_ */

src/APP/Aufgabe3/ps7/core0/cfg/gt_core_cfg.h

@@ -0,0 +1,24 @@
+/*
+ * gt_core_cfg.h
+ *
+ *  Created on: Aug 19, 2014
+ *      Author: matthiasb
+ */
+
+#ifndef GT_CORE_CFG_H_
+#define GT_CORE_CFG_H_
+
+#define GT_USE_CPU_ARM9		0
+#define GT_USE_CPU_CM3		0
+#define GT_USE_CPU_CM7		0
+#define GT_USE_CPU_ARM_V7_A 1
+
+#define GT_STACKSIZE		256
+#define GT_MAXTASKS			10
+#define GT_MAXQACT			5
+
+#if ( GT_NUM_OF_TASKS > GT_MAXTASKS )
+#error "Too many tasks, increase GT_MAXTASKS or decrease GT_NUM_OF_TASKS"
+#endif
+
+#endif /* GT_CORE_CFG_H_ */

src/APP/Aufgabe3/ps7/core0/cfg/http-c_cfg.h

@@ -0,0 +1,224 @@
+/*
+*********************************************************************************************************
+*                                               uC/HTTP
+*                                      Hypertext Transfer Protocol
+*
+*                         (c) Copyright 2004-2015; Micrium, Inc.; Weston, FL
+*
+*                  All rights reserved.  Protected by international copyright laws.
+*
+*                  uC/HTTP is provided in source form to registered licensees ONLY.  It is
+*                  illegal to distribute this source code to any third party unless you receive
+*                  written permission by an authorized Micrium representative.  Knowledge of
+*                  the source code may NOT be used to develop a similar product.
+*
+*                  Please help us continue to provide the Embedded community with the finest
+*                  software available.  Your honesty is greatly appreciated.
+*
+*                  You can find our product's user manual, API reference, release notes and
+*                  more information at: https://doc.micrium.com
+*
+*                  You can contact us at: http://www.micrium.com
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                   HTTP CLIENT CONFIGURATION FILE
+*
+*                                              TEMPLATE
+*
+* Filename      : http-c_cfg.h
+* Version       : V3.00.01
+* Programmer(s) : MM
+*                 AL
+*********************************************************************************************************
+* Note(s)       : (1) Assumes the following versions (or more recent) of software modules are included in
+*                     the project build :
+*
+*                       (a) uC/CPU    V1.29.02
+*                       (b) uC/LIB    V1.38.00
+*                       (c) uC/Common V1.00.00
+*                       (d) uC/TCP-IP V3.03.00
+*
+*
+*                 (2) For additional details on the features available with uC/HTTPc, the API, the
+*                     installation, etc. Please refer to the uC/HTTPc documentation available at
+*                     https://doc.micrium.com/HTTPc.
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                           INCLUDE FILES
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#include  <Common/http.h>
+#include  <Client/Source/http-c_type.h>
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                               MODULE
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#ifndef  HTTPc_CFG_MODULE_PRESENT
+#define  HTTPc_CFG_MODULE_PRESENT
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                      COMPILE-TIME CONFIGURATION
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                                   HTTP ARGUMENT CHECK CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_ARG_CHK_EXT_EN to enable/disable the HTTP client external argument
+*               check feature :
+*
+*               (a) When ENABLED,  ALL arguments received from any port interface provided by the developer
+*                   are checked/validated.
+*
+*               (b) When DISABLED, NO  arguments received from any port interface provided by the developer
+*                   are checked/validated.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_ARG_CHK_EXT_EN                 DEF_ENABLED
+
+
+/*
+*********************************************************************************************************
+*                                    HTTP CLIENT TASK CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_MODE_ASYNC_TASK_EN to enable/disable HTTP client task.
+*               (a) DEF_DISABLED : No HTTP client task will be created to process the HTTP requests.
+*                                  The Blocking HTTPc API will be enabled.
+*
+*               (b) DEF_ENABLED  : An HTTP client task will be created to process all the HTTP requests.
+*                                  The Non-Blocking HTTPc API will be enabled. Therefore, multiple
+*                                  connections can be handle by the task simultaneously.
+*
+*           (2) Configure HTTPc_CFG_MODE_BLOCK_EN to enable/disable the blocking option when the
+*               asynchronous HTTPc Task is enabled.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_MODE_ASYNC_TASK_EN           DEF_DISABLED
+
+#define  HTTPc_CFG_MODE_BLOCK_EN                DEF_ENABLED
+
+
+/*
+*********************************************************************************************************
+*                              HTTP CLIENT PERSISTENT CONNECTION CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_PERSISTENT_EN to enable/disable Persistent Connection support.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_PERSISTENT_EN                DEF_ENABLED
+
+
+/*
+*********************************************************************************************************
+*                                HTTP CLIENT CHUNKED TRANSFER CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_CHUNK_TX_EN to enable/disable Chunked Transfer support in Transmission.
+*
+*           (2) Chunked Transfer in Reception is always enabled.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_CHUNK_TX_EN                  DEF_ENABLED
+
+
+/*
+*********************************************************************************************************
+*                                 HTTP CLIENT QUERY STRING CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_QUERY_STR_EN to enable/disable Query String support in URL.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_QUERY_STR_EN                 DEF_ENABLED
+
+
+/*
+*********************************************************************************************************
+*                                HTTP CLIENT HEADER FIELD CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_HDR_RX_EN to enable/disable header field processing in reception
+*               (i.e for headers received in the HTTP response.
+*
+*           (2) Configure HTTPc_CFG_HDR_TX_EN to enable/disable header field processing in transmission
+*               (i.e for headers to include in the HTTP request.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_HDR_RX_EN                    DEF_ENABLED
+
+
+#define  HTTPc_CFG_HDR_TX_EN                    DEF_ENABLED
+
+
+/*
+*********************************************************************************************************
+*                                     HTTP CLIENT FORM CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_FORM_EN to enable/disable HTTP form creation source code.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_FORM_EN                      DEF_ENABLED
+
+
+/*
+*********************************************************************************************************
+*                                   HTTP CLIENT USER DATA CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_USER_DATA_EN         to enable/disable user data pointer in HTTPc_CONN
+*                                                        and HTTPc_REQ structure.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_USER_DATA_EN                 DEF_ENABLED
+
+
+/*
+*********************************************************************************************************
+*                                   HTTP CLIENT WEBSOCKET CONFIGURATION
+*
+* Note(s) : (1) Configure HTTPc_CFG_WEBSOCKET_EN        to enable/disable the Websocket feature.
+*********************************************************************************************************
+*/
+
+#define  HTTPc_CFG_WEBSOCKET_EN                 DEF_DISABLED
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                      RUN-TIME CONFIGURATION
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+extern  const  HTTP_TASK_CFG   HTTPc_TaskCfg;
+extern  const  HTTPc_CFG       HTTPc_Cfg;
+
+
+/* =============================================== END =============================================== */
+#endif  /* HTTPc_CFG_MODULE_PRESENT */

src/APP/Aufgabe3/ps7/core0/cfg/imu.h

@@ -0,0 +1,45 @@
+/*
+ * imu.h
+ *
+ *  Created on: Nov 6, 2018
+ *      Author: laurenzb
+ */
+
+#ifndef SRC_APP_AUFGABE7_PS7_CORE0_CFG_IMU_H_
+#define SRC_APP_AUFGABE7_PS7_CORE0_CFG_IMU_H_
+
+#include <stdio.h>
+
+#include "../../../../Aufgabe3/ps7/core0/cfg/xparameters.h"
+#include "xiicps.h"
+
+
+
+
+#define MPU9250_AD   0x68   			//Adresse d. I²C slaves festlegen
+#define GYRO_CONFIG_AD 0x1B        		//Gyroskop config register
+#define ACCEL_CONFIG_1_AD 0x1C     		//Beschleunigungssensor config reg1
+#define ACCEL_CONFIG_2_AD 0x1D        	//Beschleunigungssensor config reg1
+#define CONFIG_AD 0x1A            		//IMU config reg
+#define PWR_MGMT_1_AD 0x6B				//cloc power management register
+#define GYRO_XOUT_H_AD 0x43     		//hier das Startregister der Gyroskopdaten
+#define ACCEL_XOUT_H_AD 0x3B    		//startreg Accel Daten
+
+#define IIC_DEVICE_ID	XPAR_XIICPS_1_DEVICE_ID //??? in xparameters.h noch die iic Daten für das Gerät festlegen?
+#define IIC_SCLK_RATE	100000
+
+unsigned int mpu9250_Imu_Init(void *pdata);
+uint8_t mpu9250_Iic_Init();
+void mpu9250_Init(void);
+uint8_t mpu9250_Write_Reg(uint8_t iic_address, uint8_t data);
+int8_t mpu9250_Read_Data(uint8_t iic_address, uint8_t length, u8 RecvBuffer[]);
+uint8_t mpu9250_Map_Gyro_Data(int16_t result[]);
+uint8_t mpu9250_Map_Acc_Data(int16_t result[]);
+uint8_t mpu9250_Read_Status(int16_t result[]);
+unsigned int mpu9250_Get_Data_Task(void *pdata);
+
+
+
+#endif /* SRC_APP_AUFGABE7_PS7_CORE0_CFG_IMU_H_ */
+
+

src/APP/Aufgabe3/ps7/core0/cfg/intr_timer.h

@@ -0,0 +1,58 @@
+/*
+ * intr_timer.h
+ *
+ *  Created on: Nov 13, 2018
+ *      Author: laurenzb
+ */
+
+#ifndef SRC_APP_AUFGABE3_PS7_CORE0_CFG_INTR_TIMER_H_
+/************************** Constant Definitions *****************************/
+
+/*
+ * The following constants map to the XPAR parameters created in the
+ * xparameters.h file. They are only defined here such that a user can easily
+ * change all the needed parameters in one place.
+ */
+#define TTC_TICK_DEVICE_ID	XPAR_XTTCPS_1_DEVICE_ID
+#define TTC_TICK_INTR_ID	XPAR_XTTCPS_1_INTR
+
+#define TTC_PWM_DEVICE_ID	XPAR_XTTCPS_0_DEVICE_ID
+#define TTC_PWM_INTR_ID		XPAR_XTTCPS_0_INTR
+#define TTCPS_CLOCK_HZ		XPAR_XTTCPS_0_CLOCK_HZ
+
+#define INTC_DEVICE_ID		XPAR_SCUGIC_SINGLE_DEVICE_ID
+
+/*
+ * Constants to set the basic operating parameters.
+ * PWM_DELTA_DUTY is critical to the running time of the test. Smaller values
+ * make the test run longer.
+ */
+#define	TICK_TIMER_FREQ_HZ	100  /* Tick timer counter's output frequency */
+#define	PWM_OUT_FREQ		350  /* PWM timer counter's output frequency */
+
+#define PWM_DELTA_DUTY	50 /* Initial and increment to duty cycle for PWM */
+#define TICKS_PER_CHANGE_PERIOD TICK_TIMER_FREQ_HZ * 5 /* Tick signals PWM */
+
+
+
+/************************** Function Prototypes ******************************/
+
+static int TmrInterruptExample(void);  /* Main test */
+
+/* Set up routines for timer counters */
+static int SetupTicker(void);
+static int SetupPWM(void);
+static int SetupTimer(int DeviceID);
+
+/* Interleaved interrupt test for both timer counters */
+static int WaitForDutyCycleFull(void);
+
+static int SetupInterruptSystem(u16 IntcDeviceID, XScuGic *IntcInstancePtr);
+
+static void TickHandler(void *CallBackRef);
+static void PWMHandler(void *CallBackRef);
+
+
+
+
+#endif /* SRC_APP_AUFGABE3_PS7_CORE0_CFG_INTR_TIMER_H_ */

src/APP/Aufgabe3/ps7/core0/cfg/lib_cfg.h

@@ -0,0 +1,171 @@
+/*
+*********************************************************************************************************
+*                                            EXAMPLE CODE
+*
+*               This file is provided as an example on how to use Micrium products.
+*
+*               Please feel free to use any application code labeled as 'EXAMPLE CODE' in
+*               your application products.  Example code may be used as is, in whole or in
+*               part, or may be used as a reference only. This file can be modified as
+*               required to meet the end-product requirements.
+*
+*               Please help us continue to provide the Embedded community with the finest
+*               software available.  Your honesty is greatly appreciated.
+*
+*               You can find information about uC/LIB by visiting doc.micrium.com.
+*               You can contact us at: http://www.micrium.com
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                  CUSTOM LIBRARY CONFIGURATION FILE
+*
+*                                              TEMPLATE
+*
+* Filename      : lib_cfg.h
+* Version       : V1.38.01.00
+* Programmer(s) : FBJ
+*                 JFD
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                               MODULE
+*********************************************************************************************************
+*/
+
+#ifndef  LIB_CFG_MODULE_PRESENT
+#define  LIB_CFG_MODULE_PRESENT
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                    MEMORY LIBRARY CONFIGURATION
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                             MEMORY LIBRARY ARGUMENT CHECK CONFIGURATION
+*
+* Note(s) : (1) Configure LIB_MEM_CFG_ARG_CHK_EXT_EN to enable/disable the memory library suite external
+*               argument check feature :
+*
+*               (a) When ENABLED,     arguments received from any port interface provided by the developer
+*                   or application are checked/validated.
+*
+*               (b) When DISABLED, NO arguments received from any port interface provided by the developer
+*                   or application are checked/validated.
+*********************************************************************************************************
+*/
+
+                                                                /* External argument check.                             */
+                                                                /* Indicates if arguments received from any port ...    */
+                                                                /* ... interface provided by the developer or ...       */
+                                                                /* ... application are checked/validated.               */
+#define  LIB_MEM_CFG_ARG_CHK_EXT_EN     DEF_DISABLED
+
+
+/*
+*********************************************************************************************************
+*                         MEMORY LIBRARY ASSEMBLY OPTIMIZATION CONFIGURATION
+*
+* Note(s) : (1) Configure LIB_MEM_CFG_OPTIMIZE_ASM_EN to enable/disable assembly-optimized memory function(s).
+*********************************************************************************************************
+*/
+
+                                                                /* Assembly-optimized function(s).                      */
+                                                                /* Enable/disable assembly-optimized memory ...         */
+                                                                /* ... function(s). [see Note #1]                       */
+#define  LIB_MEM_CFG_OPTIMIZE_ASM_EN    DEF_DISABLED
+
+
+/*
+*********************************************************************************************************
+*                                   MEMORY ALLOCATION CONFIGURATION
+*
+* Note(s) : (1) Configure LIB_MEM_CFG_DBG_INFO_EN to enable/disable memory allocation usage tracking
+*               that associates a name with each segment or dynamic pool allocated.
+*
+*           (2) (a) Configure LIB_MEM_CFG_HEAP_SIZE with the desired size of heap memory (in octets).
+*
+*               (b) Configure LIB_MEM_CFG_HEAP_BASE_ADDR to specify a base address for heap memory :
+*
+*                   (1) Heap initialized to specified application memory, if LIB_MEM_CFG_HEAP_BASE_ADDR
+*                                                                                #define'd in 'lib_cfg.h';
+*                                                                         CANNOT #define to address 0x0
+*
+*                   (2) Heap declared to Mem_Heap[] in 'lib_mem.c',       if LIB_MEM_CFG_HEAP_BASE_ADDR
+*                                                                            NOT #define'd in 'lib_cfg.h'
+*********************************************************************************************************
+*/
+
+                                                                /* Allocation debugging information.                    */
+                                                                /* Enable/disable allocation of debug information ...   */
+                                                                /* ... associated to each memory allocation.            */
+#define  LIB_MEM_CFG_DBG_INFO_EN        DEF_DISABLED
+
+
+                                                                /* Heap memory size (in bytes).                         */
+                                                                /* Configure the desired size of the heap memory. ...   */
+                                                                /* ... Set to 0 to disable heap allocation features.    */
+#define  LIB_MEM_CFG_HEAP_SIZE                  64*1024
+
+
+                                                                /* Heap memory padding alignment (in bytes).            */
+                                                                /* Configure the desired size of padding alignment ...  */
+                                                                /* ... of each buffer allocated from the heap.          */
+#define  LIB_MEM_CFG_HEAP_PADDING_ALIGN    LIB_MEM_PADDING_ALIGN_NONE
+
+#if 0                                                           /* Remove this to have heap alloc at specified addr.    */
+#define  LIB_MEM_CFG_HEAP_BASE_ADDR       0
+#endif
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                    STRING LIBRARY CONFIGURATION
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                                 STRING FLOATING POINT CONFIGURATION
+*
+* Note(s) : (1) Configure LIB_STR_CFG_FP_EN to enable/disable floating point string function(s).
+*
+*           (2) Configure LIB_STR_CFG_FP_MAX_NBR_DIG_SIG to configure the maximum number of significant
+*               digits to calculate &/or display for floating point string function(s).
+*
+*               See also 'lib_str.h  STRING FLOATING POINT DEFINES  Note #1'.
+*********************************************************************************************************
+*/
+
+                                                                /* Floating point feature(s).                           */
+                                                                /* Enable/disable floating point to string functions.   */
+#define  LIB_STR_CFG_FP_EN                      DEF_DISABLED
+
+
+                                                                /* Floating point number of significant digits.         */
+                                                                /* Configure the maximum number of significant ...      */
+                                                                /* ... digits to calculate &/or display for ...         */
+                                                                /* ... floating point string function(s).               */
+#define  LIB_STR_CFG_FP_MAX_NBR_DIG_SIG         LIB_STR_FP_MAX_NBR_DIG_SIG_DFLT
+
+
+/*
+*********************************************************************************************************
+*                                             MODULE END
+*********************************************************************************************************
+*/
+
+#endif                                                          /* End of lib cfg module include.                       */
+

src/APP/Aufgabe3/ps7/core0/cfg/mmu_cfg.h

@@ -0,0 +1,42 @@
+/*
+ * mmu_cfg.h
+ *
+ *  Created on: 25.04.2018
+ *      Author: kaige
+ */
+
+#ifndef SRC_APP_LWIPREWORK_PS7_CORE0_CFG_MMU_CFG_H_
+#define SRC_APP_LWIPREWORK_PS7_CORE0_CFG_MMU_CFG_H_
+
+#include "mmu.h"
+
+/*------------------------------------------------------------------------------------------------*/
+/*!
+* \brief    FIRST LEVEL TRANSLATION TABLE (FTT)
+*
+* \ingroup  PAR_CPU_MMU
+*
+*           This variable represents the first level translation table. Each entry within
+*           the table represents the configuration of a 1MB memory segment. If a memory
+*           portion below 1MB must be accessed, the entry represents a pointer to the
+*           linked coarse page table, which contains the information of that 1MB in detail.
+*
+* \note     This table MUST be aligned at 16kB boundary.
+*/
+/*------------------------------------------------------------------------------------------------*/
+
+const PAR_MEM_REGION_T PARMemTbl_Core[]  = {
+/*   +-------------------------------------------------------------------------------------------+
+*    | virtual   | physical  |     size      |   owner          |  permissions    |    HID Field |
+*    +-----------+-----------+---------------+------------------+-----------------+--------------+*/
+	// First 1MB is marked as non-cacheable/non-bufferable (contains 3x 64KB SRAM @ address 0x00000000
+	{ 0x00000000, 0x00000000, MMU_SIZE_1MB,   PAR_AP_PRW__URW_, PAR_HID_TEX_CB_CACHED_MEMORY | PAR_HID_CACHE_INNER_CB | PAR_HID_CACHE_OUTER_CB },
+    // DDR Memory is marked as normal (only 512MB for now)
+	{ 0x00100000, 0x00100000, MMU_SIZE_16MB, PAR_AP_PRW__URW_, PAR_HID_TEX_CB_CACHED_MEMORY | PAR_HID_CACHE_INNER___ | PAR_HID_CACHE_OUTER___ },
+    // Device section
+	{ 0xE0000000, 0xE0000000, MMU_SIZE_512MB-MMU_SIZE_1MB, PAR_AP_PRW__URW_, PAR_HID_EXCLUSIVE_SYS_DEVICE },
+	// Upper 1MB section contains 1x 64KB SRAM @ address 0xFFFF0000
+	{ 0xFFF00000, 0xFFF00000, MMU_SIZE_1MB,   PAR_AP_PRW__URW_, PAR_HID_TEX_CB_OUT_IN_NON_CACHABLE }
+};
+
+#endif /* SRC_APP_LWIPREWORK_PS7_CORE0_CFG_MMU_CFG_H_ */

src/APP/Aufgabe3/ps7/core0/cfg/net_cfg.h

@@ -0,0 +1,676 @@
+/*
+*********************************************************************************************************
+*                                             uC/TCP-IP
+*                                      The Embedded TCP/IP Suite
+*
+*                         (c) Copyright 2004-2015; Micrium, Inc.; Weston, FL
+*
+*                  All rights reserved.  Protected by international copyright laws.
+*
+*                  uC/TCP-IP is provided in source form to registered licensees ONLY.  It is
+*                  illegal to distribute this source code to any third party unless you receive
+*                  written permission by an authorized Micrium representative.  Knowledge of
+*                  the source code may NOT be used to develop a similar product.
+*
+*                  Please help us continue to provide the Embedded community with the finest
+*                  software available.  Your honesty is greatly appreciated.
+*
+*                  You can find our product's user manual, API reference, release notes and
+*                  more information at: https://doc.micrium.com
+*
+*                  You can contact us at: http://www.micrium.com
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                     NETWORK CONFIGURATION FILE
+*
+*                                              TEMPLATE
+*
+* Filename : net_cfg.h
+* Version  : V3.03.01
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                            INCLUDE FILES
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#include  <net_def.h>
+#include  <net_type.h>
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                               MODULE
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#ifndef  NET_CFG_MODULE_PRESENT
+#define  NET_CFG_MODULE_PRESENT
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                             NETWORK EXTERNAL APPLICATION CONFIGURATION
+*
+* Note(s) : (1) When uC/DNS-Client is present in the project some high level functions can resolve hostname.
+*               So uC/TCPIP should know that uC/DNS-Client is present to call the proper API.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+                                                                /* Configure DNS Client feature  (see Note #1) :        */
+#define  NET_EXT_MODULE_CFG_DNS_EN                                 DEF_ENABLED
+                                                                /*   DEF_DISABLED       DNS Client is DISABLED          */
+                                                                /*   DEF_ENABLED        DNS Client is  ENABLED          */
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                        TASKS CONFIGURATION
+*
+* Note(s) : (1) (a) Each network task maps to a unique, developer-configured task configuration that
+*                   MUST be defined in application files, typically 'net_cfg.c', & SHOULD be forward-
+*                   declared with the exact same name & type in order to be used by the application during
+*                   calls to Net_Init().
+*
+*               (b) Since these task configuration structures are referenced ONLY by application files,
+*                   there is NO required naming convention for these configuration structures.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+extern  const  NET_TASK_CFG  NetRxTaskCfg;
+extern  const  NET_TASK_CFG  NetTxDeallocTaskCfg;
+extern  const  NET_TASK_CFG  NetTmrTaskCfg;
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                        TASKS Q CONFIGURATION
+*
+* Note(s) : (1) Rx queue size should be configured such that it reflects the total number of DMA receive descriptors on all
+*               devices. If DMA is not available, or a combination of DMA and I/O based interfaces are configured then this
+*               number reflects the maximum number of packets that can be acknowledged and signalled during a single receive
+*               interrupt event for all interfaces.
+*
+*           (2) Tx queue size should be defined to be the total number of small and large transmit buffers declared for
+*               all interfaces.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#define  NET_CFG_IF_RX_Q_SIZE                   100
+#define  NET_CFG_IF_TX_DEALLOC_Q_SIZE           100
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                        NETWORK CONFIGURATION
+*
+* Note(s) : (1) uC/TCP-IP code may call optimized assembly functions. Optimized assembly files/functions must be included
+*               in the project to be enabled. Optimized functions are located in files under folders:
+*
+*                   $uC-TCPIP/Ports/<processor>/<compiler>
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+                                                                /* Configure network protocol suite's assembly ...      */
+                                                                /* ... optimization (see Note #1) :                     */
+#define  NET_CFG_OPTIMIZE_ASM_EN                DEF_DISABLED
+                                                                /*   DEF_DISABLED       Assembly optimization DISABLED  */
+                                                                /*   DEF_ENABLED        Assembly optimization ENABLED   */
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                     NETWORK DEBUG CONFIGURATION
+*
+* Note(s) : (1) Configure NET_DBG_CFG_MEM_CLR_EN to enable/disable the network protocol suite from clearing
+*               internal data structure memory buffers; a convenient feature while debugging.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+                                                                /* Configure memory clear feature  (see Note #1) :      */
+#define  NET_DBG_CFG_MEM_CLR_EN                 DEF_DISABLED
+                                                                /*   DEF_DISABLED  Data structure clears DISABLED       */
+                                                                /*   DEF_ENABLED   Data structure clears ENABLED        */
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                NETWORK ARGUMENT CHECK CONFIGURATION
+*
+* Note(s) : (1) Configure NET_ERR_CFG_ARG_CHK_EXT_EN to enable/disable the network protocol suite external
+*               argument check feature :
+*
+*               (a) When ENABLED,  ALL arguments received from any port interface provided by the developer
+*                   or application are checked/validated.
+*
+*               (b) When DISABLED, NO  arguments received from any port interface provided by the developer
+*                   or application are checked/validated.
+*
+*           (2) Configure NET_ERR_CFG_ARG_CHK_DBG_EN to enable/disable the network protocol suite internal,
+*               debug argument check feature :
+*
+*               (a) When ENABLED,     internal arguments are checked/validated to debug the network protocol
+*                   suite.
+*
+*               (b) When DISABLED, NO internal arguments are checked/validated to debug the network protocol
+*                   suite.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+                                                                /* Configure external argument check feature ...        */
+                                                                /* ... (see Note #1) :                                  */
+#define  NET_ERR_CFG_ARG_CHK_EXT_EN             DEF_ENABLED
+                                                                /*   DEF_DISABLED     Argument check DISABLED           */
+                                                                /*   DEF_ENABLED      Argument check ENABLED            */
+
+                                                                /* Configure internal argument check feature ...        */
+                                                                /* ... (see Note #2) :                                  */
+#define  NET_ERR_CFG_ARG_CHK_DBG_EN             DEF_DISABLED
+                                                                /*   DEF_DISABLED     Argument check DISABLED           */
+                                                                /*   DEF_ENABLED      Argument check ENABLED            */
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                               NETWORK COUNTER MANAGEMENT CONFIGURATION
+*
+* Note(s) : (1) Configure NET_CTR_CFG_STAT_EN to enable/disable network protocol suite statistics counters.
+*
+*           (2) Configure NET_CTR_CFG_ERR_EN  to enable/disable network protocol suite error      counters.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+                                                                /* Configure statistics counter feature (see Note #1) : */
+#define  NET_CTR_CFG_STAT_EN                    DEF_DISABLED
+                                                                /*   DEF_DISABLED     Stat  counters DISABLED           */
+                                                                /*   DEF_ENABLED      Stat  counters ENABLED            */
+
+                                                                /* Configure error      counter feature (see Note #2) : */
+#define  NET_CTR_CFG_ERR_EN                     DEF_DISABLED
+                                                                /*   DEF_DISABLED     Error counters DISABLED           */
+                                                                /*   DEF_ENABLED      Error counters ENABLED            */
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                               NETWORK TIMER MANAGEMENT CONFIGURATION
+*
+* Note(s) : (1) Configure NET_TMR_CFG_NBR_TMR with the desired number of network TIMER objects.
+*
+*               Timers are required for :
+*
+*               (a) ARP & NDP cache entries
+*               (b) IP        fragment reassembly
+*               (c) TCP       state machine connections
+*               (d) IF        Link status check-up
+*
+*           (2) Configure NET_TMR_CFG_TASK_FREQ to schedule the execution frequency of the network timer
+*               task -- how often NetTmr_TaskHandler() is scheduled to run per second as implemented in
+*               NetTmr_Task().
+*
+*               (a) NET_TMR_CFG_TASK_FREQ  MUST NOT be configured as a floating-point frequency.
+*
+*               See also 'net_tmr.h  NETWORK TIMER TASK TIME DEFINES  Notes #1 & #2'
+*                      & 'net_tmr.c  NetTmr_Task()  Notes #1 & #2'.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#define  NET_TMR_CFG_NBR_TMR                    100
+#define  NET_TMR_CFG_TASK_FREQ                  10
+
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                NETWORK INTERFACE LAYER CONFIGURATION
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#define  NET_IF_CFG_MAX_NBR_IF                  1
+
+                                                                /* Configure specific interface(s) :                    */
+#define  NET_IF_CFG_LOOPBACK_EN                 DEF_DISABLED
+
+#define  NET_IF_CFG_ETHER_EN                    DEF_ENABLED
+
+#define  NET_IF_CFG_WIFI_EN                     DEF_DISABLED
+                                                                /*   DEF_DISABLED      Interface type DISABLED          */
+                                                                /*   DEF_ENABLED       interface type ENABLED           */
+
+#define  NET_IF_CFG_TX_SUSPEND_TIMEOUT_MS       1
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                           ADDRESS RESOLUTION PROTOCOL LAYER CONFIGURATION
+*
+* Note(s) : (1) Address resolution protocol ONLY required for IPv4.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#define  NET_ARP_CFG_CACHE_NBR                  3
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                           NEIGHBOR DISCOVERY PROTOCOL LAYER CONFIGURATION
+*
+* Note(s) : (1) Neighbor Discovery Protocol ONLY required for IPv6.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#define  NET_NDP_CFG_CACHE_NBR                  5
+#define  NET_NDP_CFG_DEST_NBR                   5
+#define  NET_NDP_CFG_PREFIX_NBR                 5
+#define  NET_NDP_CFG_ROUTER_NBR                 1
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                            INTERNET PROTOCOL LAYER VERSION CONFIGURATION
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                                                IPv4
+*********************************************************************************************************
+*/
+                                                                /* Configure IPv4.                                      */
+#define  NET_IPv4_CFG_EN                        DEF_ENABLED
+                                                                /*   DEF_DISABLED    IPv4 disabled.                     */
+                                                                /*   DEF_ENABLED     IPv4 enabled.                      */
+
+
+#define  NET_IPv4_CFG_IF_MAX_NBR_ADDR           1
+
+/*
+*********************************************************************************************************
+*                                                IPv6
+*********************************************************************************************************
+*/
+
+                                                                /* Configure IPv6.                                      */
+#define  NET_IPv6_CFG_EN                        DEF_DISABLED
+                                                                /*   DEF_DISABLED    IPv6 disabled.                     */
+                                                                /*   DEF_ENABLED     IPv6 enabled.                      */
+
+                                                                /* Configure IPv6 Stateless Address Auto-Configuration. */
+#define  NET_IPv6_CFG_ADDR_AUTO_CFG_EN          DEF_ENABLED
+                                                                /*   DEF_DISABLED    IPv6 Auto-Cfg disabled.            */
+                                                                /*   DEF_ENABLED     IPv6 Auto-Cfg enabled.             */
+
+                                                                /* Configure IPv6 Duplication Address Detection (DAD).  */
+#define  NET_IPv6_CFG_DAD_EN                    DEF_ENABLED
+                                                                /*   DEF_DISABLED    IPv6 DAD disabled.                 */
+                                                                /*   DEF_ENABLED     IPv6 DAD enabled.                  */
+
+#define  NET_IPv6_CFG_IF_MAX_NBR_ADDR           2
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                  INTERNET GROUP MANAGEMENT PROTOCOL(MULTICAST) LAYER CONFIGURATION
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+                                                                /* Configure IPv4 multicast support :                   */
+#define  NET_MCAST_CFG_IPv4_RX_EN               DEF_ENABLED
+#define  NET_MCAST_CFG_IPv4_TX_EN               DEF_ENABLED
+                                                                /*   DEF_DISABLED    Multicast rx or tx disabled.       */
+                                                                /*   DEF_ENABLED     Multicast rx or tx enabled.        */
+
+#define  NET_MCAST_CFG_HOST_GRP_NBR_MAX         2
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                 NETWORK SOCKET LAYER CONFIGURATION
+*
+* Note(s) : (1) The maximum accept queue size represents the number of connection that can be queued by
+*               the stack before being accepted. For a TCP server when a connection is queued, it means
+*               that the SYN, ACK packet has been sent back, so the remote host can start transmitting
+*               data once the connection is queued and the stack will queue up all data received until
+*               the connection is accepted and the data is read.
+*
+*           (2) Receive and transmit queue size MUST be properly configured to optimize performance.
+*
+*               (a) It represents the number of bytes that can be queued by one socket. It's important
+*                   that all socket are not able to queue more data than what the device can hold in its
+*                   buffers.
+*
+*               (b) The size should be also a multiple of the maximum segment size (MSS) to optimize
+*                   performance. UDP MSS is 1470 and TCP MSS is 1460.
+*
+*               (c) RX and TX queue size can be reduce at runtime using socket option API.
+*
+*               (d) Window calculation example:
+*
+*                       Number of TCP connection  : 2
+*                       Number of UDP connection  : 0
+*                       Number of RX large buffer : 10
+*                       Number of TX Large buffer : 6
+*                       Number of TX small buffer : 2
+*                       Size of RX large buffer   : 1518
+*                       Size of TX large buffer   : 1518
+*                       Size of TX small buffer   : 60
+*
+*                       TCP MSS RX                = 1460
+*                       TCP MSS TX large buffer   = 1460
+*                       TCP MSS TX small buffer   = 0
+*
+*                       Maximum receive  window   = (10 * 1460)           = 14600 bytes
+*                       Maximum transmit window   = (6  * 1460) + (2 * 0) = 8760  bytes
+*
+*                       RX window size per socket = (14600 / 2)           =  7300 bytes
+*                       TX window size per socket = (8760  / 2)           =  4380 bytes
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#define  NET_SOCK_CFG_SOCK_NBR_TCP              2
+#define  NET_SOCK_CFG_SOCK_NBR_UDP              1
+
+                                                                /* Configure socket select functionality :              */
+#define  NET_SOCK_CFG_SEL_EN                    DEF_ENABLED
+                                                                /*   DEF_DISABLED  Socket select  DISABLED              */
+                                                                /*   DEF_ENABLED   Socket select  ENABLED               */
+
+                                                                /* Configure stream-type sockets' accept queue          */
+#define  NET_SOCK_CFG_CONN_ACCEPT_Q_SIZE_MAX    2
+
+
+                                                                /* Configure sockets' buffer sizes in number of octets  */
+                                                                /* (see Note #2):                                       */
+#define  NET_SOCK_CFG_RX_Q_SIZE_OCTET           4096
+#define  NET_SOCK_CFG_TX_Q_SIZE_OCTET           4096
+
+
+/* ==================================  ADVANCED SOCKET CONFIGURATION: DEFAULT VALUES ================================== */
+/* By default sockets are set to block. Add the following define to set all sockets as non-blocking. Note that it's     */
+/* possible to change socket's blocking mode at runtime using socket option API.                                        */
+/*                                                                                                                      */
+/*     #define  NET_SOCK_DFLT_NO_BLOCK_EN                     DEF_ENABLED                                               */
+/*                                                                                                                      */
+/* By default random port start at 65000, redefine the following define to modify where random port start:              */
+/*                                                                                                                      */
+/*     #define  NET_SOCK_DFLT_PORT_NBR_RANDOM_BASE            65000u                                                    */
+/*                                                                                                                      */
+/* When a socket is set as blocking the following default timeout values are used. Redefine the following defines to    */
+/* change default timeouts. Timeout values may also be configured with network time constant, NET_TMR_TIME_INFINITE,    */
+/* to never time out. Note that it's possible to change at runtime any timeout values using Socket option API.          */
+/*                                                                                                                      */
+/*     #define  NET_SOCK_DFLT_TIMEOUT_RX_Q_MS                 10000u                                                    */
+/*     #define  NET_SOCK_DFLT_TIMEOUT_CONN_REQ_MS             10000u                                                    */
+/*     #define  NET_SOCK_DFLT_TIMEOUT_CONN_ACCEPT_MS          10000u                                                    */
+/*     #define  NET_SOCK_DFLT_TIMEOUT_CONN_CLOSE_MS           10000u                                                    */
+/* ==================================================================================================================== */
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                          TRANSMISSION CONTROL PROTOCOL LAYER CONFIGURATION
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+                                                                /* Configure TCP support :                              */
+#define  NET_TCP_CFG_EN                         DEF_ENABLED
+                                                                /*   DEF_DISABLED  TCP layer  DISABLED                  */
+                                                                /*   DEF_ENABLED   TCP layer  ENABLED                   */
+
+/* ========================================= ADVANCED TCP LAYER CONFIGURATION ========================================= */
+/* By default TCP RX and TX windows are set to equal the socket RX and TX queue sizes. Default values can be changed by */
+/* redefining the following defines. TCP windows must be properly configured to optimize performance (see note about    */
+/* Socket TX and RX windows). Note that it's possible to decrease window size at run time using Socket option API.      */
+/*                                                                                                                      */
+/*     #define  NET_TCP_DFLT_RX_WIN_SIZE_OCTET      NET_SOCK_CFG_RX_Q_SIZE_OCTET                                        */
+/*     #define  NET_TCP_DFLT_TX_WIN_SIZE_OCTET      NET_SOCK_CFG_TX_Q_SIZE_OCTET                                        */
+/*                                                                                                                      */
+/* As shown in the TCP state diagram (see RFC #793), before moving from 'TIME-WAIT' state to 'CLOSED' state a timeout   */
+/* (2MSL) must expire. This means that the TCP connection cannot be made available for subsequent TCP connections until */
+/* this timeout. It can be a problem for embedded systems with low resources especially when many TCP connections are   */
+/* made in a small period of time since it is possible to run out of free TCP connections quickly. Therefore this       */
+/* timeout is set to 0 by default to avoid this kind of problem and the connection is made available as soon as the     */
+/* 'TIME-WAIT' state is reached. However, it's possible to set the default MSL timeout to something else by redefining  */
+/* the following define. Note that it is possible to change the MSL timeout for a specific TCP connection using Socket  */
+/* option API.                                                                                                          */
+/*                                                                                                                      */
+/*     #define  NET_TCP_DFLT_TIMEOUT_CONN_MAX_SEG_SEC       0u                                                          */
+/*                                                                                                                      */
+/* To avoid leaving a connection in the FIN_WAIT_2 state forever when a connection moves from the 'FIN_WAIT_1' state to */
+/* the FIN_WAIT_2, the TCP connection's timer is set to 15 second, and when it expires the connection is dropped. Thus, */
+/* if the other host doesn't response to the close request, the connection will still be closed after the timeout.      */
+/* This default timeout can be change by redefining the following define.                                               */
+/*                                                                                                                      */
+/*     #define  NET_TCP_DFLT_TIMEOUT_CONN_FIN_WAIT_2_SEC    15u                                                         */
+/*                                                                                                                      */
+/* The number of TCP connections is configured following the number of TCP sockets and the accept queue size when the   */
+/* MSL is set to 0 ms. However, since the default MSL can be modified, it might be needed to increase the number of TCP */
+/* connections to establish more connections when waiting for the MSL expiration. It is possible to add more TCP        */
+/* connections by defining the following define.                                                                        */
+/*                                                                                                                      */
+/*     #define  NET_TCP_CFG_NBR_CONN                        0u                                                          */
+/*                                                                                                                      */
+/* By default an 'ACK' is generated within 500 ms of the arrival of the first unacknowledged packet, as specified in    */
+/* RFC #2581, Section 4.2. However it's possible to modify this value by defining the following define.                 */
+/*                                                                                                                      */
+/*     #define  NET_TCP_DFLT_TIMEOUT_CONN_ACK_DLY_MS        500u                                                        */
+/*                                                                                                                      */
+/* When a socket is set as blocking the following default timeout values are used. Redefine the following defines to    */
+/* change default timeout. Timeout values may also be configured with network time constant, NET_TMR_TIME_INFINITE,     */
+/* to never time out. Note that it's possible to change at runtime any timeout values using Socket option API.          */
+/*     #define  NET_TCP_DFLT_TIMEOUT_CONN_RX_Q_MS           1000u                                                       */
+/*     #define  NET_TCP_DFLT_TIMEOUT_CONN_TX_Q_MS           1000u                                                       */
+/* ==================================================================================================================== */
+
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                             USER DATAGRAM PROTOCOL LAYER CONFIGURATION
+*
+* Note(s) : (1) Configure NET_UDP_CFG_APP_API_SEL with the desired configuration for demultiplexing
+*               UDP datagrams to application connections :
+*
+*                   NET_UDP_APP_API_SEL_SOCK        Demultiplex UDP datagrams to BSD sockets ONLY.
+*                   NET_UDP_APP_API_SEL_APP         Demultiplex UDP datagrams to application-specific
+*                                                       connections ONLY.
+*                   NET_UDP_APP_API_SEL_SOCK_APP    Demultiplex UDP datagrams to BSD sockets first;
+*                                                       if NO socket connection found to demultiplex
+*                                                       a UDP datagram, demultiplex to application-
+*                                                       specific connection.
+*
+*               See also 'net_udp.c  NetUDP_RxPktDemuxDatagram()  Note #1'
+*                      & 'net_udp.c  NetUDP_RxPktDemuxAppData()   Note #1'.
+*
+*           (2) (a) RFC #1122, Section 4.1.3.4 states that "an application MAY optionally ... discard
+*                   ... [or allow] ... received ... UDP datagrams without checksums".
+*
+*               (b) Configure NET_UDP_CFG_RX_CHK_SUM_DISCARD_EN to enable/disable discarding of UDP
+*                   datagrams received with NO computed check-sum :
+*
+*                   (1) When ENABLED,  ALL UDP datagrams received without a check-sum are discarded.
+*
+*                   (2) When DISABLED, ALL UDP datagrams received without a check-sum are flagged so
+*                       that application(s) may handle &/or discard.
+*
+*               See also 'net_udp.c  NetUDP_RxPktValidate()  Note #4d3A'.
+*
+*           (3) (a) RFC #1122, Section 4.1.3.4 states that "an application MAY optionally be able to
+*                   control whether a UDP checksum will be generated".
+*
+*               (b) Configure NET_UDP_CFG_TX_CHK_SUM_EN to enable/disable transmitting UDP datagrams
+*                   with check-sums :
+*
+*                   (1) When ENABLED,  ALL UDP datagrams are transmitted with    a computed check-sum.
+*
+*                   (2) When DISABLED, ALL UDP datagrams are transmitted without a computed check-sum.
+*
+*               See also 'net_udp.c  NetUDP_TxPktPrepareHdr()  Note #3b'.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+                                                                /* Configure UDP Receive Check-Sum Discard feature ...  */
+                                                                /* ... (see Note #2b) :                                 */
+#define  NET_UDP_CFG_RX_CHK_SUM_DISCARD_EN      DEF_DISABLED
+                                                                /*   DEF_DISABLED  UDP Check-Sums  Received without ... */
+                                                                /*                     Check-Sums Validated             */
+                                                                /*   DEF_ENABLED   UDP Datagrams  Received without ...  */
+                                                                /*                     Check-Sums Discarded             */
+
+                                                                /* Configure UDP Transmit Check-Sum feature ...         */
+                                                                /* ... (see Note #3b) :                                 */
+#define  NET_UDP_CFG_TX_CHK_SUM_EN              DEF_DISABLED
+                                                                /*   DEF_DISABLED  Transmit Check-Sums  DISABLED        */
+                                                                /*   DEF_ENABLED   Transmit Check-Sums  ENABLED         */
+
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                               NETWORK SECURITY MANAGER CONFIGURATION
+*
+* Note(s): (1) The network security layer can be enabled ONLY if the application project contains a secure module
+*              supported by uC/TCPIP such as:
+*
+*              (a) NanoSSL provided by Mocana.
+*              (b) CyaSSL  provided by YaSSL.
+*
+*          (2) The network security port must be also added to the project. Security port can be found under the folder:
+*
+*                 $uC-TCPIP/Secure/<module>
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+                                                                /* Configure network security layer (See Note #1 & #2): */
+#define  NET_SECURE_CFG_EN                      DEF_DISABLED
+                                                                /*   DEF_DISABLED  Security layer  DISABLED             */
+                                                                /*   DEF_ENABLED   Security layer  ENABLED              */
+
+#define  NET_SECURE_CFG_MAX_NBR_SOCK_SERVER     2u              /* Configure total number of server secure sockets.     */
+#define  NET_SECURE_CFG_MAX_NBR_SOCK_CLIENT     2u              /* Configure total number of client secure sockets.     */
+
+#define  NET_SECURE_CFG_MAX_CERT_LEN            1500u           /* Configure servers certificate maximum length (bytes) */
+#define  NET_SECURE_CFG_MAX_KEY_LEN             1500u           /* Configure servers key maximum length (bytes)         */
+
+                                                                /* Configure maximum number of certificate authorities  */
+#define  NET_SECURE_CFG_MAX_NBR_CA              1u              /* that can be installed.                               */
+
+#define  NET_SECURE_CFG_MAX_CA_CERT_LEN         1500u           /* Configure CA certificate maximum length (bytes)      */
+
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                               INTERFACE CHECKSUM OFFLOAD CONFIGURATION
+*
+* Note(s): (1) These configuration can be enabled only if all your interfaces support specific checksum offload
+*              option.
+*
+*          (2) By default a driver should enabled the all checksum offload option.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+/* ========================================== ADVANCED OFFLOAD CONFIGURATION ========================================== */
+/* By default all checksum are validated by the stack however it is possible to enable or disable specific checksum     */
+/* validate and calculation if the interface controller is able to achieve it. You can add the following define in this */
+/* file to change the default behavior.                                                                                 */
+/*                                                                                                                      */
+/* -------------------------------------------------- IPv4 CHECKSUM --------------------------------------------------- */
+/*                                                  Configure validation in reception.                                  */
+/* #define  NET_IPV4_CFG_CHK_SUM_OFFLOAD_RX_EN  DEF_DISABLED                                                            */
+/*                                                                                                                      */
+/*                                                  Configure calculation in transmission.                              */
+/* #define  NET_IPV4_CFG_CHK_SUM_OFFLOAD_TX_EN  DEF_DISABLED                                                            */
+/*                                                                                                                      */
+/*                                                                                                                      */
+/* -------------------------------------------------- ICMP CHECKSUM --------------------------------------------------- */
+/*                                                  Configure validation in reception.                                  */
+/* #define  NET_ICMP_CFG_CHK_SUM_OFFLOAD_RX_EN  DEF_DISABLED                                                            */
+/*                                                                                                                      */
+/*                                                  Configure calculation in transmission.                              */
+/* #define  NET_ICMP_CFG_CHK_SUM_OFFLOAD_TX_EN  DEF_DISABLED                                                            */
+/*                                                                                                                      */
+/*                                                                                                                      */
+/* --------------------------------------------------- UDP CHECKSUM --------------------------------------------------- */
+/*                                                  Configure validation in reception.                                  */
+/* #define  NET_UDP_CFG_CHK_SUM_OFFLOAD_RX_EN   DEF_DISABLED                                                            */
+/*                                                                                                                      */
+/*                                                  Configure calculation in transmission.                              */
+/* #define  NET_UDP_CFG_CHK_SUM_OFFLOAD_TX_EN   DEF_DISABLED                                                            */
+/*                                                                                                                      */
+/*                                                                                                                      */
+/* --------------------------------------------------- TCP CHECKSUM --------------------------------------------------- */
+/*                                                  Configure validation in reception.                                  */
+/* #define  NET_TCP_CFG_CHK_SUM_OFFLOAD_RX_EN   DEF_DISABLED                                                            */
+/*                                                                                                                      */
+/*                                                  Configure calculation in transmission.                              */
+/* #define  NET_TCP_CFG_CHK_SUM_OFFLOAD_TX_EN   DEF_DISABLED                                                            */
+/* ==================================================================================================================== */
+
+
+/* ======================================================= END ======================================================== */
+#endif  /* NET_CFG_MODULE_PRESENT */
+
+#define  NET_IPV4_CFG_CHK_SUM_OFFLOAD_RX_EN  DEF_DISABLED
+#define  NET_IPV4_CFG_CHK_SUM_OFFLOAD_TX_EN  DEF_DISABLED
+#define  NET_ICMP_CFG_CHK_SUM_OFFLOAD_RX_EN  DEF_DISABLED
+#define  NET_ICMP_CFG_CHK_SUM_OFFLOAD_TX_EN  DEF_DISABLED
+#define  NET_UDP_CFG_CHK_SUM_OFFLOAD_RX_EN  DEF_DISABLED
+#define  NET_UDP_CFG_CHK_SUM_OFFLOAD_TX_EN  DEF_DISABLED
+#define  NET_TCP_CFG_CHK_SUM_OFFLOAD_RX_EN  DEF_DISABLED
+#define  NET_TCP_CFG_CHK_SUM_OFFLOAD_TX_EN  DEF_DISABLED

src/APP/Aufgabe3/ps7/core0/cfg/net_xil_ether_lite_dev_cfg.h

@@ -0,0 +1,115 @@
+/*
+*********************************************************************************************************
+*                                             uC/TCP-IP
+*                                      The Embedded TCP/IP Suite
+*
+*                         (c) Copyright 2004-2015; Micrium, Inc.; Weston, FL
+*
+*                  All rights reserved.  Protected by international copyright laws.
+*
+*                  uC/TCP-IP is provided in source form to registered licensees ONLY.  It is
+*                  illegal to distribute this source code to any third party unless you receive
+*                  written permission by an authorized Micrium representative.  Knowledge of
+*                  the source code may NOT be used to develop a similar product.
+*
+*                  Please help us continue to provide the Embedded community with the finest
+*                  software available.  Your honesty is greatly appreciated.
+*
+*                  You can find our product's user manual, API reference, release notes and
+*                  more information at: https://doc.micrium.com
+*
+*                  You can contact us at: http://www.micrium.com
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                  NETWORK DEVICE CONFIGURATION FILE
+*
+*                                              TEMPLATE
+*
+* Filename : net_dev_cfg.h
+* Version  : V3.00.00
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                               MODULE
+*
+* Note(s) : (1) This network device configuration header file is protected from multiple pre-processor
+*               inclusion through use of the network module present pre-processor macro definition.
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#ifndef  NET_DEV_CFG_MODULE_PRESENT                             /* See Note #1.                                         */
+#define  NET_DEV_CFG_MODULE_PRESENT
+
+#include   <Source/net_cfg_net.h>
+
+#ifdef  NET_IF_ETHER_MODULE_EN
+#include   <IF/net_if_ether.h>
+#endif
+
+#ifdef  NET_IF_WIFI_MODULE_EN
+#include   <IF/net_if_wifi.h>
+#endif
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                    NETWORK DEVICE CONFIGURATION
+*
+* Note(s) : (1) (a) Each network device maps to a unique, developer-configured device configuration that
+*                   MUST be defined in application files, typically 'net_dev_cfg.c', & SHOULD be forward-
+*                   declared with the exact same name & type in order to be used by the application during
+*                   calls to NetIF_Add().
+*
+*               (b) Since these device configuration structures are referenced ONLY by application files,
+*                   there is NO required naming convention for these configuration structures.  However,
+*                   the following naming convention is suggested for all developer-configured network
+*                   device configuration structures :
+*
+*                       NetDev_Cfg_<Device>[_Number]
+*
+*                           where
+*                                   <Device>        Name of device or device driver
+*                                   [Number]        Network device number for each specific instance of
+*                                                       device (optional if the development board does NOT
+*                                                       support multiple instances of the specific device)
+*
+*                       Examples :
+*
+*                           NET_DEV_CFG_ETHER  NetDev_Cfg_MACB;         Ethernet configuration for MACB
+*
+*                           NET_DEV_CFG_ETHER  NetDev_Cfg_FEC_0;        Ethernet configuration for FEC #0
+*                           NET_DEV_CFG_ETHER  NetDev_Cfg_FEC_1;        Ethernet configuration for FEC #1
+*
+*                           NET_DEV_CFG_WIFI   NetDev_Cfg_RS9110N21_0;  Wireless configuration for RS9110-N-21
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#ifdef  NET_IF_ETHER_MODULE_EN
+
+extern  NET_DEV_CFG_ETHER  NetDev_AXIEthernetLite_0;
+extern  NET_PHY_CFG_ETHER  NetPhy_Cfg_Ether_0;
+
+#endif  /* NET_IF_ETHER_MODULE_EN */
+
+
+/*
+*********************************************************************************************************
+*********************************************************************************************************
+*                                             MODULE END
+*********************************************************************************************************
+*********************************************************************************************************
+*/
+
+#endif  /* NET_DEV_CFG_MODULE_PRESENT */
+

src/APP/Aufgabe3/ps7/core0/cfg/os_cfg.h

@@ -0,0 +1,145 @@
+/*
+*********************************************************************************************************
+*                                                uC/OS-II
+*                                          The Real-Time Kernel
+*                                  uC/OS-II Configuration File for V2.9x
+*
+*                               (c) Copyright 2005-2014, Micrium, Weston, FL
+*                                          All Rights Reserved
+*
+*
+* File    : OS_CFG.H
+* By      : Jean J. Labrosse
+* Version : V2.92.11
+*
+* LICENSING TERMS:
+* ---------------
+*   uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research.
+* If you plan on using  uC/OS-II  in a commercial product you need to contact Micrium to properly license
+* its use in your product. We provide ALL the source code for your convenience and to help you experience
+* uC/OS-II.   The fact that the  source is provided does  NOT  mean that you can use it without  paying a
+* licensing fee.
+*********************************************************************************************************
+*/
+
+#ifndef OS_CFG_H
+#define OS_CFG_H
+
+
+                                       /* ---------------------- MISCELLANEOUS ----------------------- */
+#define OS_APP_HOOKS_EN           1u   /* Application-defined hooks are called from the uC/OS-II hooks */
+#define OS_ARG_CHK_EN             0u   /* Enable (1) or Disable (0) argument checking                  */
+#define OS_CPU_HOOKS_EN           1u   /* uC/OS-II hooks are found in the processor port files         */
+
+#define OS_DEBUG_EN               1u   /* Enable(1) debug variables                                    */
+
+#define OS_EVENT_MULTI_EN         1u   /* Include code for OSEventPendMulti()                          */
+#define OS_EVENT_NAME_EN          1u   /* Enable names for Sem, Mutex, Mbox and Q                      */
+
+#define OS_LOWEST_PRIO           63u   /* Defines the lowest priority that can be assigned ...         */
+                                       /* ... MUST NEVER be higher than 254!                           */
+
+#define OS_MAX_EVENTS            20u   /* Max. number of event control blocks in your application      */
+#define OS_MAX_FLAGS              5u   /* Max. number of Event Flag Groups    in your application      */
+#define OS_MAX_MEM_PART           5u   /* Max. number of memory partitions                             */
+#define OS_MAX_QS                 6u   /* Max. number of queue control blocks in your application      */
+#define OS_MAX_TASKS             20u   /* Max. number of tasks in your application, MUST be >= 2       */
+
+#define OS_SCHED_LOCK_EN          1u   /* Include code for OSSchedLock() and OSSchedUnlock()           */
+
+#define OS_TICK_STEP_EN           1u   /* Enable tick stepping feature for uC/OS-View                  */
+#define OS_TICKS_PER_SEC       1000u   /* Set the number of ticks in one second                        */
+
+#define OS_TLS_TBL_SIZE           0u   /* Size of Thread-Local Storage Table                           */
+
+
+                                       /* --------------------- TASK STACK SIZE ---------------------- */
+#define OS_TASK_TMR_STK_SIZE    128u   /* Timer      task stack size (# of OS_STK wide entries)        */
+#define OS_TASK_STAT_STK_SIZE   128u   /* Statistics task stack size (# of OS_STK wide entries)        */
+#define OS_TASK_IDLE_STK_SIZE   128u   /* Idle       task stack size (# of OS_STK wide entries)        */
+
+
+                                       /* --------------------- TASK MANAGEMENT ---------------------- */
+#define OS_TASK_CHANGE_PRIO_EN    1u   /*     Include code for OSTaskChangePrio()                      */
+#define OS_TASK_CREATE_EN         1u   /*     Include code for OSTaskCreate()                          */
+#define OS_TASK_CREATE_EXT_EN     1u   /*     Include code for OSTaskCreateExt()                       */
+#define OS_TASK_DEL_EN            1u   /*     Include code for OSTaskDel()                             */
+#define OS_TASK_NAME_EN           1u   /*     Enable task names                                        */
+#define OS_TASK_PROFILE_EN        1u   /*     Include variables in OS_TCB for profiling                */
+#define OS_TASK_QUERY_EN          1u   /*     Include code for OSTaskQuery()                           */
+#define OS_TASK_REG_TBL_SIZE      1u   /*     Size of task variables array (#of INT32U entries)        */
+#define OS_TASK_STAT_EN           1u   /*     Enable (1) or Disable(0) the statistics task             */
+#define OS_TASK_STAT_STK_CHK_EN   1u   /*     Check task stacks from statistic task                    */
+#define OS_TASK_SUSPEND_EN        1u   /*     Include code for OSTaskSuspend() and OSTaskResume()      */
+#define OS_TASK_SW_HOOK_EN        1u   /*     Include code for OSTaskSwHook()                          */
+
+
+                                       /* ----------------------- EVENT FLAGS ------------------------ */
+#define OS_FLAG_EN                1u   /* Enable (1) or Disable (0) code generation for EVENT FLAGS    */
+#define OS_FLAG_ACCEPT_EN         1u   /*     Include code for OSFlagAccept()                          */
+#define OS_FLAG_DEL_EN            1u   /*     Include code for OSFlagDel()                             */
+#define OS_FLAG_NAME_EN           1u   /*     Enable names for event flag group                        */
+#define OS_FLAG_QUERY_EN          1u   /*     Include code for OSFlagQuery()                           */
+#define OS_FLAG_WAIT_CLR_EN       1u   /* Include code for Wait on Clear EVENT FLAGS                   */
+#define OS_FLAGS_NBITS           16u   /* Size in #bits of OS_FLAGS data type (8, 16 or 32)            */
+
+
+                                       /* -------------------- MESSAGE MAILBOXES --------------------- */
+#define OS_MBOX_EN                1u   /* Enable (1) or Disable (0) code generation for MAILBOXES      */
+#define OS_MBOX_ACCEPT_EN         1u   /*     Include code for OSMboxAccept()                          */
+#define OS_MBOX_DEL_EN            1u   /*     Include code for OSMboxDel()                             */
+#define OS_MBOX_PEND_ABORT_EN     1u   /*     Include code for OSMboxPendAbort()                       */
+#define OS_MBOX_POST_EN           1u   /*     Include code for OSMboxPost()                            */
+#define OS_MBOX_POST_OPT_EN       1u   /*     Include code for OSMboxPostOpt()                         */
+#define OS_MBOX_QUERY_EN          1u   /*     Include code for OSMboxQuery()                           */
+
+
+                                       /* --------------------- MEMORY MANAGEMENT -------------------- */
+#define OS_MEM_EN                 1u   /* Enable (1) or Disable (0) code generation for MEMORY MANAGER */
+#define OS_MEM_NAME_EN            1u   /*     Enable memory partition names                            */
+#define OS_MEM_QUERY_EN           1u   /*     Include code for OSMemQuery()                            */
+
+
+                                       /* ---------------- MUTUAL EXCLUSION SEMAPHORES --------------- */
+#define OS_MUTEX_EN               1u   /* Enable (1) or Disable (0) code generation for MUTEX          */
+#define OS_MUTEX_ACCEPT_EN        1u   /*     Include code for OSMutexAccept()                         */
+#define OS_MUTEX_DEL_EN           1u   /*     Include code for OSMutexDel()                            */
+#define OS_MUTEX_QUERY_EN         1u   /*     Include code for OSMutexQuery()                          */
+
+
+                                       /* ---------------------- MESSAGE QUEUES ---------------------- */
+#define OS_Q_EN                   1u   /* Enable (1) or Disable (0) code generation for QUEUES         */
+#define OS_Q_ACCEPT_EN            1u   /*     Include code for OSQAccept()                             */
+#define OS_Q_DEL_EN               1u   /*     Include code for OSQDel()                                */
+#define OS_Q_FLUSH_EN             1u   /*     Include code for OSQFlush()                              */
+#define OS_Q_PEND_ABORT_EN        1u   /*     Include code for OSQPendAbort()                          */
+#define OS_Q_POST_EN              1u   /*     Include code for OSQPost()                               */
+#define OS_Q_POST_FRONT_EN        1u   /*     Include code for OSQPostFront()                          */
+#define OS_Q_POST_OPT_EN          1u   /*     Include code for OSQPostOpt()                            */
+#define OS_Q_QUERY_EN             1u   /*     Include code for OSQQuery()                              */
+
+
+                                       /* ------------------------ SEMAPHORES ------------------------ */
+#define OS_SEM_EN                 1u   /* Enable (1) or Disable (0) code generation for SEMAPHORES     */
+#define OS_SEM_ACCEPT_EN          1u   /*    Include code for OSSemAccept()                            */
+#define OS_SEM_DEL_EN             1u   /*    Include code for OSSemDel()                               */
+#define OS_SEM_PEND_ABORT_EN      1u   /*    Include code for OSSemPendAbort()                         */
+#define OS_SEM_QUERY_EN           1u   /*    Include code for OSSemQuery()                             */
+#define OS_SEM_SET_EN             1u   /*    Include code for OSSemSet()                               */
+
+
+                                       /* --------------------- TIME MANAGEMENT ---------------------- */
+#define OS_TIME_DLY_HMSM_EN       1u   /*     Include code for OSTimeDlyHMSM()                         */
+#define OS_TIME_DLY_RESUME_EN     1u   /*     Include code for OSTimeDlyResume()                       */
+#define OS_TIME_GET_SET_EN        1u   /*     Include code for OSTimeGet() and OSTimeSet()             */
+#define OS_TIME_TICK_HOOK_EN      1u   /*     Include code for OSTimeTickHook()                        */
+
+
+                                       /* --------------------- TIMER MANAGEMENT --------------------- */
+#define OS_TMR_EN                 0u   /* Enable (1) or Disable (0) code generation for TIMERS         */
+#define OS_TMR_CFG_MAX           16u   /*     Maximum number of timers                                 */
+#define OS_TMR_CFG_NAME_EN        1u   /*     Determine timer names                                    */
+#define OS_TMR_CFG_WHEEL_SIZE     7u   /*     Size of timer wheel (#Spokes)                            */
+#define OS_TMR_CFG_TICKS_PER_SEC 10u   /*     Rate at which timer management task runs (Hz)            */
+
+#endif

src/APP/Aufgabe3/ps7/core0/cfg/pid.h

@@ -0,0 +1,18 @@
+/*
+ * pid.h
+ *
+ *  Created on: Jan 28, 2019
+ *      Author: laurenzb
+ */
+
+#ifndef SRC_APP_AUFGABE7_PS7_CORE0_CFG_PID_H_
+#define SRC_APP_AUFGABE7_PS7_CORE0_CFG_PID_H_
+
+unsigned int pid_Init(void *pdata);
+int16_t pid_Constrain(int16_t value, int16_t lowerBorder, int16_t higherBorder);
+unsigned int pid_Task(void *pdata);
+int16_t map(int16_t x, int16_t in_min, int16_t in_max, int16_t out_min, int16_t out_max);
+
+
+
+#endif /* SRC_APP_AUFGABE7_PS7_CORE0_CFG_PID_H_ */

src/APP/Aufgabe3/ps7/core0/cfg/shell_cfg.h

@@ -0,0 +1,96 @@
+/*
+*********************************************************************************************************
+*                                              uC/Shell
+*                                            Shell Utility
+*
+*                          (c) Copyright 2007-2013; Micrium, Inc.; Weston, FL
+*
+*               All rights reserved.  Protected by international copyright laws.
+*
+*               uC/Shell is provided in source form to registered licensees ONLY.  It is
+*               illegal to distribute this source code to any third party unless you receive
+*               written permission by an authorized Micrium representative.  Knowledge of
+*               the source code may NOT be used to develop a similar product.
+*
+*               Please help us continue to provide the Embedded community with the finest
+*               software available.  Your honesty is greatly appreciated.
+*
+*               You can contact us at www.micrium.com.
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                  SHELL UTILITY CONFIGURATION FILE
+*
+*                                              TEMPLATE
+*
+* Filename      : shell_cfg.h
+* Version       : V1.03.01
+* Programmer(s) : SR
+*                 FBJ
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                                 MODULE
+*********************************************************************************************************
+*/
+
+#ifndef  SHELL_CFG_H
+#define  SHELL_CFG_H
+
+
+/*
+*********************************************************************************************************
+*                                                 SHELL
+*
+* Note(s) : (1) Defines the size of the table used to hold the various modules' command tables.  Command
+*               tables are added using the Shell_CmdTblAdd() function.  Once the table is full, it is not
+*               possible to add any more unless Shell_CmdTblRem() is first called.
+*
+*           (2) Defines the maximum number or argument(s) a command may pass on the string holding the
+*               complete command.  The minimum value is 1.
+*
+*           (3) Defines the maximum length for module command name, including the NULL character.
+*********************************************************************************************************
+*/
+
+#define  SHELL_CFG_CMD_TBL_SIZE                            3    /* Cfg Shell cmd tbl size  (see Note #1).               */
+#define  SHELL_CFG_CMD_ARG_NBR_MAX                         5    /* Cfg cmd max nbr of arg  (see Note #2).               */
+
+#define  SHELL_CFG_MODULE_CMD_NAME_LEN_MAX                 6    /* Cfg module cmd name len (See Note #3).               */
+
+
+/*
+*********************************************************************************************************
+*                                                TRACING
+*********************************************************************************************************
+*/
+
+#ifndef  TRACE_LEVEL_OFF
+#define  TRACE_LEVEL_OFF                                  0u
+#endif
+
+#ifndef  TRACE_LEVEL_INFO
+#define  TRACE_LEVEL_INFO                                 1u
+#endif
+
+#ifndef  TRACE_LEVEL_DBG
+#define  TRACE_LEVEL_DBG                                  2u
+#endif
+
+#define  SHELL_TRACE_LEVEL                   TRACE_LEVEL_OFF
+#define  SHELL_TRACE                                  printf
+
+
+/*
+*********************************************************************************************************
+*                                          MODULE END
+*********************************************************************************************************
+*/
+
+#endif

src/APP/Aufgabe3/ps7/core0/cfg/terminal_cfg.h

@@ -0,0 +1,70 @@
+/*
+*********************************************************************************************************
+*                                               uC/Shell
+*                                            Shell utility
+*
+*                             (c) Copyright 2007-2013; Micrium, Inc.; Weston, FL
+*
+*                   All rights reserved.  Protected by international copyright laws.
+*                   Knowledge of the source code may not be used to write a similar
+*                   product.  This file may only be used in accordance with a license
+*                   and should not be redistributed in any way.
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*
+*                                               TERMINAL
+*
+*                                      CONFIGURATION TEMPLATE FILE
+*
+* Filename      : terminal_cfg.h
+* Version       : V1.03.01
+* Programmer(s) : BAN
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                                           TASKS PRIORITIES
+*********************************************************************************************************
+*/
+
+#define  TERMINAL_OS_CFG_TASK_PRIO                        16u
+
+
+/*
+*********************************************************************************************************
+*                                              STACK SIZES
+*                             Size of the task stacks (# of OS_STK entries)
+*********************************************************************************************************
+*/
+
+#define  TERMINAL_OS_CFG_TASK_STK_SIZE                  1024u
+
+
+/*
+*********************************************************************************************************
+*                                               TERMINAL
+*
+* Note(s) : (1) Defines the maximum length of a command entered on the terminal, in characters.
+*
+*           (2) Defines the maximum path length of the Current Working Directory (CWD).
+*
+*           (3) Enables/disables command history.
+*
+*           (4) Defines the number of items to hold in the command history.
+*
+*           (5) Defines the length of a item in the command history.  If a command is entered into the
+*               terminal that exceeds this length, then only the first characters, up to this number of
+*               characters, will be copied into the command history.
+*********************************************************************************************************
+*/
+
+#define  TERMINAL_CFG_MAX_CMD_LEN                        260u   /* Cfg max cmd  len         (see Note #1).              */
+#define  TERMINAL_CFG_MAX_PATH_LEN                       260u   /* Cfg max path len         (see Note #2).              */
+
+#define  TERMINAL_CFG_HISTORY_EN                 DEF_ENABLED    /* En/dis history           (see Note #3).              */
+#define  TERMINAL_CFG_HISTORY_ITEMS_NBR                   16u   /* Cfg nbr history items    (see Note #4).              */
+#define  TERMINAL_CFG_HISTORY_ITEM_LEN                    64u   /* Cfg history item len     (see Note #5).              */

src/APP/Aufgabe3/ps7/core0/cfg/ttc_timer.h

@@ -0,0 +1,15 @@
+/*
+ * ttc_timer.h
+ *
+ *  Created on: Nov 13, 2018
+ *      Author: laurenzb
+ */
+
+#include <stdint.h>
+
+#ifndef SRC_APP_AUFGABE3_PS7_CORE0_CFG_TTC_TIMER_H_
+#define SRC_APP_AUFGABE3_PS7_CORE0_CFG_TTC_TIMER_H_
+
+
+
+#endif /* SRC_APP_AUFGABE3_PS7_CORE0_CFG_TTC_TIMER_H_ */

src/APP/Aufgabe3/ps7/core0/cfg/xparameters.h

@@ -0,0 +1,704 @@
+/******************************************************************/
+
+/* Definition for CPU ID */
+#define XPAR_CPU_ID 0
+
+/* Definitions for peripheral PS7_CORTEXA9_0 */
+#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
+#define XPAR_PS7_CORTEXA9_1_CPU_CLK_FREQ_HZ XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_CORTEXA9_0 */
+#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
+#define XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+
+/******************************************************************/
+
+#undef DEF_DISABLED
+#undef DEF_ENABLED
+#define DEF_ENABLED 1
+#define DEF_DISABLED 0
+
+#include "../../../../Aufgabe3/ps7/core0/cfg/xparameters_ps.h"
+
+
+
+/******************************************************************/
+
+/* Definitions for driver BRAM */
+#define XPAR_XBRAM_NUM_INSTANCES 1
+
+/* Definitions for peripheral AXI_BRAM_CTRL_0 */
+#define XPAR_AXI_BRAM_CTRL_0_DEVICE_ID 0
+#define XPAR_AXI_BRAM_CTRL_0_DATA_WIDTH 32
+#define XPAR_AXI_BRAM_CTRL_0_ECC 0
+#define XPAR_AXI_BRAM_CTRL_0_FAULT_INJECT 0
+#define XPAR_AXI_BRAM_CTRL_0_CE_FAILING_REGISTERS 0
+#define XPAR_AXI_BRAM_CTRL_0_UE_FAILING_REGISTERS 0
+#define XPAR_AXI_BRAM_CTRL_0_ECC_STATUS_REGISTERS 0
+#define XPAR_AXI_BRAM_CTRL_0_CE_COUNTER_WIDTH 0
+#define XPAR_AXI_BRAM_CTRL_0_ECC_ONOFF_REGISTER 0
+#define XPAR_AXI_BRAM_CTRL_0_ECC_ONOFF_RESET_VALUE 0
+#define XPAR_AXI_BRAM_CTRL_0_WRITE_ACCESS 0
+#define XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR 0x40000000
+#define XPAR_AXI_BRAM_CTRL_0_S_AXI_HIGHADDR 0x40001FFF
+#define XPAR_AXI_BRAM_CTRL_0_S_AXI_CTRL_BASEADDR 0xFFFFFFFF
+#define XPAR_AXI_BRAM_CTRL_0_S_AXI_CTRL_HIGHADDR 0xFFFFFFFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral AXI_BRAM_CTRL_0 */
+#define XPAR_BRAM_0_DEVICE_ID XPAR_AXI_BRAM_CTRL_0_DEVICE_ID
+#define XPAR_BRAM_0_DATA_WIDTH 32
+#define XPAR_BRAM_0_ECC 0
+#define XPAR_BRAM_0_FAULT_INJECT 0
+#define XPAR_BRAM_0_CE_FAILING_REGISTERS 0
+#define XPAR_BRAM_0_UE_FAILING_REGISTERS 0
+#define XPAR_BRAM_0_ECC_STATUS_REGISTERS 0
+#define XPAR_BRAM_0_CE_COUNTER_WIDTH 0
+#define XPAR_BRAM_0_ECC_ONOFF_REGISTER 0
+#define XPAR_BRAM_0_ECC_ONOFF_RESET_VALUE 0
+#define XPAR_BRAM_0_WRITE_ACCESS 0
+#define XPAR_BRAM_0_BASEADDR 0x40000000
+#define XPAR_BRAM_0_HIGHADDR 0x40001FFF
+
+
+/******************************************************************/
+
+
+/* Definitions for peripheral PS7_DDR_0 */
+#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
+#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver DEVCFG */
+#define XPAR_XDCFG_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_DEV_CFG_0 */
+#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0
+#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000
+#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_DEV_CFG_0 */
+#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
+#define XPAR_XDCFG_0_BASEADDR 0xF8007000
+#define XPAR_XDCFG_0_HIGHADDR 0xF80070FF
+
+
+/******************************************************************/
+
+/* Definitions for driver DMAPS */
+#define XPAR_XDMAPS_NUM_INSTANCES 2
+
+/* Definitions for peripheral PS7_DMA_NS */
+#define XPAR_PS7_DMA_NS_DEVICE_ID 0
+#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
+#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF
+
+
+/* Definitions for peripheral PS7_DMA_S */
+#define XPAR_PS7_DMA_S_DEVICE_ID 1
+#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
+#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_DMA_NS */
+#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
+#define XPAR_XDMAPS_0_BASEADDR 0xF8004000
+#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF
+
+/* Canonical definitions for peripheral PS7_DMA_S */
+#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
+#define XPAR_XDMAPS_1_BASEADDR 0xF8003000
+#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF
+
+
+/******************************************************************/
+
+
+/* Definitions for peripheral PS7_AFI_0 */
+#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
+#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
+
+
+/* Definitions for peripheral PS7_AFI_1 */
+#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000
+#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF
+
+
+/* Definitions for peripheral PS7_AFI_2 */
+#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000
+#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF
+
+
+/* Definitions for peripheral PS7_AFI_3 */
+#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000
+#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
+
+
+/* Definitions for peripheral PS7_DDRC_0 */
+#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
+#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
+
+
+/* Definitions for peripheral PS7_GLOBALTIMER_0 */
+#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200
+#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF
+
+
+/* Definitions for peripheral PS7_GPV_0 */
+#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000
+#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF
+
+
+/* Definitions for peripheral PS7_INTC_DIST_0 */
+#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000
+#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF
+
+
+/* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
+#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
+#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
+
+
+/* Definitions for peripheral PS7_OCMC_0 */
+#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000
+#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF
+
+
+/* Definitions for peripheral PS7_PL310_0 */
+#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000
+#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF
+
+
+/* Definitions for peripheral PS7_PMU_0 */
+#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000
+#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF
+#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000
+#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF
+
+
+/* Definitions for peripheral PS7_QSPI_LINEAR_0 */
+#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
+#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFDFFFFFF
+
+
+/* Definitions for peripheral PS7_RAM_0 */
+#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
+#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
+
+
+/* Definitions for peripheral PS7_RAM_1 */
+#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000
+#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
+
+
+/* Definitions for peripheral PS7_SLCR_0 */
+#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
+#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF
+
+
+/******************************************************************/
+
+/* Definitions for driver GPIO */
+#define XPAR_XGPIO_NUM_INSTANCES 1
+
+/* Definitions for peripheral AXI_GPIO_0 */
+#define XPAR_AXI_GPIO_0_BASEADDR 0x41200000
+#define XPAR_AXI_GPIO_0_HIGHADDR 0x4120FFFF
+#define XPAR_AXI_GPIO_0_DEVICE_ID 0
+#define XPAR_AXI_GPIO_0_INTERRUPT_PRESENT 0
+#define XPAR_AXI_GPIO_0_IS_DUAL 0
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral AXI_GPIO_0 */
+#define XPAR_GPIO_0_BASEADDR 0x41200000
+#define XPAR_GPIO_0_HIGHADDR 0x4120FFFF
+#define XPAR_GPIO_0_DEVICE_ID XPAR_AXI_GPIO_0_DEVICE_ID
+#define XPAR_GPIO_0_INTERRUPT_PRESENT 0
+#define XPAR_GPIO_0_IS_DUAL 0
+
+
+/******************************************************************/
+
+/* Definitions for driver GPIOPS */
+#define XPAR_XGPIOPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_GPIO_0 */
+#define XPAR_PS7_GPIO_0_DEVICE_ID 0
+#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
+#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_GPIO_0 */
+#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
+#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
+#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
+
+
+/******************************************************************/
+
+///* Definitions for driver IICPS */
+//#define XPAR_XIICPS_NUM_INSTANCES 1
+//
+///* Definitions for peripheral PS7_I2C_0 */
+//#define XPAR_PS7_I2C_0_DEVICE_ID 0
+//#define XPAR_PS7_I2C_0_BASEADDR 0xE0004000
+//#define XPAR_PS7_I2C_0_HIGHADDR 0xE0004FFF
+//#define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 111111115
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_I2C_0 */
+#define XPAR_XIICPS_0_DEVICE_ID XPAR_PS7_I2C_0_DEVICE_ID
+#define XPAR_XIICPS_0_BASEADDR 0xE0004000
+#define XPAR_XIICPS_0_HIGHADDR 0xE0004FFF
+#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 111111115
+
+
+/******************************************************************/
+
+/* Definitions for driver QSPIPS */
+#define XPAR_XQSPIPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_QSPI_0 */
+#define XPAR_PS7_QSPI_0_DEVICE_ID 0
+#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000
+#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
+#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000
+#define XPAR_PS7_QSPI_0_QSPI_MODE 2
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_QSPI_0 */
+#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID
+#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000
+#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
+#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000
+#define XPAR_XQSPIPS_0_QSPI_MODE 2
+
+
+/******************************************************************/
+
+/* Definitions for driver SCUWDT */
+#define XPAR_XSCUWDT_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SCUWDT_0 */
+#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
+#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
+#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_SCUWDT_0 */
+#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
+#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
+#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
+
+
+/******************************************************************/
+
+/* Definitions for driver UCOS_EMACPS */
+#define XPAR_UCOS_EMACPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_ETHERNET_0 */
+#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0
+#define XPAR_PS7_ETHERNET_0_BASEADDR 0x00000000
+#define XPAR_PS7_ETHERNET_0_HIGHADDR 0x00000000
+#define XPAR_PS7_ETHERNET_0_CLOCK_FREQ_HZ 0
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_ETHERNET_0 */
+#define XPAR_UCOS_EMACPS_0_NUM_INSTANCES 0
+#define XPAR_UCOS_EMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID
+#define XPAR_UCOS_EMACPS_0_BASEADDR 0x00000000
+#define XPAR_UCOS_EMACPS_0_HIGHADDR 0x00000000
+#define XPAR_UCOS_EMACPS_0_CLOCK_FREQ_HZ 0
+
+
+/******************************************************************/
+
+/* Definitions for driver UCOS_L2CACHEC */
+#define XPAR_UCOS_L2CACHEC_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_L2CACHEC_0 */
+#define XPAR_PS7_L2CACHEC_0_DEVICE_ID 0
+#define XPAR_PS7_L2CACHEC_0_BASEADDR 0xF8F02000
+#define XPAR_PS7_L2CACHEC_0_HIGHADDR 0xF8F02FFF
+
+
+/******************************************************************/
+
+/* Definitions for driver UCOS_SCUC */
+#define XPAR_UCOS_L2CACHEC_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SCUC_0 */
+#define XPAR_PS7_SCUC_0_DEVICE_ID 0
+#define XPAR_PS7_SCUC_0_BASEADDR 0xF8F00000
+#define XPAR_PS7_SCUC_0_HIGHADDR 0xF8F000FC
+
+
+/******************************************************************/
+
+
+/***Definitions for Core_nIRQ/nFIQ interrupts ****/
+/* Definitions for driver UCOS_SCUGIC */
+#define XPAR_XSCUGIC_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SCUGIC_0 */
+#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0
+#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100
+#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FF
+#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_SCUGIC_0 */
+#define XPAR_SCUGIC_0_DEVICE_ID 0
+#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100
+#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FF
+#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000
+
+
+/******************************************************************/
+
+/* Definitions for driver UCOS_SCUTIMER */
+#define XPAR_UCOS_SCUC_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SCUTIMER_0 */
+#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
+#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
+#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F
+
+
+/******************************************************************/
+
+/* Definitions for driver UCOS_SDPS */
+#define XPAR_UCOS_SDPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_SD_0 */
+#define XPAR_PS7_SD_0_DEVICE_ID 0
+#define XPAR_PS7_SD_0_BASEADDR 0xE0100000
+#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
+#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_SD_0 */
+#define XPAR_UCOS_SDPS_0_NUM_INSTANCES 0
+#define XPAR_UCOS_SDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID
+#define XPAR_UCOS_SDPS_0_BASEADDR 0xE0100000
+#define XPAR_UCOS_SDPS_0_HIGHADDR 0xE0100FFF
+#define XPAR_UCOS_SDPS_0_SDIO_CLK_FREQ_HZ 50000000
+
+
+/******************************************************************/
+
+///* Definitions for driver UCOS_TTCPS */
+//#define XPAR_UCOS_TTCPS_NUM_INSTANCES 3
+//
+///* Definitions for peripheral PS7_TTC_0 */
+//#define XPAR_PS7_TTC_0_DEVICE_ID 0
+//#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000
+//#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115
+//#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0
+//#define XPAR_PS7_TTC_1_DEVICE_ID 1
+//#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004
+//#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115
+//#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0
+//#define XPAR_PS7_TTC_2_DEVICE_ID 2
+//#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008
+//#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115
+//#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0
+
+
+/******************************************************************/
+
+/* Definitions for driver UCOS_UARTPS */
+#define XPAR_UCOS_UARTPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_UART_1 */
+#define XPAR_PS7_UART_1_DEVICE_ID 0
+#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
+#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
+#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 50000000
+#define XPAR_PS7_UART_1_HAS_MODEM 0
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_UART_1 */
+#define XPAR_UCOS_UARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
+#define XPAR_UCOS_UARTPS_0_BASEADDR 0xE0001000
+#define XPAR_UCOS_UARTPS_0_HIGHADDR 0xE0001FFF
+#define XPAR_UCOS_UARTPS_0_UART_CLK_FREQ_HZ 50000000
+#define XPAR_UCOS_UARTPS_0_HAS_MODEM 0
+
+
+/******************************************************************/
+
+/* Definitions for driver UCOS_USBPS */
+#define XPAR_UCOS_USBPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_USB_0 */
+#define XPAR_PS7_USB_0_DEVICE_ID 0
+#define XPAR_PS7_USB_0_BASEADDR 0xE0002000
+#define XPAR_PS7_USB_0_HIGHADDR 0xE0002FFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_USB_0 */
+#define XPAR_UCOS_USBPS_0_DEVICE_ID XPAR_PS7_USB_0_DEVICE_ID
+#define XPAR_UCOS_USBPS_0_BASEADDR 0xE0002000
+#define XPAR_UCOS_USBPS_0_HIGHADDR 0xE0002FFF
+
+
+/******************************************************************/
+
+/* Definitions for driver XADCPS */
+#define XPAR_XADCPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_XADC_0 */
+#define XPAR_PS7_XADC_0_DEVICE_ID 0
+#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100
+#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_XADC_0 */
+#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
+#define XPAR_XADCPS_0_BASEADDR 0xF8007100
+#define XPAR_XADCPS_0_HIGHADDR 0xF8007120
+
+
+/******************************************************************/
+
+
+//UCOS STDOUT
+#define UCOS_STDOUT_DRIVER UCOS_UART_PS7_UART
+#define UCOS_STDOUT_DEVICE_ID 0
+#define STDOUT_BASEADDRESS
+
+//UCOS Ethernet
+#define UCOS_ETHERNET_DRIVER UCOS_ETHERNET_EMACPS
+
+//UCOS TASK PARAMETERS
+#define UCOS_START_TASK_PRIO 5
+#define UCOS_START_TASK_STACK_SIZE 784
+#define UCOS_START_DEBUG_TRACE DEF_ENABLED
+#define NET_TASK_CFG_RX_PRIO 30
+#define NET_TASK_CFG_RX_STACK_SIZE 3072
+#define NET_TASK_CFG_TXDEALLOC_PRIO 6
+#define NET_TASK_CFG_TXDEALLOC_STACK_SIZE 2048
+#define NET_TASK_CFG_TMR_PRIO 18
+#define NET_TASK_CFG_TMR_STACK_SIZE 2048
+#define HTTPc_OS_CFG_TASK_PRIO 20
+#define HTTPc_OS_CFG_TASK_STK_SIZE 2048
+#define UCOS_HTTPc_OS_CFG_TASK_DELAY 1
+#define UCOS_HTTPc_OS_CFG_MSG_Q_SIZE 5
+#define UCOS_HTTPc_OS_CFG_TIMEOUT 2000
+#define UCOS_HTTPc_OS_CFG_INACTIVITY_TIMEOUT 30
+
+#define UCOS_AMP_MASTER DEF_ENABLED
+
+
+#define UCOS_CFG_INIT_CAN DEF_ENABLED
+#define UCOS_CFG_INIT_NET DEF_ENABLED
+#define UCOS_CFG_INIT_FS DEF_DISABLED
+#define UCOS_CFG_INIT_OPENAMP DEF_DISABLED
+#define UCOS_CFG_INIT_USBD DEF_DISABLED
+#define UCOS_CFG_INIT_USBH DEF_DISABLED
+
+
+#define UCOS_ETHERNET_ADDRESS "10.10.110.2"
+#define UCOS_ETHERNET_GATEWAY "10.10.110.1"
+#define UCOS_ETHERNET_SUBMASK "255.255.255.0"
+#define UCOS_ETHERNET_DHCP DEF_ENABLED
+
+
+#define UCOS_IF_RX_BUF_NBR 12
+#define UCOS_IF_TX_LARGE_BUF_NBR 8
+#define UCOS_IF_TX_SMALL_BUF_NBR 8
+#define UCOS_IF_RX_DESC_NBR 0
+#define UCOS_IF_TX_DESC_NBR 0
+#define UCOS_IF_DEDIC_MEM_ADDR 0
+#define UCOS_IF_DEDIC_MEM_SIZE 0
+#define UCOS_IF_HW_ADDR "50:E5:49:E6:8D:28"
+
+
+#define UCOS_PHY_BUS_ADDR 255
+#define UCOS_PHY_BUS_MODE UCOS_NET_PHY_BUS_MODE_GMII
+#define UCOS_PHY_TYPE UCOS_NET_PHY_TYPE_INT
+#define UCOS_PHY_SPEED UCOS_NET_PHY_SPD_AUTO
+#define UCOS_PHY_DUPLEX UCOS_NET_PHY_DUPLEX_AUTO
+
+
+#define UCOS_USB_DRIVER UCOS_USB_NONE
+#define UCOS_USB_DEVICE_ID 0
+#define UCOS_USB_TYPE UCOS_USB_TYPE_DEVICE
+
+
+#define UCOS_RAMDISK_EN DEF_DISABLED
+#define UCOS_RAMDISK_SIZE 128
+#define UCOS_RAMDISK_SECTOR_SIZE 512
+#define UCOS_RAMDISK_BASE_ADDRESS 0
+
+
+#define UCOS_SDCARD_EN DEF_DISABLED
+
+
+#define XPAR_PS7_ETHERNET_0_INT_SOURCE 54
+#define XPAR_PS7_SD_0_INT_SOURCE 56
+#define XPAR_PS7_UART_1_INT_SOURCE 82
+#define XPAR_PS7_USB_0_INT_SOURCE 53
+
+#define UCOS_ZYNQ_CONFIG_MMU DEF_DISABLED
+#define UCOS_ZYNQ_ENABLE_MMU DEF_DISABLED
+#define UCOS_ZYNQ_CONFIG_CACHES DEF_DISABLED
+#define UCOS_ZYNQ_ENABLE_CACHES DEF_DISABLED
+#define UCOS_ZYNQ_ENABLE_OPTIMS DEF_DISABLED
+#define ZYNQ_ENABLE_EARLY_L1_I_EN DEF_DISABLED
+#define ZYNQ_ENABLE_EARLY_L1_D_EN DEF_DISABLED
+#define UCOS_CPU_TYPE UCOS_CPU_TYPE_PS7
+
+//Parameters added by Kai Gemlau
+#define UCOS_SMP_ENABLE DEF_DISABLED
+
+/******************************************************************/
+
+/* Definitions for driver TTCPS */
+#define XPAR_XTTCPS_NUM_INSTANCES 3U
+
+/* Definitions for peripheral PS7_TTC_0 */
+#define XPAR_PS7_TTC_0_DEVICE_ID 0U
+#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000U
+#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115U
+#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0U
+#define XPAR_PS7_TTC_1_DEVICE_ID 1U
+#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004U
+#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115U
+#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0U
+#define XPAR_PS7_TTC_2_DEVICE_ID 2U
+#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008U
+#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115U
+#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0U
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_TTC_0 */
+#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PS7_TTC_0_DEVICE_ID
+#define XPAR_XTTCPS_0_BASEADDR 0xF8001000U
+#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 111111115U
+#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0U
+
+#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PS7_TTC_1_DEVICE_ID
+#define XPAR_XTTCPS_1_BASEADDR 0xF8001004U
+#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 111111115U
+#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0U
+
+#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PS7_TTC_2_DEVICE_ID
+#define XPAR_XTTCPS_2_BASEADDR 0xF8001008U
+#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 111111115U
+#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0U
+
+
+/******************************************************************/
+/* Definitions for driver GPIOPS */
+#define XPAR_XGPIOPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_GPIO_0 */
+#define XPAR_PS7_GPIO_0_DEVICE_ID 0
+#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
+#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_GPIO_0 */
+#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
+#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
+#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver IICPS */
+#define XPAR_XIICPS_NUM_INSTANCES 2
+
+/* Definitions for peripheral PS7_I2C_0 */
+#define XPAR_PS7_I2C_0_DEVICE_ID 0
+#define XPAR_PS7_I2C_0_BASEADDR 0xE0004000
+#define XPAR_PS7_I2C_0_HIGHADDR 0xE0004FFF
+#define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 111111115
+
+
+/* Definitions for peripheral PS7_I2C_1 */
+#define XPAR_PS7_I2C_1_DEVICE_ID 1
+#define XPAR_PS7_I2C_1_BASEADDR 0xE0005000
+#define XPAR_PS7_I2C_1_HIGHADDR 0xE0005FFF
+#define XPAR_PS7_I2C_1_I2C_CLK_FREQ_HZ 111111115
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_I2C_0 */
+#define XPAR_XIICPS_0_DEVICE_ID XPAR_PS7_I2C_0_DEVICE_ID
+#define XPAR_XIICPS_0_BASEADDR 0xE0004000
+#define XPAR_XIICPS_0_HIGHADDR 0xE0004FFF
+#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 111111115
+
+/* Canonical definitions for peripheral PS7_I2C_1 */
+#define XPAR_XIICPS_1_DEVICE_ID XPAR_PS7_I2C_1_DEVICE_ID
+#define XPAR_XIICPS_1_BASEADDR 0xE0005000
+#define XPAR_XIICPS_1_HIGHADDR 0xE0005FFF
+#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 111111115
+
+
+/******************************************************************/
+
+/* Definitions for driver UARTPS */
+#define XPAR_XUARTPS_NUM_INSTANCES 1
+
+/* Definitions for peripheral PS7_UART_1 */
+#define XPAR_PS7_UART_1_DEVICE_ID 0
+#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
+#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
+#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 50000000
+#define XPAR_PS7_UART_1_HAS_MODEM 0
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PS7_UART_1 */
+#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
+#define XPAR_XUARTPS_0_BASEADDR 0xE0001000
+#define XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF
+#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 50000000
+#define XPAR_XUARTPS_0_HAS_MODEM 0
+
+
+/******************************************************************/

src/APP/Aufgabe3/ps7/core0/cfg/xparameters_ps.h

@@ -0,0 +1,325 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xparameters_ps.h
+*
+* This file contains the address definitions for the hard peripherals
+* attached to the ARM Cortex A9 core.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 02/01/10 Initial version
+* 3.04a sdm     02/02/12 Removed some of the defines as they are being generated through
+*                        driver tcl
+* 5.0	pkp		01/16/15 Added interrupt ID definition of ttc for TEST APP
+* </pre>
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XPARAMETERS_PS_H_
+#define _XPARAMETERS_PS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock
+ */
+
+/* Canonical definitions for DDR MEMORY */
+#define XPAR_DDR_MEM_BASEADDR		0x00000000U
+#define XPAR_DDR_MEM_HIGHADDR		0x3FFFFFFFU
+
+/* Canonical definitions for Interrupts  */
+#define XPAR_XUARTPS_0_INTR		XPS_UART0_INT_ID
+#define XPAR_XUARTPS_1_INTR		XPS_UART1_INT_ID
+#define XPAR_XUSBPS_0_INTR		XPS_USB0_INT_ID
+#define XPAR_XUSBPS_1_INTR		XPS_USB1_INT_ID
+#define XPAR_XIICPS_0_INTR		XPS_I2C0_INT_ID
+#define XPAR_XIICPS_1_INTR		XPS_I2C1_INT_ID
+#define XPAR_XSPIPS_0_INTR		XPS_SPI0_INT_ID
+#define XPAR_XSPIPS_1_INTR		XPS_SPI1_INT_ID
+#define XPAR_XCANPS_0_INTR		XPS_CAN0_INT_ID
+#define XPAR_XCANPS_1_INTR		XPS_CAN1_INT_ID
+#define XPAR_XGPIOPS_0_INTR		XPS_GPIO_INT_ID
+#define XPAR_XEMACPS_0_INTR		XPS_GEM0_INT_ID
+#define XPAR_XEMACPS_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
+#define XPAR_XEMACPS_1_INTR		XPS_GEM1_INT_ID
+#define XPAR_XEMACPS_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
+#define XPAR_XSDIOPS_0_INTR		XPS_SDIO0_INT_ID
+#define XPAR_XQSPIPS_0_INTR		XPS_QSPI_INT_ID
+#define XPAR_XSDIOPS_1_INTR		XPS_SDIO1_INT_ID
+#define XPAR_XWDTPS_0_INTR		XPS_WDT_INT_ID
+#define XPAR_XDCFG_0_INTR		XPS_DVC_INT_ID
+#define XPAR_SCUTIMER_INTR		XPS_SCU_TMR_INT_ID
+#define XPAR_SCUWDT_INTR		XPS_SCU_WDT_INT_ID
+#define XPAR_XTTCPS_0_INTR		XPS_TTC0_0_INT_ID
+#define XPAR_XTTCPS_1_INTR		XPS_TTC0_1_INT_ID
+#define XPAR_XTTCPS_2_INTR		XPS_TTC0_2_INT_ID
+#define XPAR_XTTCPS_3_INTR		XPS_TTC1_0_INT_ID
+#define XPAR_XTTCPS_4_INTR		XPS_TTC1_1_INT_ID
+#define XPAR_XTTCPS_5_INTR		XPS_TTC1_2_INT_ID
+#define XPAR_XDMAPS_0_FAULT_INTR	XPS_DMA0_ABORT_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_0	XPS_DMA0_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_1	XPS_DMA1_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_2	XPS_DMA2_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_3	XPS_DMA3_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_4	XPS_DMA4_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_5	XPS_DMA5_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_6	XPS_DMA6_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_7	XPS_DMA7_INT_ID
+
+
+#define XPAR_XQSPIPS_0_LINEAR_BASEADDR	XPS_QSPI_LINEAR_BASEADDR
+#define XPAR_XPARPORTPS_CTRL_BASEADDR	XPS_PARPORT_CRTL_BASEADDR
+
+
+
+/* Canonical definitions for DMAC */
+
+
+/* Canonical definitions for WDT */
+
+/* Canonical definitions for SLCR */
+#define XPAR_XSLCR_NUM_INSTANCES	1U
+#define XPAR_XSLCR_0_DEVICE_ID		0U
+#define XPAR_XSLCR_0_BASEADDR		XPS_SYS_CTRL_BASEADDR
+
+/* Canonical definitions for SCU GIC */
+#define XPAR_SCUGIC_NUM_INSTANCES	1U
+#define XPAR_SCUGIC_SINGLE_DEVICE_ID	0U
+#define XPAR_SCUGIC_CPU_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00000100U)
+#define XPAR_SCUGIC_DIST_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00001000U)
+#define XPAR_SCUGIC_ACK_BEFORE		0U
+
+/* Canonical definitions for Global Timer */
+#define XPAR_GLOBAL_TMR_NUM_INSTANCES	1U
+#define XPAR_GLOBAL_TMR_DEVICE_ID	0U
+#define XPAR_GLOBAL_TMR_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00000200U)
+#define XPAR_GLOBAL_TMR_INTR		XPS_GLOBAL_TMR_INT_ID
+
+
+/* Xilinx Parallel Flash Library (XilFlash) User Settings */
+#define XPAR_AXI_EMC
+
+
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock. These have been put for bacwards compatibilty
+ */
+
+#define XPS_PERIPHERAL_BASEADDR		0xE0000000U
+#define XPS_UART0_BASEADDR		0xE0000000U
+#define XPS_UART1_BASEADDR		0xE0001000U
+#define XPS_USB0_BASEADDR		0xE0002000U
+#define XPS_USB1_BASEADDR		0xE0003000U
+#define XPS_I2C0_BASEADDR		0xE0004000U
+#define XPS_I2C1_BASEADDR		0xE0005000U
+#define XPS_SPI0_BASEADDR		0xE0006000U
+#define XPS_SPI1_BASEADDR		0xE0007000U
+#define XPS_CAN0_BASEADDR		0xE0008000U
+#define XPS_CAN1_BASEADDR		0xE0009000U
+#define XPS_GPIO_BASEADDR		0xE000A000U
+#define XPS_GEM0_BASEADDR		0xE000B000U
+#define XPS_GEM1_BASEADDR		0xE000C000U
+#define XPS_QSPI_BASEADDR		0xE000D000U
+#define XPS_PARPORT_CRTL_BASEADDR	0xE000E000U
+#define XPS_SDIO0_BASEADDR		0xE0100000U
+#define XPS_SDIO1_BASEADDR		0xE0101000U
+#define XPS_IOU_BUS_CFG_BASEADDR	0xE0200000U
+#define XPS_NAND_BASEADDR		0xE1000000U
+#define XPS_PARPORT0_BASEADDR		0xE2000000U
+#define XPS_PARPORT1_BASEADDR		0xE4000000U
+#define XPS_QSPI_LINEAR_BASEADDR	0xFC000000U
+#define XPS_SYS_CTRL_BASEADDR		0xF8000000U	/* AKA SLCR */
+#define XPS_TTC0_BASEADDR		0xF8001000U
+#define XPS_TTC1_BASEADDR		0xF8002000U
+#define XPS_DMAC0_SEC_BASEADDR		0xF8003000U
+#define XPS_DMAC0_NON_SEC_BASEADDR	0xF8004000U
+#define XPS_WDT_BASEADDR		0xF8005000U
+#define XPS_DDR_CTRL_BASEADDR		0xF8006000U
+#define XPS_DEV_CFG_APB_BASEADDR	0xF8007000U
+#define XPS_AFI0_BASEADDR		0xF8008000U
+#define XPS_AFI1_BASEADDR		0xF8009000U
+#define XPS_AFI2_BASEADDR		0xF800A000U
+#define XPS_AFI3_BASEADDR		0xF800B000U
+#define XPS_OCM_BASEADDR		0xF800C000U
+#define XPS_EFUSE_BASEADDR		0xF800D000U
+#define XPS_CORESIGHT_BASEADDR		0xF8800000U
+#define XPS_TOP_BUS_CFG_BASEADDR	0xF8900000U
+#define XPS_SCU_PERIPH_BASE		0xF8F00000U
+#define XPS_L2CC_BASEADDR		0xF8F02000U
+#define XPS_SAM_RAM_BASEADDR		0xFFFC0000U
+#define XPS_FPGA_AXI_S0_BASEADDR	0x40000000U
+#define XPS_FPGA_AXI_S1_BASEADDR	0x80000000U
+#define XPS_IOU_S_SWITCH_BASEADDR	0xE0000000U
+#define XPS_PERIPH_APB_BASEADDR		0xF8000000U
+
+/* Shared Peripheral Interrupts (SPI) */
+#define XPS_CORE_PARITY0_INT_ID		32U
+#define XPS_CORE_PARITY1_INT_ID		33U
+#define XPS_L2CC_INT_ID			34U
+#define XPS_OCMINTR_INT_ID		35U
+#define XPS_ECC_INT_ID			36U
+#define XPS_PMU0_INT_ID			37U
+#define XPS_PMU1_INT_ID			38U
+#define XPS_SYSMON_INT_ID		39U
+#define XPS_DVC_INT_ID			40U
+#define XPS_WDT_INT_ID			41U
+#define XPS_TTC0_0_INT_ID		42U
+#define XPS_TTC0_1_INT_ID		43U
+#define XPS_TTC0_2_INT_ID 		44U
+#define XPS_DMA0_ABORT_INT_ID		45U
+#define XPS_DMA0_INT_ID			46U
+#define XPS_DMA1_INT_ID			47U
+#define XPS_DMA2_INT_ID			48U
+#define XPS_DMA3_INT_ID			49U
+#define XPS_SMC_INT_ID			50U
+#define XPS_QSPI_INT_ID			51U
+#define XPS_GPIO_INT_ID			52U
+#define XPS_USB0_INT_ID			53U
+#define XPS_GEM0_INT_ID			54U
+#define XPS_GEM0_WAKE_INT_ID		55U
+#define XPS_SDIO0_INT_ID		56U
+#define XPS_I2C0_INT_ID			57U
+#define XPS_SPI0_INT_ID			58U
+#define XPS_UART0_INT_ID		59U
+#define XPS_CAN0_INT_ID			60U
+#define XPS_FPGA0_INT_ID		61U
+#define XPS_FPGA1_INT_ID		62U
+#define XPS_FPGA2_INT_ID		63U
+#define XPS_FPGA3_INT_ID		64U
+#define XPS_FPGA4_INT_ID		65U
+#define XPS_FPGA5_INT_ID		66U
+#define XPS_FPGA6_INT_ID		67U
+#define XPS_FPGA7_INT_ID		68U
+#define XPS_TTC1_0_INT_ID		69U
+#define XPS_TTC1_1_INT_ID		70U
+#define XPS_TTC1_2_INT_ID		71U
+#define XPS_DMA4_INT_ID			72U
+#define XPS_DMA5_INT_ID			73U
+#define XPS_DMA6_INT_ID			74U
+#define XPS_DMA7_INT_ID			75U
+#define XPS_USB1_INT_ID			76U
+#define XPS_GEM1_INT_ID			77U
+#define XPS_GEM1_WAKE_INT_ID		78U
+#define XPS_SDIO1_INT_ID		79U
+#define XPS_I2C1_INT_ID			80U
+#define XPS_SPI1_INT_ID			81U
+#define XPS_UART1_INT_ID		82U
+#define XPS_CAN1_INT_ID			83U
+#define XPS_FPGA8_INT_ID		84U
+#define XPS_FPGA9_INT_ID		85U
+#define XPS_FPGA10_INT_ID		86U
+#define XPS_FPGA11_INT_ID		87U
+#define XPS_FPGA12_INT_ID		88U
+#define XPS_FPGA13_INT_ID		89U
+#define XPS_FPGA14_INT_ID		90U
+#define XPS_FPGA15_INT_ID		91U
+
+/* Private Peripheral Interrupts (PPI) */
+#define XPS_GLOBAL_TMR_INT_ID		27U	/* SCU Global Timer interrupt */
+#define XPS_FIQ_INT_ID			28U	/* FIQ from FPGA fabric */
+#define XPS_SCU_TMR_INT_ID		29U	/* SCU Private Timer interrupt */
+#define XPS_SCU_WDT_INT_ID		30U	/* SCU Private WDT interrupt */
+#define XPS_IRQ_INT_ID			31U	/* IRQ from FPGA fabric */
+
+
+/* REDEFINES for TEST APP */
+/* Definitions for UART */
+#define XPAR_PS7_UART_0_INTR		XPS_UART0_INT_ID
+#define XPAR_PS7_UART_1_INTR		XPS_UART1_INT_ID
+#define XPAR_PS7_USB_0_INTR		XPS_USB0_INT_ID
+#define XPAR_PS7_USB_1_INTR		XPS_USB1_INT_ID
+#define XPAR_PS7_I2C_0_INTR		XPS_I2C0_INT_ID
+#define XPAR_PS7_I2C_1_INTR		XPS_I2C1_INT_ID
+#define XPAR_PS7_SPI_0_INTR		XPS_SPI0_INT_ID
+#define XPAR_PS7_SPI_1_INTR		XPS_SPI1_INT_ID
+#define XPAR_PS7_CAN_0_INTR		XPS_CAN0_INT_ID
+#define XPAR_PS7_CAN_1_INTR		XPS_CAN1_INT_ID
+#define XPAR_PS7_GPIO_0_INTR		XPS_GPIO_INT_ID
+#define XPAR_PS7_ETHERNET_0_INTR	XPS_GEM0_INT_ID
+#define XPAR_PS7_ETHERNET_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_1_INTR	XPS_GEM1_INT_ID
+#define XPAR_PS7_ETHERNET_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
+#define XPAR_PS7_QSPI_0_INTR		XPS_QSPI_INT_ID
+#define XPAR_PS7_WDT_0_INTR		XPS_WDT_INT_ID
+#define XPAR_PS7_SCUWDT_0_INTR		XPS_SCU_WDT_INT_ID
+#define XPAR_PS7_SCUTIMER_0_INTR	XPS_SCU_TMR_INT_ID
+#define XPAR_PS7_XADC_0_INTR		XPS_SYSMON_INT_ID
+#define XPAR_PS7_TTC_0_INTR         XPS_TTC0_0_INT_ID
+#define XPAR_PS7_TTC_1_INTR         XPS_TTC0_1_INT_ID
+#define XPAR_PS7_TTC_2_INTR         XPS_TTC0_2_INT_ID
+#define XPAR_PS7_TTC_3_INTR         XPS_TTC1_0_INT_ID
+#define XPAR_PS7_TTC_4_INTR         XPS_TTC1_1_INT_ID
+#define XPAR_PS7_TTC_5_INTR         XPS_TTC1_2_INT_ID
+
+#define XPAR_XADCPS_INT_ID		XPS_SYSMON_INT_ID
+
+/* For backwards compatibilty */
+#define XPAR_XUARTPS_0_CLOCK_HZ		XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
+#define XPAR_XUARTPS_1_CLOCK_HZ		XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
+#define XPAR_XTTCPS_0_CLOCK_HZ		XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_1_CLOCK_HZ		XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_2_CLOCK_HZ		XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_3_CLOCK_HZ		XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_4_CLOCK_HZ		XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_5_CLOCK_HZ		XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
+#define XPAR_XIICPS_0_CLOCK_HZ		XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
+#define XPAR_XIICPS_1_CLOCK_HZ		XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
+
+#define XPAR_XQSPIPS_0_CLOCK_HZ		XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
+
+#define XPAR_SCUTIMER_DEVICE_ID		0U
+#define XPAR_SCUWDT_DEVICE_ID		0U
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */

src/APP/Aufgabe3/ps7/core0/linker/lscript.ld

@@ -0,0 +1,291 @@
+/*******************************************************************/
+/*                                                                 */
+/* This file is automatically generated by linker script generator.*/
+/*                                                                 */
+/* Version:                                 */
+/*                                                                 */
+/* Copyright (c) 2010-2016 Xilinx, Inc.  All rights reserved.      */
+/*                                                                 */
+/* Description : Cortex-A9 Linker Script                          */
+/*                                                                 */
+/*******************************************************************/
+
+_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
+_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
+
+_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
+_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
+_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
+_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
+_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
+
+/* Define Memories in the system */
+
+MEMORY
+{
+   axi_bram_ctrl_0_Mem0 : ORIGIN = 0x40000000, LENGTH = 0x2000
+   ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x3FF00000
+   ps7_qspi_linear_0 : ORIGIN = 0xFC000000, LENGTH = 0x2000000
+   ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000
+   ps7_ram_1 : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00
+   ps7_ddr_core_0 : ORIGIN = 0x100000, LENGTH = 0x700000
+   ps7_ddr_core_1 : ORIGIN = 0x800000, LENGTH = 0x800000
+}
+
+/* Specify the default entry point to the program */
+
+ENTRY(_vector_table)
+
+/* Define the sections, and where they are mapped in memory */
+
+SECTIONS
+{
+.text : {
+   KEEP (*(.vectors))
+   *(.boot)
+   *(.text)
+   *(.text.*)
+   *(.gnu.linkonce.t.*)
+   *(.plt)
+   *(.gnu_warning)
+   *(.gcc_execpt_table)
+   *(.glue_7)
+   *(.glue_7t)
+   *(.vfp11_veneer)
+   *(.ARM.extab)
+   *(.gnu.linkonce.armextab.*)
+} > ps7_ddr_core_0
+
+.init : {
+   KEEP (*(.init))
+} > ps7_ddr_core_0
+
+.fini : {
+   KEEP (*(.fini))
+} > ps7_ddr_core_0
+
+.rodata : {
+   __rodata_start = .;
+   *(.rodata)
+   *(.rodata.*)
+   *(.gnu.linkonce.r.*)
+   __rodata_end = .;
+} > ps7_ddr_core_0
+
+.rodata1 : {
+   __rodata1_start = .;
+   *(.rodata1)
+   *(.rodata1.*)
+   __rodata1_end = .;
+} > ps7_ddr_core_0
+
+.sdata2 : {
+   __sdata2_start = .;
+   *(.sdata2)
+   *(.sdata2.*)
+   *(.gnu.linkonce.s2.*)
+   __sdata2_end = .;
+} > ps7_ddr_core_0
+
+.sbss2 : {
+   __sbss2_start = .;
+   *(.sbss2)
+   *(.sbss2.*)
+   *(.gnu.linkonce.sb2.*)
+   __sbss2_end = .;
+} > ps7_ddr_core_0
+
+.data : {
+   __data_start = .;
+   *(.data)
+   *(.data.*)
+   *(.gnu.linkonce.d.*)
+   *(.jcr)
+   *(.got)
+   *(.got.plt)
+   __data_end = .;
+} > ps7_ddr_core_0
+
+.data1 : {
+   __data1_start = .;
+   *(.data1)
+   *(.data1.*)
+   __data1_end = .;
+} > ps7_ddr_core_0
+
+.got : {
+   *(.got)
+} > ps7_ddr_core_0
+
+.ctors : {
+   __CTOR_LIST__ = .;
+   ___CTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.ctors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
+   KEEP (*(SORT(.ctors.*)))
+   KEEP (*(.ctors))
+   __CTOR_END__ = .;
+   ___CTORS_END___ = .;
+} > ps7_ddr_core_0
+
+.dtors : {
+   __DTOR_LIST__ = .;
+   ___DTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.dtors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
+   KEEP (*(SORT(.dtors.*)))
+   KEEP (*(.dtors))
+   __DTOR_END__ = .;
+   ___DTORS_END___ = .;
+} > ps7_ddr_core_0
+
+.fixup : {
+   __fixup_start = .;
+   *(.fixup)
+   __fixup_end = .;
+} > ps7_ddr_core_0
+
+.eh_frame : {
+   *(.eh_frame)
+} > ps7_ddr_core_0
+
+.eh_framehdr : {
+   __eh_framehdr_start = .;
+   *(.eh_framehdr)
+   __eh_framehdr_end = .;
+} > ps7_ddr_core_0
+
+.gcc_except_table : {
+   *(.gcc_except_table)
+} > ps7_ddr_core_0
+
+.mmu_tbl (ALIGN(16384)) : {
+   __mmu_tbl_start = .;
+   *(.mmu_tbl)
+   __mmu_tbl_end = .;
+} > ps7_ddr_core_0
+
+.ARM.exidx : {
+   __exidx_start = .;
+   *(.ARM.exidx*)
+   *(.gnu.linkonce.armexidix.*.*)
+   __exidx_end = .;
+} > ps7_ddr_core_0
+
+.preinit_array : {
+   __preinit_array_start = .;
+   KEEP (*(SORT(.preinit_array.*)))
+   KEEP (*(.preinit_array))
+   __preinit_array_end = .;
+} > ps7_ddr_core_0
+
+.init_array : {
+   __init_array_start = .;
+   KEEP (*(SORT(.init_array.*)))
+   KEEP (*(.init_array))
+   __init_array_end = .;
+} > ps7_ddr_core_0
+
+.fini_array : {
+   __fini_array_start = .;
+   KEEP (*(SORT(.fini_array.*)))
+   KEEP (*(.fini_array))
+   __fini_array_end = .;
+} > ps7_ddr_core_0
+
+.ARM.attributes : {
+   __ARM.attributes_start = .;
+   *(.ARM.attributes)
+   __ARM.attributes_end = .;
+} > ps7_ddr_core_0
+
+.sdata : {
+   __sdata_start = .;
+   *(.sdata)
+   *(.sdata.*)
+   *(.gnu.linkonce.s.*)
+   __sdata_end = .;
+} > ps7_ddr_core_0
+
+.sbss (NOLOAD) : {
+   __sbss_start = .;
+   *(.sbss)
+   *(.sbss.*)
+   *(.gnu.linkonce.sb.*)
+   __sbss_end = .;
+} > ps7_ddr_core_0
+
+.tdata : {
+   __tdata_start = .;
+   *(.tdata)
+   *(.tdata.*)
+   *(.gnu.linkonce.td.*)
+   __tdata_end = .;
+} > ps7_ddr_core_0
+
+.tbss : {
+   __tbss_start = .;
+   *(.tbss)
+   *(.tbss.*)
+   *(.gnu.linkonce.tb.*)
+   __tbss_end = .;
+} > ps7_ddr_core_0
+
+.bss (NOLOAD) : {
+   __bss_start = .;
+   *(.bss)
+   *(.bss.*)
+   *(.gnu.linkonce.b.*)
+   *(COMMON)
+   __bss_end = .;
+} > ps7_ddr_core_0
+
+_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
+
+_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
+
+/* Generate Stack and Heap definitions */
+
+.heap (NOLOAD) : {
+   . = ALIGN(16);
+   _heap = .;
+   HeapBase = .;
+   _heap_start = .;
+   . += _HEAP_SIZE;
+   _heap_end = .;
+   HeapLimit = .;
+} > ps7_ddr_core_0
+
+.stack (NOLOAD) : {
+   . = ALIGN(16);
+   _stack_end = .;
+   . += _STACK_SIZE;
+   . = ALIGN(16);
+   _stack = .;
+   __stack = _stack;
+   . = ALIGN(16);
+   _irq_stack_end = .;
+   . += _IRQ_STACK_SIZE;
+   . = ALIGN(16);
+   __irq_stack = .;
+   _supervisor_stack_end = .;
+   . += _SUPERVISOR_STACK_SIZE;
+   . = ALIGN(16);
+   __supervisor_stack = .;
+   _abort_stack_end = .;
+   . += _ABORT_STACK_SIZE;
+   . = ALIGN(16);
+   __abort_stack = .;
+   _fiq_stack_end = .;
+   . += _FIQ_STACK_SIZE;
+   . = ALIGN(16);
+   __fiq_stack = .;
+   _undef_stack_end = .;
+   . += _UNDEF_STACK_SIZE;
+   . = ALIGN(16);
+   __undef_stack = .;
+} > ps7_ddr_core_0
+
+_end = .;
+}
+

src/APP/Aufgabe3/ps7/core0/main.c

@@ -0,0 +1,31 @@
+/*
+ ============================================================================
+ Name        : main.c
+ Author      : Laurenz Borchers
+ Version     :
+ Copyright   : Copyright belongs to the authors
+ Description : Hello World in C, Praktikum Aufgabe 3
+ ============================================================================
+ */
+
+#include <mmu.h>
+#include <stdio.h>
+#include "ucos_uartps.h"
+#include "ucos_ii.h"
+#include "ucos_bsp.h"
+#include "xil_testmem.h"
+#include "xil_printf.h"
+#include "ttc_timer.h"
+
+
+void InitDoneCallback(void * p_arg) {
+	(void) p_arg;
+	UCOS_Print("OS started!\r\n");
+}
+
+int main(void) {
+	MMUInit();
+	UCOSStartup(InitDoneCallback);
+	while (1)
+		;
+}